drm/i915: [GEN7] Use HW scheduler for fixed function shaders

commit a1e969e0332de7a430e62822cee8f2ec8d83cd7c upstream.

This originally started as a patch from Bernard as a way of simply
setting the VS scheduler. After submitting the RFC patch, we decided to
also modify the DS scheduler. To be most explicit, I've made the patch
explicitly set all scheduler modes, and included the defines for other
modes (in case someone feels frisky later).

The rest of the story gets a bit weird. The first version of the patch
showed an almost unbelievable performance improvement. Since rebasing my
branch it appears the performance improvement has gone, unfortunately.
But setting these bits seem to be the right thing to do given that the
docs describe corruption that can occur with the default settings.

In summary, I am seeing no more perf improvements (or regressions) in my
limited testing, but we believe this should be set to prevent rendering
corruption, therefore cc stable.

v1: Clear bit 4 also (Ken + Eugeni)
Do a full clear + set of the bits we want (Me).

Cc: Bernard Kilarski <bernard.r.kilarski@intel.com>
Reviewed-by (RFC): Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b05c256d496b1e2f947c8b52df94f8182f5aa392..387b2b34e93fc021c9fd86ec793506562144af39 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -537,6 +537,21 @@
 
 #define GEN6_BSD_RNCID                 0x12198
 
+#define GEN7_FF_THREAD_MODE            0x20a0
+#define   GEN7_FF_SCHED_MASK           0x0077070
+#define   GEN7_FF_TS_SCHED_HS1         (0x5<<16)
+#define   GEN7_FF_TS_SCHED_HS0         (0x3<<16)
+#define   GEN7_FF_TS_SCHED_LOAD_BALANCE        (0x1<<16)
+#define   GEN7_FF_TS_SCHED_HW          (0x0<<16) /* Default */
+#define   GEN7_FF_VS_SCHED_HS1         (0x5<<12)
+#define   GEN7_FF_VS_SCHED_HS0         (0x3<<12)
+#define   GEN7_FF_VS_SCHED_LOAD_BALANCE        (0x1<<12) /* Default */
+#define   GEN7_FF_VS_SCHED_HW          (0x0<<12)
+#define   GEN7_FF_DS_SCHED_HS1         (0x5<<4)
+#define   GEN7_FF_DS_SCHED_HS0         (0x3<<4)
+#define   GEN7_FF_DS_SCHED_LOAD_BALANCE        (0x1<<4)  /* Default */
+#define   GEN7_FF_DS_SCHED_HW          (0x0<<4)
+
 /*
  * Framebuffer compression (915+ only)
  */

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index f150a15279ea857de6f995829b64ed9d526abee7..a040ca0ae20c2bd6e80c91e5237ebd2eddaa74f7 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7451,6 +7451,18 @@ static void gen6_init_clock_gating(struct drm_device *dev)
                           DISPPLANE_TRICKLE_FEED_DISABLE);
 }
 
+static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
+{
+       uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
+
+       reg &= ~GEN7_FF_SCHED_MASK;
+       reg |= GEN7_FF_TS_SCHED_HW;
+       reg |= GEN7_FF_VS_SCHED_HW;
+       reg |= GEN7_FF_DS_SCHED_HW;
+
+       I915_WRITE(GEN7_FF_THREAD_MODE, reg);
+}
+
 static void ivybridge_init_clock_gating(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -7597,6 +7609,8 @@ static void ironlake_teardown_rc6(struct drm_device *dev)
                drm_gem_object_unreference(&dev_priv->pwrctx->base);
                dev_priv->pwrctx = NULL;
        }
+
+       gen7_setup_fixed_func_scheduler(dev_priv);
 }
 
 static void ironlake_disable_rc6(struct drm_device *dev)