drm/i915/bxt: add DDI port HW readout support

Add support for reading out the HW state for DDI ports. Since the actual
programming is very similar to the CHV/VLV DPIO PLL programming we can
reuse much of the logic from there.

This fixes the state checker failures I saw on my BXT with HDMI output.

v2:
- rebased on v2 of patch 4/5

Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4d8ef2de4374c468ea250bdc88c252cbdf9a0843..42ba1ef641d8fc638b0984ea104786dfb6c878ba 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1170,10 +1170,12 @@ enum skl_disp_power_wells {
 #define _PORT_PLL_EBB_0_A              0x162034
 #define _PORT_PLL_EBB_0_B              0x6C034
 #define _PORT_PLL_EBB_0_C              0x6C340
-#define   PORT_PLL_P1_MASK             (0x07 << 13)
-#define   PORT_PLL_P1(x)               ((x)  << 13)
-#define   PORT_PLL_P2_MASK             (0x1f << 8)
-#define   PORT_PLL_P2(x)               ((x)  << 8)
+#define   PORT_PLL_P1_SHIFT            13
+#define   PORT_PLL_P1_MASK             (0x07 << PORT_PLL_P1_SHIFT)
+#define   PORT_PLL_P1(x)               ((x)  << PORT_PLL_P1_SHIFT)
+#define   PORT_PLL_P2_SHIFT            8
+#define   PORT_PLL_P2_MASK             (0x1f << PORT_PLL_P2_SHIFT)
+#define   PORT_PLL_P2(x)               ((x)  << PORT_PLL_P2_SHIFT)
 #define BXT_PORT_PLL_EBB_0(port)       _PORT3(port, _PORT_PLL_EBB_0_A, \
                                                _PORT_PLL_EBB_0_B,      \
                                                _PORT_PLL_EBB_0_C)
@@ -1193,8 +1195,9 @@ enum skl_disp_power_wells {
 /* PORT_PLL_0_A */
 #define   PORT_PLL_M2_MASK             0xFF
 /* PORT_PLL_1_A */
-#define   PORT_PLL_N_MASK              (0x0F << 8)
-#define   PORT_PLL_N(x)                        ((x) << 8)
+#define   PORT_PLL_N_SHIFT             8
+#define   PORT_PLL_N_MASK              (0x0F << PORT_PLL_N_SHIFT)
+#define   PORT_PLL_N(x)                        ((x) << PORT_PLL_N_SHIFT)
 /* PORT_PLL_2_A */
 #define   PORT_PLL_M2_FRAC_MASK                0x3FFFFF
 /* PORT_PLL_3_A */

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index cf2896da8ad80681a503ca8aea203d6f52f9b191..cef9709fa2baecdf5679d7faadd82bea4bb31a84 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1140,8 +1140,26 @@ static void hsw_ddi_clock_get(struct intel_encoder *encoder,
 static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
                                enum intel_dpll_id dpll)
 {
-       /* FIXME formula not available in bspec */
-       return 0;
+       struct intel_shared_dpll *pll;
+       struct intel_dpll_hw_state *state;
+       intel_clock_t clock;
+
+       /* For DDI ports we always use a shared PLL. */
+       if (WARN_ON(dpll == DPLL_ID_PRIVATE))
+               return 0;
+
+       pll = &dev_priv->shared_dplls[dpll];
+       state = &pll->config.hw_state;
+
+       clock.m1 = 2;
+       clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
+       if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
+               clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
+       clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
+       clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
+       clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
+
+       return chv_calc_dpll_params(100000, &clock);
 }
 
 static void bxt_ddi_clock_get(struct intel_encoder *encoder,