; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
%1 = load <2 x i8>* %loadaddr
%2 = zext <2 x i8> %1 to <2 x i64>
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
%1 = load <2 x i16>* %loadaddr
%2 = zext <2 x i16> %1 to <2 x i64>
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
-; CHECK-NEXT: vuzp.16 [[REG]], d17
-; CHECK-NEXT: vrev32.16 [[REG]], d17
+; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}}
+; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]
; CHECK-NEXT: bx lr
%1 = load <2 x i8>* %loadaddr
; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
-; CHECK-NEXT: vst1.64 {[[REG]], d17}, [r1]
+; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
; CHECK-NEXT: bx lr
%1 = load <4 x i8>* %loadaddr
%2 = zext <4 x i8> %1 to <4 x i32>