ARM NEON VCLE is an alias for VCGE w/ the source operands reversed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146699 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrNEON.td b/lib/Target/ARM/ARMInstrNEON.td
index b5b39b7cb373639b191b1b94b7c73c6183d69355..ecf12e96616bd250e4cbe24c3d3b58a0d7987699 100644 (file)
--- a/lib/Target/ARM/ARMInstrNEON.td
+++ b/lib/Target/ARM/ARMInstrNEON.td
@@ -5786,6 +5786,38 @@ defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
                          (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
 
+// VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
+// D-register versions.
+def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
+                    (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
+                    (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
+                    (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
+                    (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
+                    (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
+                    (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
+                    (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
+// Q-register versions.
+def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
+                    (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
+                    (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
+                    (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
+                    (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
+                    (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
+                    (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
+                    (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
+
 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
 // D-register versions.
 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",

diff --git a/test/MC/ARM/neon-cmp-encoding.s b/test/MC/ARM/neon-cmp-encoding.s
index 57de2db9c62156717da0135cc079dabedf089817..b3aedb8e52ecd866911d66eb4572dccec35dae76 100644 (file)
--- a/test/MC/ARM/neon-cmp-encoding.s
+++ b/test/MC/ARM/neon-cmp-encoding.s
@@ -144,3 +144,33 @@
 @ CHECK: vcgt.u16      d12, d3, d13    @ encoding: [0x0d,0xc3,0x13,0xf3]
 @ CHECK: vcgt.u32      d12, d3, d13    @ encoding: [0x0d,0xc3,0x23,0xf3]
 @ CHECK: vcgt.f32      d12, d3, d13    @ encoding: [0x0d,0xce,0x23,0xf3]
+
+       vcle.s8 d16, d16, d17
+       vcle.s16 d16, d16, d17
+       vcle.s32 d16, d16, d17
+       vcle.u8 d16, d16, d17
+       vcle.u16 d16, d16, d17
+       vcle.u32 d16, d16, d17
+       vcle.f32 d16, d16, d17
+       vcle.s8 q8, q8, q9
+       vcle.s16 q8, q8, q9
+       vcle.s32 q8, q8, q9
+       vcle.u8 q8, q8, q9
+       vcle.u16 q8, q8, q9
+       vcle.u32 q8, q8, q9
+       vcle.f32 q8, q8, q9
+
+@ CHECK: vcge.s8       d16, d17, d16           @ encoding: [0xb0,0x03,0x41,0xf2]
+@ CHECK: vcge.s16      d16, d17, d16   @ encoding: [0xb0,0x03,0x51,0xf2]
+@ CHECK: vcge.s32      d16, d17, d16   @ encoding: [0xb0,0x03,0x61,0xf2]
+@ CHECK: vcge.u8       d16, d17, d16           @ encoding: [0xb0,0x03,0x41,0xf3]
+@ CHECK: vcge.u16      d16, d17, d16   @ encoding: [0xb0,0x03,0x51,0xf3]
+@ CHECK: vcge.u32      d16, d17, d16   @ encoding: [0xb0,0x03,0x61,0xf3]
+@ CHECK: vcge.f32      d16, d17, d16   @ encoding: [0xa0,0x0e,0x41,0xf3]
+@ CHECK: vcge.s8       q8, q9, q8              @ encoding: [0xf0,0x03,0x42,0xf2]
+@ CHECK: vcge.s16      q8, q9, q8      @ encoding: [0xf0,0x03,0x52,0xf2]
+@ CHECK: vcge.s32      q8, q9, q8      @ encoding: [0xf0,0x03,0x62,0xf2]
+@ CHECK: vcge.u8       q8, q9, q8              @ encoding: [0xf0,0x03,0x42,0xf3]
+@ CHECK: vcge.u16      q8, q9, q8      @ encoding: [0xf0,0x03,0x52,0xf3]
+@ CHECK: vcge.u32      q8, q9, q8      @ encoding: [0xf0,0x03,0x62,0xf3]
+@ CHECK: vcge.f32      q8, q9, q8      @ encoding: [0xe0,0x0e,0x42,0xf3]