Pseudo, NoItinerary,
"dmb", "",
[(ARMMemBarrier)]>,
- Requires<[HasV7]> {
+ Requires<[IsARM, HasV7]> {
let Inst{31-4} = 0xf57ff05;
// FIXME: add support for options other than a full system DMB
let Inst{3-0} = 0b1111;
Pseudo, NoItinerary,
"dsb", "",
[(ARMSyncBarrier)]>,
- Requires<[HasV7]> {
+ Requires<[IsARM, HasV7]> {
let Inst{31-4} = 0xf57ff04;
// FIXME: add support for options other than a full system DSB
let Inst{3-0} = 0b1111;
def t2Int_MemBarrierV7 : AInoP<(outs), (ins),
Pseudo, NoItinerary,
"dmb", "",
- [(ARMMemBarrier)]> {
+ [(ARMMemBarrier)]>,
+ Requires<[IsThumb2]> {
// FIXME: add support for options other than a full system DMB
}
def t2Int_SyncBarrierV7 : AInoP<(outs), (ins),
Pseudo, NoItinerary,
"dsb", "",
- [(ARMSyncBarrier)]> {
+ [(ARMSyncBarrier)]>,
+ Requires<[IsThumb2]> {
// FIXME: add support for options other than a full system DSB
}
}