Fix a bogus srem rule - a negative value srem'd by a power-of-2

can have a non-negative result; for example, -16%16 is 0. Also,
clarify the related comments. This fixes PR2670.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54767 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Analysis/ValueTracking.cpp b/lib/Analysis/ValueTracking.cpp
index e35f0d0fcedd4bc98907851db8fa9f8c965bde63..3a04f5eb869c8dccee19368374fd5b52f9a82348 100644 (file)
--- a/lib/Analysis/ValueTracking.cpp
+++ b/lib/Analysis/ValueTracking.cpp
@@ -369,15 +369,13 @@ void llvm::ComputeMaskedBits(Value *V, const APInt &Mask,
         ComputeMaskedBits(I->getOperand(0), Mask2, KnownZero2, KnownOne2, TD, 
                           Depth+1);
 
-        // The sign of a remainder is equal to the sign of the first
-        // operand (zero being positive).
+        // If the sign bit of the first operand is zero, the sign bit of
+        // the result is zero. If the first operand has no one bits below
+        // the second operand's single 1 bit, its sign will be zero.
         if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
           KnownZero2 |= ~LowBits;
-        else if (KnownOne2[BitWidth-1])
-          KnownOne2 |= ~LowBits;
 
         KnownZero |= KnownZero2 & Mask;
-        KnownOne |= KnownOne2 & Mask;
 
         assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 
       }

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 144dc6e198fc5b7aaafa4013f8b205bc5d8039d9..9eab89ffb03aa18d9d64ce640b4a5aa01ba3c1d9 100644 (file)
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1656,15 +1656,13 @@ void SelectionDAG::ComputeMaskedBits(SDValue Op, const APInt &Mask,
         APInt Mask2 = LowBits | APInt::getSignBit(BitWidth);
         ComputeMaskedBits(Op.getOperand(0), Mask2,KnownZero2,KnownOne2,Depth+1);
 
-        // The sign of a remainder is equal to the sign of the first
-        // operand (zero being positive).
+        // If the sign bit of the first operand is zero, the sign bit of
+        // the result is zero. If the first operand has no one bits below
+        // the second operand's single 1 bit, its sign will be zero.
         if (KnownZero2[BitWidth-1] || ((KnownZero2 & LowBits) == LowBits))
           KnownZero2 |= ~LowBits;
-        else if (KnownOne2[BitWidth-1])
-          KnownOne2 |= ~LowBits;
 
         KnownZero |= KnownZero2 & Mask;
-        KnownOne |= KnownOne2 & Mask;
 
         assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?");
       }

diff --git a/lib/Transforms/Scalar/InstructionCombining.cpp b/lib/Transforms/Scalar/InstructionCombining.cpp
index bdea6e40d21e2fd527d6334b8505cc129a1f3f59..74b88b9afc69d3a8974e7471b39c3a64457b8a00 100644 (file)
--- a/lib/Transforms/Scalar/InstructionCombining.cpp
+++ b/lib/Transforms/Scalar/InstructionCombining.cpp
@@ -1266,11 +1266,8 @@ bool InstCombiner::SimplifyDemandedBits(Value *V, APInt DemandedMask,
 
         if (LHSKnownZero[BitWidth-1] || ((LHSKnownZero & LowBits) == LowBits))
           LHSKnownZero |= ~LowBits;
-        else if (LHSKnownOne[BitWidth-1])
-          LHSKnownOne |= ~LowBits;
 
         KnownZero |= LHSKnownZero & DemandedMask;
-        KnownOne |= LHSKnownOne & DemandedMask;
 
         assert((KnownZero & KnownOne) == 0&&"Bits known to be one AND zero?"); 
       }

diff --git a/test/Transforms/InstCombine/srem1.ll b/test/Transforms/InstCombine/srem1.ll
new file mode 100644 (file)
index 0000000..ee59d3e
--- /dev/null
+++ b/test/Transforms/InstCombine/srem1.ll
@@ -0,0 +1,18 @@
+; RUN: llvm-as < %s | opt -instcombine
+; PR2670
+
+@g_127 = external global i32           ; <i32*> [#uses=1]
+
+define i32 @func_56(i32 %p_58, i32 %p_59, i32 %p_61, i16 signext %p_62) nounwind {
+entry:
+       %call = call i32 (...)* @rshift_s_s( i32 %p_61, i32 1 )         ; <i32> [#uses=1]
+       %conv = sext i32 %call to i64           ; <i64> [#uses=1]
+       %or = or i64 -1734012817166602727, %conv                ; <i64> [#uses=1]
+       %rem = srem i64 %or, 1          ; <i64> [#uses=1]
+       %cmp = icmp eq i64 %rem, 1              ; <i1> [#uses=1]
+       %cmp.ext = zext i1 %cmp to i32          ; <i32> [#uses=1]
+       store i32 %cmp.ext, i32* @g_127
+       ret i32 undef
+}
+
+declare i32 @rshift_s_s(...)