ARM: mvebu: fix second and third PCIe unit of Armada XP mv78260

commit 2163e61c92d9337e721a0d067d88ae62b52e0d3e upstream.

mv78260 flavour of Marvell Armada XP SoC has 3 PCIe units. The
two first units are both x4 and quad x1 capable. The third unit
is only x4 capable. This patch fixes mv78260 .dtsi to reflect
those capabilities.

Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
index f4029f015aff8008fee6b8eb98db44e139d48670..55cdd58c155f03f9af01cb61744f7d1c0328f1de 100644 (file)
--- a/arch/arm/boot/dts/armada-xp-mv78260.dtsi
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -101,7 +101,7 @@
                        /*
                         * MV78260 has 3 PCIe units Gen2.0: Two units can be
                         * configured as x4 or quad x1 lanes. One unit is
-                        * x4/x1.
+                        * x4 only.
                         */
                        pcie-controller {
                                compatible = "marvell,armada-xp-pcie";
@@ -119,7 +119,9 @@
                                        0x82000000 0 0x48000 0x48000 0 0x00002000   /* Port 0.2 registers */
                                        0x82000000 0 0x4c000 0x4c000 0 0x00002000   /* Port 0.3 registers */
                                        0x82000000 0 0x80000 0x80000 0 0x00002000   /* Port 1.0 registers */
-                                       0x82000000 0 0x82000 0x82000 0 0x00002000   /* Port 3.0 registers */
+                                       0x82000000 0 0x84000 0x84000 0 0x00002000   /* Port 1.1 registers */
+                                       0x82000000 0 0x88000 0x88000 0 0x00002000   /* Port 1.2 registers */
+                                       0x82000000 0 0x8c000 0x8c000 0 0x00002000   /* Port 1.3 registers */
                                        0x82000000 0 0xe0000000 0xe0000000 0 0x08000000   /* non-prefetchable memory */
                                        0x81000000 0 0    0xe8000000 0 0x00100000>; /* downstream I/O */
 
@@ -187,35 +189,83 @@
                                        status = "disabled";
                                };
 
-                               pcie@9,0 {
+                               pcie@5,0 {
                                        device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
-                                       reg = <0x4800 0 0 0 0>;
+                                       assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
+                                       reg = <0x2800 0 0 0 0>;
                                        #address-cells = <3>;
                                        #size-cells = <2>;
                                        #interrupt-cells = <1>;
                                        ranges;
                                        interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 99>;
-                                       marvell,pcie-port = <2>;
+                                       interrupt-map = <0 0 0 0 &mpic 62>;
+                                       marvell,pcie-port = <1>;
                                        marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 26>;
+                                       clocks = <&gateclk 9>;
+                                       status = "disabled";
+                               };
+
+                               pcie@6,0 {
+                                       device_type = "pci";
+                                       assigned-addresses = <0x82000800 0 0x84000 0 0x2000>;
+                                       reg = <0x3000 0 0 0 0>;
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       #interrupt-cells = <1>;
+                                       ranges;
+                                       interrupt-map-mask = <0 0 0 0>;
+                                       interrupt-map = <0 0 0 0 &mpic 63>;
+                                       marvell,pcie-port = <1>;
+                                       marvell,pcie-lane = <1>;
+                                       clocks = <&gateclk 10>;
+                                       status = "disabled";
+                               };
+
+                               pcie@7,0 {
+                                       device_type = "pci";
+                                       assigned-addresses = <0x82000800 0 0x88000 0 0x2000>;
+                                       reg = <0x3800 0 0 0 0>;
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       #interrupt-cells = <1>;
+                                       ranges;
+                                       interrupt-map-mask = <0 0 0 0>;
+                                       interrupt-map = <0 0 0 0 &mpic 64>;
+                                       marvell,pcie-port = <1>;
+                                       marvell,pcie-lane = <2>;
+                                       clocks = <&gateclk 11>;
                                        status = "disabled";
                                };
 
-                               pcie@10,0 {
+                               pcie@8,0 {
                                        device_type = "pci";
-                                       assigned-addresses = <0x82000800 0 0x82000 0 0x2000>;
-                                       reg = <0x5000 0 0 0 0>;
+                                       assigned-addresses = <0x82000800 0 0x8c000 0 0x2000>;
+                                       reg = <0x4000 0 0 0 0>;
                                        #address-cells = <3>;
                                        #size-cells = <2>;
                                        #interrupt-cells = <1>;
                                        ranges;
                                        interrupt-map-mask = <0 0 0 0>;
-                                       interrupt-map = <0 0 0 0 &mpic 103>;
-                                       marvell,pcie-port = <3>;
+                                       interrupt-map = <0 0 0 0 &mpic 65>;
+                                       marvell,pcie-port = <1>;
+                                       marvell,pcie-lane = <3>;
+                                       clocks = <&gateclk 12>;
+                                       status = "disabled";
+                               };
+
+                               pcie@9,0 {
+                                       device_type = "pci";
+                                       assigned-addresses = <0x82000800 0 0x42000 0 0x2000>;
+                                       reg = <0x4800 0 0 0 0>;
+                                       #address-cells = <3>;
+                                       #size-cells = <2>;
+                                       #interrupt-cells = <1>;
+                                       ranges;
+                                       interrupt-map-mask = <0 0 0 0>;
+                                       interrupt-map = <0 0 0 0 &mpic 99>;
+                                       marvell,pcie-port = <2>;
                                        marvell,pcie-lane = <0>;
-                                       clocks = <&gateclk 27>;
+                                       clocks = <&gateclk 26>;
                                        status = "disabled";
                                };
                        };