Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversion

if profitable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107673 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 8b4d701fc71838114e1a51cfb57e2a189069797a..2ec5ad4ec0acb08a3009dee2e0ff9b133c4ec463 100644 (file)
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -718,6 +718,12 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
   if (SrcRC == ARM::DPR_8RegisterClass)
     SrcRC = ARM::DPR_VFP2RegisterClass;
 
+  // NEONMoveFixPass will convert VFP moves to NEON moves when profitable.
+  if (DestRC == ARM::DPR_VFP2RegisterClass)
+    DestRC = ARM::DPRRegisterClass;
+  if (SrcRC == ARM::DPR_VFP2RegisterClass)
+    SrcRC = ARM::DPRRegisterClass;
+
   // Allow QPR / QPR_VFP2 / QPR_8 cross-class copies.
   if (DestRC == ARM::QPR_VFP2RegisterClass ||
       DestRC == ARM::QPR_8RegisterClass)
@@ -750,10 +756,6 @@ ARMBaseInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
       Opc = (SrcRC == ARM::GPRRegisterClass ? ARM::VMOVSR : ARM::VMOVS);
     else if (DestRC == ARM::DPRRegisterClass)
       Opc = ARM::VMOVD;
-    else if (DestRC == ARM::DPR_VFP2RegisterClass ||
-             SrcRC == ARM::DPR_VFP2RegisterClass)
-      // Always use neon reg-reg move if source or dest is NEON-only regclass.
-      Opc = ARM::VMOVDneon;
     else if (DestRC == ARM::QPRRegisterClass)
       Opc = ARM::VMOVQ;
     else if (DestRC == ARM::QQPRRegisterClass)

diff --git a/test/CodeGen/ARM/vget_lane.ll b/test/CodeGen/ARM/vget_lane.ll
index bc10da09bb377e017056fc5743046dec9c6419b2..05e7f50909528be2fd2fe6159f7ed706bfe2f7e7 100644 (file)
--- a/test/CodeGen/ARM/vget_lane.ll
+++ b/test/CodeGen/ARM/vget_lane.ll
@@ -205,7 +205,7 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
 define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
 ;CHECK: test_vset_lanef32:
 ;CHECK: vmov.f32 s3, s0
-;CHECK: vmov d0, d1
+;CHECK: vmov.f64 d0, d1
 entry:
   %0 = insertelement <2 x float> %arg1_float32x2_t, float %arg0_float32_t, i32 1 ; <<2 x float>> [#uses=1]
   ret <2 x float> %0