Added X86 readport patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24879 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index 5ee107bfdb5aa427673456e611238ded6a1d178d..338b823b8d4964cb497fd031e383157a00e66824 100644 (file)
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -133,6 +133,10 @@ def SDTBr : SDTypeProfile<0, 1, [ // br
 
 def SDTRet : SDTypeProfile<0, 0, []>; // ret
 
+def SDTReadPort : SDTypeProfile<1, 1, [ // readport
+  SDTCisInt<0>, SDTCisInt<1>
+]>;
+
 def SDTWritePort : SDTypeProfile<0, 2, [ // writeport
   SDTCisInt<0>, SDTCisInt<1>
 ]>;
@@ -254,6 +258,7 @@ def selectcc   : SDNode<"ISD::SELECT_CC"  , SDTSelectCC>;
 def br         : SDNode<"ISD::BR"         , SDTBr,     [SDNPHasChain]>;
 def ret        : SDNode<"ISD::RET"        , SDTRet,    [SDNPHasChain]>;
 
+def readport   : SDNode<"ISD::READPORT"   , SDTReadPort,  [SDNPHasChain]>;
 def writeport  : SDNode<"ISD::WRITEPORT"  , SDTWritePort, [SDNPHasChain]>;
 
 def load       : SDNode<"ISD::LOAD"       , SDTLoad,  [SDNPHasChain]>;

diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index 07ff869b203a0720c3f0f830147fd65517c3377a..66810a3b038514d627cf4796e5f6e3c1b3f48bca 100644 (file)
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -399,18 +399,27 @@ def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}", []>,
 //  Input/Output Instructions...
 //
 def IN8rr  : I<0xEC, RawFrm, (ops),
-               "in{b} {%dx, %al|%AL, %DX}", []>,  Imp<[DX], [AL]>;
+               "in{b} {%dx, %al|%AL, %DX}",
+               [(set AL, (readport DX))]>,  Imp<[DX], [AL]>;
 def IN16rr : I<0xED, RawFrm, (ops),
-               "in{w} {%dx, %ax|%AX, %DX}", []>,  Imp<[DX], [AX]>, OpSize;
+               "in{w} {%dx, %ax|%AX, %DX}",
+               [(set AX, (readport DX))]>,  Imp<[DX], [AX]>, OpSize;
 def IN32rr : I<0xED, RawFrm, (ops),
-               "in{l} {%dx, %eax|%EAX, %DX}", []>, Imp<[DX],[EAX]>;
-
-def IN8ri  : Ii8<0xE4, RawFrm, (ops i8imm:$port),
-                  "in{b} {$port, %al|%AL, $port}", []>,  Imp<[], [AL]>;
-def IN16ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
-                  "in{w} {$port, %ax|%AX, $port}", []>,  Imp<[], [AX]>, OpSize;
-def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
-                  "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
+               "in{l} {%dx, %eax|%EAX, %DX}",
+               [(set EAX, (readport DX))]>, Imp<[DX],[EAX]>;
+
+def IN8ri  : Ii8<0xE4, RawFrm, (ops i16i8imm:$port),
+                  "in{b} {$port, %al|%AL, $port}",
+                 [(set AL, (readport i16immZExt8:$port))]>,
+             Imp<[], [AL]>;
+def IN16ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
+                  "in{w} {$port, %ax|%AX, $port}",
+                 [(set AX, (readport i16immZExt8:$port))]>,
+             Imp<[], [AX]>, OpSize;
+def IN32ri : Ii8<0xE5, RawFrm, (ops i16i8imm:$port),
+                  "in{l} {$port, %eax|%EAX, $port}",
+                 [(set EAX, (readport i16immZExt8:$port))]>,
+             Imp<[],[EAX]>;
 
 def OUT8rr  : I<0xEE, RawFrm, (ops),
                 "out{b} {%al, %dx|%DX, %AL}",
@@ -425,15 +434,15 @@ def OUT32rr : I<0xEF, RawFrm, (ops),
 def OUT8ir  : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
                    "out{b} {%al, $port|$port, %AL}",
                    [(writeport AL, i16immZExt8:$port)]>,
-                   Imp<[AL], []>;
+              Imp<[AL], []>;
 def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
                    "out{w} {%ax, $port|$port, %AX}",
                    [(writeport AX, i16immZExt8:$port)]>,
-                   Imp<[AX], []>, OpSize;
+              Imp<[AX], []>, OpSize;
 def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
                    "out{l} {%eax, $port|$port, %EAX}",
                    [(writeport EAX, i16immZExt8:$port)]>,
-                   Imp<[EAX], []>;
+              Imp<[EAX], []>;
 
 //===----------------------------------------------------------------------===//
 //  Move Instructions...