add the memri memory operand

this makes it possible for ldr instructions with non-zero immediate

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29103 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 81932a51dbb7e9cee775ba5d6e705b69a2ed49df..9172c53b3b19f203bc36c144c39dd7cf8e56506a 100644 (file)
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -58,6 +58,12 @@ namespace {
       return "ARM Assembly Printer";
     }
 
+    void printMemRegImm(const MachineInstr *MI, unsigned OpNo) {
+      printOperand(MI, OpNo + 1);
+      O << ", ";
+      printOperand(MI, OpNo);
+    }
+
     void printOperand(const MachineInstr *MI, int opNum);
     void printMemOperand(const MachineInstr *MI, int opNum,
                          const char *Modifier = 0);

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 33413d6c5b507aa2a31cb1c88d4a5c8a4f055e45..2b75b42aa4e029764837784eb9a281ca5bf07c78 100644 (file)
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -164,7 +164,7 @@ public:
 
   void Select(SDOperand &Result, SDOperand Op);
   virtual void InstructionSelectBasicBlock(SelectionDAG &DAG);
-  bool SelectAddrReg(SDOperand N, SDOperand &Base);
+  bool SelectAddrRegImm(SDOperand N, SDOperand &Offset, SDOperand &Base);
 
   // Include the pieces autogenerated from the target description.
 #include "ARMGenDAGISel.inc"
@@ -183,7 +183,10 @@ void ARMDAGToDAGISel::InstructionSelectBasicBlock(SelectionDAG &DAG) {
   ScheduleAndEmitDAG(DAG);
 }
 
-bool ARMDAGToDAGISel::SelectAddrReg(SDOperand N, SDOperand &Base) {
+//register plus/minus 12 bit offset
+bool ARMDAGToDAGISel::SelectAddrRegImm(SDOperand N, SDOperand &Offset,
+                                   SDOperand &Base) {
+  Offset = CurDAG->getTargetConstant(0, MVT::i32);
   if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(N)) {
     Base = CurDAG->getTargetFrameIndex(FI->getIndex(), N.getValueType());
   }

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 68913de1059e7f9a0507384e51f314449f25632e..2f3196f18917c918dd1d7f25556a7bdf8d9c4b27 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -12,9 +12,18 @@
 //
 //===----------------------------------------------------------------------===//
 
+// Address operands
+def memri : Operand<iPTR> {
+  let PrintMethod = "printMemRegImm";
+  let NumMIOperands = 2;
+  let MIOperandInfo = (ops i32imm, ptr_rc);
+}
+
 // Define ARM specific addressing mode.
- //register or frame index
-def raddr  : ComplexPattern<iPTR, 1, "SelectAddrReg", []>;
+//register plus/minus 12 bit offset
+def iaddr  : ComplexPattern<iPTR, 2, "SelectAddrRegImm", []>;
+//register plus scaled register
+//def raddr  : ComplexPattern<iPTR, 2, "SelectAddrRegReg", []>;
 
 //===----------------------------------------------------------------------===//
 // Instructions
@@ -42,9 +51,9 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
 
 def bxr: InstARM<(ops IntRegs:$dst), "bx $dst", [(brind IntRegs:$dst)]>;
 
-def ldr   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
+def ldr   : InstARM<(ops IntRegs:$dst, memri:$addr),
                      "ldr $dst, [$addr]",
-                     [(set IntRegs:$dst, (load raddr:$addr))]>;
+                     [(set IntRegs:$dst, (load iaddr:$addr))]>;
 
 def str  : InstARM<(ops IntRegs:$src, IntRegs:$addr),
                     "str $src, [$addr]",

diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 0c269eede23e8be272ded08a10343deb6b7013cf..e7e1690596fe97c1ead682c0bd45a56bf1aec4a1 100644 (file)
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -83,23 +83,33 @@ ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
 
   assert (MI.getOpcode() == ARM::ldr);
 
-  unsigned FrameIdx = 1;
+  unsigned FrameIdx = 2;
+  unsigned OffIdx = 1;
 
   int FrameIndex = MI.getOperand(FrameIdx).getFrameIndex();
 
   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
+  assert (MI.getOperand(OffIdx).getImmedValue() == 0);
 
   unsigned StackSize = MF.getFrameInfo()->getStackSize();
 
   Offset += StackSize;
 
-  // Insert a set of r12 with the full address
-  // r12 = r13 + offset
-  MachineBasicBlock *MBB2 = MI.getParent();
-  BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
-
-  // Replace the FrameIndex with r12
-  MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
+  assert (Offset >= 0);
+  if (Offset < 4096) {
+    // Replace the FrameIndex with r13
+    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R13);
+    // Replace the ldr offset with Offset
+    MI.getOperand(OffIdx).ChangeToImmediate(Offset);
+  } else {
+    // Insert a set of r12 with the full address
+    // r12 = r13 + offset
+    MachineBasicBlock *MBB2 = MI.getParent();
+    BuildMI(*MBB2, II, ARM::addri, 2, ARM::R12).addReg(ARM::R13).addImm(Offset);
+
+    // Replace the FrameIndex with r12
+    MI.getOperand(FrameIdx).ChangeToRegister(ARM::R12);
+  }
 }
 
 void ARMRegisterInfo::