ARM encoding for VSWP got the second operand incorrect.
authorJim Grosbach <grosbach@apple.com>
Fri, 30 Mar 2012 18:53:01 +0000 (18:53 +0000)
committerJim Grosbach <grosbach@apple.com>
Fri, 30 Mar 2012 18:53:01 +0000 (18:53 +0000)
Make the non-tied register operand names line up with what the base
class encoding handler expects.

rdar://11157236

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153766 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMInstrNEON.td
test/MC/ARM/neon-vswp.s [new file with mode: 0644]

index c5458ed4d04d6aaac1ee6b3da94948c8b62e65c7..dc5298c2d940344a9a1940075d5869d27531079a 100644 (file)
@@ -4787,12 +4787,12 @@ def  VCNTq    : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
 
 // Vector Swap
 def  VSWPd    : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
-                     (outs DPR:$Vd, DPR:$Vd1), (ins DPR:$Vm, DPR:$Vm1),
-                     NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1",
+                     (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
+                     NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
                      []>;
 def  VSWPq    : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
-                     (outs QPR:$Vd, QPR:$Vd1), (ins QPR:$Vm, QPR:$Vm1),
-                     NoItinerary, "vswp", "$Vd, $Vd1", "$Vm = $Vd, $Vm1 = $Vd1",
+                     (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
+                     NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
                      []>;
 
 // Vector Move Operations.
diff --git a/test/MC/ARM/neon-vswp.s b/test/MC/ARM/neon-vswp.s
new file mode 100644 (file)
index 0000000..2138eed
--- /dev/null
@@ -0,0 +1,7 @@
+@ RUN: llvm-mc -mcpu=cortex-a8 -triple armv7-apple-darwin -show-encoding < %s | FileCheck %s
+
+vswp d1, d2
+vswp q1, q2
+
+@ CHECK: vswp  d1, d2                  @ encoding: [0x02,0x10,0xb2,0xf3]
+@ CHECK: vswp  q1, q2                  @ encoding: [0x44,0x20,0xb2,0xf3]