Merge identical code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28274 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index cf11c97f980509a1fe6ffd1bbdb56e687b298a18..650aaae7df87acfbe8926505e811d0c218a83792 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3012,14 +3012,6 @@ SDOperand SelectionDAGLegalize::PromoteOp(SDOperand Op) {
   case ISD::AND:
   case ISD::OR:
   case ISD::XOR:
-    // The input may have strange things in the top bits of the registers, but
-    // these operations don't care.  They may have weird bits going out, but
-    // that too is okay if they are integer operations.
-    Tmp1 = PromoteOp(Node->getOperand(0));
-    Tmp2 = PromoteOp(Node->getOperand(1));
-    assert(Tmp1.getValueType() == NVT && Tmp2.getValueType() == NVT);
-    Result = DAG.getNode(Node->getOpcode(), NVT, Tmp1, Tmp2);
-    break;
   case ISD::ADD:
   case ISD::SUB:
   case ISD::MUL: