Add an ARM RSCrr instruction for disassembly only.

Partial fix for PR7792.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@110361 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index 2ca241531384b0698ec1f56d1f386fadf8227a24..3c710db38c7ca719ef1f6cb43a0cb70123b387b4 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -1673,6 +1673,14 @@ def RSCri : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_imm:$b),
                  Requires<[IsARM]> {
     let Inst{25} = 1;
 }
+// The reg/reg form is only defined for the disassembler; for codegen it is
+// equivalent to SUBrr.
+def RSCrr : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, GPR:$b),
+                 DPFrm, IIC_iALUr, "rsc", "\t$dst, $a, $b",
+                 [/* For disassembly only; pattern left blank */]> {
+    let Inst{25} = 0;
+    let Inst{11-4} = 0b00000000;
+}
 def RSCrs : AsI1<0b0111, (outs GPR:$dst), (ins GPR:$a, so_reg:$b),
                  DPSoRegFrm, IIC_iALUsr, "rsc", "\t$dst, $a, $b",
                  [(set GPR:$dst, (sube_dead_carry so_reg:$b, GPR:$a))]>,

diff --git a/test/MC/Disassembler/arm-tests.txt b/test/MC/Disassembler/arm-tests.txt
index 242d5ec1102a6cd0ff4dd53c4cc7fd7c4b5e9824..52161a6ec16f72fd42be88e90d870032dbd43bab 100644 (file)
--- a/test/MC/Disassembler/arm-tests.txt
+++ b/test/MC/Disassembler/arm-tests.txt
@@ -65,6 +65,10 @@
 # CHECK:       rsbeq   r0, r2, r0
 0x00 0x00 0x62 0x00
 
+# CHECK-NOT:   rsceqs  r0, r0, r1, lsl #0
+# CHECK:       rsceqs  r0, r0, r1
+0x01 0x00 0xf0 0x00
+
 # CHECK:       sbcs    r0, pc, #1
 0x01 0x00 0xdf 0xe2