On ARM, alignment is in bits

Add lr as a hard coded operand of bx

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28494 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMAsmPrinter.cpp b/lib/Target/ARM/ARMAsmPrinter.cpp
index 0ef22be2e64d2a5209ffb05d0e16339e30032a60..81932a51dbb7e9cee775ba5d6e705b69a2ed49df 100644 (file)
--- a/lib/Target/ARM/ARMAsmPrinter.cpp
+++ b/lib/Target/ARM/ARMAsmPrinter.cpp
@@ -44,6 +44,7 @@ namespace {
       ZeroDirective = "\t.skip\t";
       CommentString = "!";
       ConstantPoolSection = "\t.section \".rodata\",#alloc\n";
+      AlignmentIsInBytes = false;
     }
 
     /// We name each basic block in a Function with a unique number, so
@@ -110,7 +111,7 @@ bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
     assert(0 && "Not implemented");
     break;
   }
-  EmitAlignment(4, F);
+  EmitAlignment(2, F);
   O << CurrentFnName << ":\n";
 
   // Print out code for the function.

diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td
index f7069275333e879a2ab1a32ab4586d0c89f819c8..4ccfa33faf213395da7c8cb6d99d2942602c6b21 100644 (file)
--- a/lib/Target/ARM/ARMInstrInfo.td
+++ b/lib/Target/ARM/ARMInstrInfo.td
@@ -42,7 +42,11 @@ def ADJCALLSTACKDOWN : InstARM<(ops i32imm:$amt),
                                "!ADJCALLSTACKDOWN $amt",
                                [(callseq_start imm:$amt)]>;
 
-def BX: InstARM<(ops), "bx", [(retflag)]>;
+//bx supports other registers as operands. So this looks like a
+//hack. Maybe a ret should be expanded to a "branch lr" and bx
+//declared as a regular instruction
+
+def BX: InstARM<(ops), "bx lr", [(retflag)]>;
 
 def ldr   : InstARM<(ops IntRegs:$dst, IntRegs:$addr),
                      "ldr $dst, [$addr]",