#define PROGRAM_BUSY_COUNT 10000
#define ERASE_BUSY_COUNT 20000
#define READ_BUSY_COUNT 5000
+#define RESET_BUSY_COUNT 20000
/* Define delays in microsec for NAND device operations */
#define TROP_US_DELAY 2000
}
+ rk2818_nand_wait_busy(mtd,READ_BUSY_COUNT);
break;
case NAND_CMD_READ0:
{
if ( column>= 0 )
{
- pRK28NC ->chip[master->cs].addr = (column + mtd->writesize) & 0xff;
- pRK28NC ->chip[master->cs].addr = ( (column + mtd->writesize) >> 8) & 0xff;
+ pRK28NC ->chip[master->cs].addr = column & 0xff;
+ pRK28NC ->chip[master->cs].addr = ( column >> 8) & 0xff;
}
if ( page_addr>=0 )
{
case NAND_CMD_STATUS:
pRK28NC ->BCHCTL = 0x0;
pRK28NC ->chip[master->cs].cmd = command;
+ while (timeout>0)
+ {
+ timeout --;
+ udelay(1);
+ if(pRK28NC->FLCTL&FL_INTCLR)
+ break;
+
+ }
break;
case NAND_CMD_RESET:
pRK28NC ->chip[master->cs].cmd = command;
+ while (timeout>0)
+ {
+ timeout --;
+ udelay(1);
+ if(pRK28NC->FLCTL&FL_INTCLR)
+ break;
+
+ }
+ rk2818_nand_wait_busy(mtd,RESET_BUSY_COUNT);
break;
/* This applies to read commands */