The add/sub SP instructions are really pseudos. The assembler should ignore

them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121345 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td
index d94b5c0c0d354740a7ebe176542e409925b8a72a..63edfa589f0b2b31343a6bd22b4aeb0748ef0f5d 100644 (file)
--- a/lib/Target/ARM/ARMInstrThumb2.td
+++ b/lib/Target/ARM/ARMInstrThumb2.td
@@ -1160,6 +1160,7 @@ def t2LEApcrelJT : T2PCOneRegImm<(outs rGPR:$Rd),
 // add/sub instructions. In thumb1 we need them since they have dedicated
 // encodings. At the least, they should be pseudo instructions.
 // ADD r, sp, {so_imm|i12}
+let isCodeGenOnly = 1 in {
 def t2ADDrSPi   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_imm:$imm),
                         IIC_iALUi, "add", ".w\t$Rd, $Rn, $imm", []> {
   let Inst{31-27} = 0b11110;
@@ -1209,6 +1210,7 @@ def t2SUBrSPs   : T2sTwoRegImm<(outs GPR:$Rd), (ins GPR:$Rn, t2_so_reg:$imm),
   let Inst{19-16} = 0b1101; // Rn = sp
   let Inst{15} = 0;
 }
+} // end isCodeGenOnly = 1
 
 // Signed and unsigned division on v7-M
 def t2SDIV : T2ThreeReg<(outs rGPR:$Rd), (ins rGPR:$Rn, rGPR:$Rm), IIC_iALUi,