#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Target/MRegisterInfo.h"
#include "llvm/Support/LeakDetector.h"
+#include "llvm/Support/Streams.h"
#include <iostream>
-
using namespace llvm;
// Global variable holding an array of descriptors for machine instructions.
}
void MachineInstr::dump() const {
- std::cerr << " " << *this;
+ llvm_cerr << " " << *this;
}
static inline void OutputReg(std::ostream &os, unsigned RegNo,
if (op.isRegister() && op.getReg() &&
MRegisterInfo::isVirtualRegister(op.getReg())) {
unsigned virtualReg = (unsigned) op.getReg();
- DEBUG(std::cerr << "op: " << op << "\n");
- DEBUG(std::cerr << "\t inst[" << i << "]: ";
- MI->print(std::cerr, TM));
+ DOUT << "op: " << op << "\n";
+ DOUT << "\t inst[" << i << "]: ";
+ DEBUG(MI->print(std::cerr, TM));
// make sure the same virtual register maps to the same physical
// register in any given instruction
}
}
MI->getOperand(i).setReg(physReg);
- DEBUG(std::cerr << "virt: " << virtualReg <<
- ", phys: " << op.getReg() << "\n");
+ DOUT << "virt: " << virtualReg << ", phys: " << op.getReg() << "\n";
}
}
RegClassIdx.clear();
/// runOnMachineFunction - Register allocate the whole function
///
bool RegAllocSimple::runOnMachineFunction(MachineFunction &Fn) {
- DEBUG(std::cerr << "Machine Function " << "\n");
+ DOUT << "Machine Function\n";
MF = &Fn;
TM = &MF->getTarget();
RegInfo = TM->getRegisterInfo();
/// operands.
///
bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
- DEBUG(std::cerr << "Machine Function\n");
+ DOUT << "Machine Function\n";
const TargetMachine &TM = MF.getTarget();
const MRegisterInfo &MRI = *TM.getRegisterInfo();
const TargetInstrInfo &TII = *TM.getInstrInfo();
bool MadeChange = false;
- DEBUG(std::cerr << "********** REWRITING TWO-ADDR INSTRS **********\n");
- DEBUG(std::cerr << "********** Function: "
- << MF.getFunction()->getName() << '\n');
+ DOUT << "********** REWRITING TWO-ADDR INSTRS **********\n";
+ DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
for (MachineFunction::iterator mbbi = MF.begin(), mbbe = MF.end();
mbbi != mbbe; ++mbbi) {
if (FirstTied) {
++NumTwoAddressInstrs;
- DEBUG(std::cerr << '\t'; mi->print(std::cerr, &TM));
+ DOUT << '\t'; DEBUG(mi->print(std::cerr, &TM));
}
FirstTied = false;
"Not a proper commutative instruction!");
unsigned regC = mi->getOperand(3-si).getReg();
if (LV.KillsRegister(mi, regC)) {
- DEBUG(std::cerr << "2addr: COMMUTING : " << *mi);
+ DOUT << "2addr: COMMUTING : " << *mi;
MachineInstr *NewMI = TII.commuteInstruction(mi);
if (NewMI == 0) {
- DEBUG(std::cerr << "2addr: COMMUTING FAILED!\n");
+ DOUT << "2addr: COMMUTING FAILED!\n";
} else {
- DEBUG(std::cerr << "2addr: COMMUTED TO: " << *NewMI);
+ DOUT << "2addr: COMMUTED TO: " << *NewMI;
// If the instruction changed to commute it, update livevar.
if (NewMI != mi) {
LV.instructionChanged(mi, NewMI); // Update live variables
#endif
if (MachineInstr *New = TII.convertToThreeAddress(mi)) {
- DEBUG(std::cerr << "2addr: CONVERTING 2-ADDR: " << *mi);
- DEBUG(std::cerr << "2addr: TO 3-ADDR: " << *New);
+ DOUT << "2addr: CONVERTING 2-ADDR: " << *mi;
+ DOUT << "2addr: TO 3-ADDR: " << *New;
LV.instructionChanged(mi, New); // Update live variables
mbbi->insert(mi, New); // Insert the new inst
mbbi->erase(mi); // Nuke the old inst.
MRI.copyRegToReg(*mbbi, mi, regA, regB, rc);
MachineBasicBlock::iterator prevMi = prior(mi);
- DEBUG(std::cerr << "\t\tprepend:\t"; prevMi->print(std::cerr, &TM));
+ DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(std::cerr, &TM));
// Update live variables for regA
LiveVariables::VarInfo& varInfo = LV.getVarInfo(regA);
mi->getOperand(ti).setReg(mi->getOperand(si).getReg());
MadeChange = true;
- DEBUG(std::cerr << "\t\trewrite to:\t"; mi->print(std::cerr, &TM));
+ DOUT << "\t\trewrite to:\t"; DEBUG(mi->print(std::cerr, &TM));
}
}
}