UPSTREAM: PCI: rockchip: move the deassert of pm/aclk/pclk after phy_init

Move them after phy_init as we want to optimize the logic
of reset control and reuse rockchip_pcie_init_port later
which should fully follow the cold boot procedure of ROM
code.

Change-Id: I0a826a6de91a7c413e42e36ea5ceea5007ee7b73
Reviewed-by: Brian Norris <briannorris@chromium.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from 0722bdd2962a4a0f6d5e8973b0d274d147adacfb)

diff --git a/drivers/pci/host/pcie-rockchip.c b/drivers/pci/host/pcie-rockchip.c
index 1531d85642ac7011ddd18fd0010ffb8a9593e334..3c8da1087fd2011441309acad0861b20a54c8eff 100644 (file)
--- a/drivers/pci/host/pcie-rockchip.c
+++ b/drivers/pci/host/pcie-rockchip.c
@@ -473,26 +473,6 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
                return err;
        }
 
-       udelay(10);
-
-       err = reset_control_deassert(rockchip->pm_rst);
-       if (err) {
-               dev_err(dev, "deassert pm_rst err %d\n", err);
-               return err;
-       }
-
-       err = reset_control_deassert(rockchip->aclk_rst);
-       if (err) {
-               dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
-               return err;
-       }
-
-       err = reset_control_deassert(rockchip->pclk_rst);
-       if (err) {
-               dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
-               return err;
-       }
-
        err = phy_init(rockchip->phy);
        if (err < 0) {
                dev_err(dev, "fail to init phy, err %d\n", err);
@@ -523,6 +503,26 @@ static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
                return err;
        }
 
+       udelay(10);
+
+       err = reset_control_deassert(rockchip->pm_rst);
+       if (err) {
+               dev_err(dev, "deassert pm_rst err %d\n", err);
+               return err;
+       }
+
+       err = reset_control_deassert(rockchip->aclk_rst);
+       if (err) {
+               dev_err(dev, "deassert aclk_rst err %d\n", err);
+               return err;
+       }
+
+       err = reset_control_deassert(rockchip->pclk_rst);
+       if (err) {
+               dev_err(dev, "deassert pclk_rst err %d\n", err);
+               return err;
+       }
+
        if (rockchip->link_gen == 2)
                rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
                                    PCIE_CLIENT_CONFIG);