Teach SplitVectorOp how to split INSERT_VECTOR_ELT.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@42457 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index ffb2a66527bf969cba1c2d6d5b45719a813b3dab..2fc8b0a7b9d1fffaa845cfd3e6c9721b1dc8e344 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -5837,6 +5837,18 @@ void SelectionDAGLegalize::SplitVectorOp(SDOperand Op, SDOperand &Lo,
     Lo = Node->getOperand(0);
     Hi = Node->getOperand(1);
     break;
+  case ISD::INSERT_VECTOR_ELT: {
+    SplitVectorOp(Node->getOperand(0), Lo, Hi);
+    unsigned Index = cast<ConstantSDNode>(Node->getOperand(2))->getValue();
+    SDOperand ScalarOp = Node->getOperand(1);
+    if (Index < NewNumElts)
+      Lo = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Lo, ScalarOp,
+                       DAG.getConstant(Index, TLI.getPointerTy()));
+    else
+      Hi = DAG.getNode(ISD::INSERT_VECTOR_ELT, NewVT, Hi, ScalarOp,
+                       DAG.getConstant(Index - NewNumElts, TLI.getPointerTy()));
+    break;
+  }
   case ISD::BUILD_VECTOR: {
     SmallVector<SDOperand, 8> LoOps(Node->op_begin(), 
                                     Node->op_begin()+NewNumElts);

diff --git a/test/CodeGen/X86/illegal-insert.ll b/test/CodeGen/X86/illegal-insert.ll
new file mode 100644 (file)
index 0000000..59773b2
--- /dev/null
+++ b/test/CodeGen/X86/illegal-insert.ll
@@ -0,0 +1,18 @@
+; RUN: llvm-as %s -o - | llc -march=x86-64
+
+define <4 x double> @foo0(<4 x double> %t) {
+  %r = insertelement <4 x double> %t, double 2.3, i32 0
+  ret <4 x double> %r
+}
+define <4 x double> @foo1(<4 x double> %t) {
+  %r = insertelement <4 x double> %t, double 2.3, i32 1
+  ret <4 x double> %r
+}
+define <4 x double> @foo2(<4 x double> %t) {
+  %r = insertelement <4 x double> %t, double 2.3, i32 2
+  ret <4 x double> %r
+}
+define <4 x double> @foo3(<4 x double> %t) {
+  %r = insertelement <4 x double> %t, double 2.3, i32 3
+  ret <4 x double> %r
+}