Fix some bugs in the alpha backend, some of which I introduced yesterday,
authorChris Lattner <sabre@nondot.org>
Wed, 17 Aug 2005 17:08:24 +0000 (17:08 +0000)
committerChris Lattner <sabre@nondot.org>
Wed, 17 Aug 2005 17:08:24 +0000 (17:08 +0000)
and some that were preexisting.  All alpha regtests pass now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22829 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaISelPattern.cpp

index 80a47a1a9d03a760691190b6fea14288e276f70d..e559852d2b9c71a8179e07d1d4a6f361507e23f1 100644 (file)
@@ -284,6 +284,7 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
       case MVT::f32:
         args_float[count] = AddLiveIn(MF,args_float[count], getRegClassFor(VT));
         argt = DAG.getCopyFromReg(DAG.getRoot(), args_float[count], VT);
+        DAG.setRoot(argt.getValue(1));
         break;
       case MVT::i1:
       case MVT::i8:
@@ -292,12 +293,12 @@ AlphaTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG)
       case MVT::i64:
         args_int[count] = AddLiveIn(MF, args_int[count],
                                     getRegClassFor(MVT::i64));
-        argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], VT);
+        argt = DAG.getCopyFromReg(DAG.getRoot(), args_int[count], MVT::i64);
+        DAG.setRoot(argt.getValue(1));
         if (VT != MVT::i64)
           argt = DAG.getNode(ISD::TRUNCATE, VT, argt);
         break;
       }
-      DAG.setRoot(argt.getValue(1));
     } else { //more args
       // Create the frame index object for this incoming parameter...
       int FI = MFI->CreateFixedObject(8, 8 * (count - 6));