teach the ppc backend how to spill/reload vector regs

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26806 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 429c9780b476e2b8dac8ff322d3e650142610526..037928fb315a8e2ddbcbaef55e6c8551cf2abb20 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -80,7 +80,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
 }
 
 unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 
-                                              int &FrameIndex) const {
+                                           int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
   case PPC::LD:

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 148449c6d4d1d6a38e795435f74dca85e02ff330..ec8f8cca6a132c92d9add5b7f62d4b3e15ade4a8 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -50,6 +50,9 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                      unsigned SrcReg, int FrameIdx,
                                      const TargetRegisterClass *RC) const {
   if (SrcReg == PPC::LR) {
+    // FIXME: this spills LR immediately to memory in one step.  To do this, we
+    // use R11, which we know cannot be used in the prolog/epilog.  This is a
+    // hack.
     BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
     addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
   } else if (RC == PPC::CRRCRegisterClass) {
@@ -63,6 +66,15 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
   } else if (RC == PPC::F4RCRegisterClass) {
     addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
+  } else if (RC == PPC::VRRCRegisterClass) {
+    // We don't have indexed addressing for vector loads.  Emit:
+    // R11 = ADDI FI#
+    // Dest = LVX R0, R11
+    // 
+    // FIXME: We use R0 here, because it isn't available for RA.
+    addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+    BuildMI(MBB, MI, PPC::STVX, 3)
+      .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
   } else {
     assert(0 && "Unknown regclass!");
     abort();
@@ -88,6 +100,14 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
   } else if (RC == PPC::F4RCRegisterClass) {
     addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
+  } else if (RC == PPC::VRRCRegisterClass) {
+    // We don't have indexed addressing for vector loads.  Emit:
+    // R11 = ADDI FI#
+    // Dest = LVX R0, R11
+    // 
+    // FIXME: We use R0 here, because it isn't available for RA.
+    addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+    BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
   } else {
     assert(0 && "Unknown regclass!");
     abort();