These targets don't like setcc

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21884 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC64ISelPattern.cpp b/lib/Target/PowerPC/PPC64ISelPattern.cpp
index 54f540fcf1e23ddcf7ef75961de62684025f99d6..a654adced928e48f73e69a42cfc181afbd46e445 100644 (file)
--- a/lib/Target/PowerPC/PPC64ISelPattern.cpp
+++ b/lib/Target/PowerPC/PPC64ISelPattern.cpp
@@ -41,6 +41,9 @@ namespace {
     int ReturnAddrIndex;              // FrameIndex for return slot.
   public:
     PPC64TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
+      // Fold away setcc operations if possible.
+      setSetCCIsExpensive();
+
       // Set up the register classes.
       addRegisterClass(MVT::i64, PPC64::GPRCRegisterClass);
       addRegisterClass(MVT::f32, PPC64::FPRCRegisterClass);

diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 536a07710defdb84a00a2896dbe6e1dabcf1c8f9..3281313617dafdc5fa3c18b705f0f1e5b84e8381 100644 (file)
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -43,6 +43,9 @@ namespace {
     int ReturnAddrIndex;              // FrameIndex for return slot.
   public:
     PPC32TargetLowering(TargetMachine &TM) : TargetLowering(TM) {
+      // Fold away setcc operations if possible.
+      setSetCCIsExpensive();
+
       // Set up the register classes.
       addRegisterClass(MVT::i32, PPC32::GPRCRegisterClass);
       addRegisterClass(MVT::f32, PPC32::FPRCRegisterClass);