Because the format of the shift instructions is `shift r, shcnt, r', the

instructions of format 3.12 and 3.13 cannot inherit from F3rdrs1, because that
implies that the two registers are the first two parameters to the instruction.

Thus I made the instructions inherit from F3rd again, and manually added an rs1
field AFTER the shcnt field in the instruction, which maps to the appropriate
place in the instruction.

The other changes are just elimination of unnecessary spaces.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6437 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/SparcV9/SparcV9_F3.td b/lib/Target/SparcV9/SparcV9_F3.td
index 294d1d7c6d0bbaddf0b7782726880cd8f3f0259a..d639ed58c9e2561648ed00b3a701551c228cb8a4 100644 (file)
--- a/lib/Target/SparcV9/SparcV9_F3.td
+++ b/lib/Target/SparcV9/SparcV9_F3.td
@@ -66,7 +66,7 @@ class F3_rs1simm13 : F3_rs1 {
 // Specific F3 classes...
 //
 
-class F3_1<bits<2> opVal,   bits<6> op3val,   string name> : F3_rdrs1rs2 {
+class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
   set op  = opVal;
   set op3 = op3val;
   set Name = name;
@@ -74,21 +74,21 @@ class F3_1<bits<2> opVal,   bits<6> op3val,   string name> : F3_rdrs1rs2 {
   //set Inst{12-5} = dontcare;
 }
 
-class F3_2<bits<2> opVal,   bits<6> op3val,   string name> : F3_rdsimm13rs1 {
+class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rdsimm13rs1 {
   set op  = opVal;
   set op3 = op3val;
   set Name = name;
   set Inst{13} = 1;   // i field = 1
 }
 
-class F3_3<bits<2> opVal,   bits<6> op3val,   string name> : F3_rs1rs2 {
+class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
   set op   = opVal;
   set op3  = op3val;
   set Name = name;
   set Inst{13}  = 0;
 }
 
-class F3_4<bits<2> opVal,   bits<6> op3Val,   string name> : F3_rs1simm13 {
+class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
   bits<13> simm;
   set op   = opVal;
   set op3  = op3Val;
@@ -98,7 +98,7 @@ class F3_4<bits<2> opVal,   bits<6> op3Val,   string name> : F3_rs1simm13 {
   set Inst{12-0} = simm;
 }
 
-class F3_11<bits<2> opVal, bits<6> op3Val,    string name> : F3_rdrs1rs2 {
+class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rdrs1rs2 {
   bit x;
   set op = opVal;
   set op3 = op3Val;
@@ -108,24 +108,28 @@ class F3_11<bits<2> opVal, bits<6> op3Val,    string name> : F3_rdrs1rs2 {
   //set Inst{11-5} = dontcare;
 }
 
-class F3_12<bits<2> opVal, bits<6> op3Val,    string name> : F3_rdrs1 {
+class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
   bits<5> shcnt;
+  bits<5> rs1;
 
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
+  set Inst{18-14} = rs1;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 0; // x field = 0
   //set Inst{11-5} = dontcare;
   set Inst{4-0} = shcnt;
 }
 
-class F3_13<bits<2> opVal, bits<6> op3Val,    string name> : F3_rdrs1 {
+class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
   bits<6> shcnt;
+  bits<5> rs1;
 
   set op  = opVal;
   set op3 = op3Val;
   set Name = name;
+  set Inst{18-14} = rs1;
   set Inst{13} = 1; // i field = 1
   set Inst{12} = 1; // x field = 1
   //set Inst{11-6} = dontcare;