let PrintMethod = "printPredicateOperand";
}
-// Conditional code operand for conditional branches and conditional moves.
-// No AlwaysVal value.
-def ccop : PredicateOperand<OtherVT, (ops i32imm, CCR), (ops)> {
- let PrintMethod = "printPredicateOperand";
-}
-
// Conditional code result for instructions whose 's' bit is set, e.g. subs.
//
def cc_out : OptionalDefOperand<OtherVT, (ops CCR), (ops (i32 zero_reg))> {
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
- def Bcc : AXI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
+ def Bcc : AI<(ops brtarget:$dst), "b", " $dst",
[/*(ARMbrcond bb:$dst, imm:$cc, CCR:$ccr)*/]>;
}
// Conditional moves
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
-def MOVCCr : AXI<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
- "mov$cc $dst, $true",
+def MOVCCr : AI<(ops GPR:$dst, GPR:$false, GPR:$true),
+ "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
-def MOVCCs : AXI<(ops GPR:$dst, GPR:$false, so_reg:$true, ccop:$cc),
- "mov$cc $dst, $true",
+def MOVCCs : AI<(ops GPR:$dst, GPR:$false, so_reg:$true),
+ "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_reg:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
-def MOVCCi : AXI<(ops GPR:$dst, GPR:$false, so_imm:$true, ccop:$cc),
- "mov$cc $dst, $true",
+def MOVCCi : AI<(ops GPR:$dst, GPR:$false, so_imm:$true),
+ "mov", " $dst, $true",
[/*(set GPR:$dst, (ARMcmov GPR:$false, so_imm:$true, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $dst">;
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
let isBranch = 1, isTerminator = 1, noResults = 1 in
- def tBcc : TI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
+ def tBcc : TI<(ops brtarget:$dst, pred:$cc), "b$cc $dst",
[/*(ARMbrcond bb:$dst, imm:$cc)*/]>;
//===----------------------------------------------------------------------===//
// Expanded by the scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
def tMOVCCr :
- PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
+ PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, pred:$cc),
"@ tMOVCCr $cc",
[/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;
// FP Conditional moves.
//
-def FCPYDcc : AXDI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
- "fcpyd$cc $dst, $true",
+def FCPYDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true),
+ "fcpyd", " $dst, $true",
[/*(set DPR:$dst, (ARMcmov DPR:$false, DPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
-def FCPYScc : AXSI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
- "fcpys$cc $dst, $true",
+def FCPYScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true),
+ "fcpys", " $dst, $true",
[/*(set SPR:$dst, (ARMcmov SPR:$false, SPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
-def FNEGDcc : AXDI<(ops DPR:$dst, DPR:$false, DPR:$true, ccop:$cc),
- "fnegd$cc $dst, $true",
+def FNEGDcc : ADI<(ops DPR:$dst, DPR:$false, DPR:$true),
+ "fnegd", " $dst, $true",
[/*(set DPR:$dst, (ARMcneg DPR:$false, DPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;
-def FNEGScc : AXSI<(ops SPR:$dst, SPR:$false, SPR:$true, ccop:$cc),
- "fnegs$cc $dst, $true",
+def FNEGScc : ASI<(ops SPR:$dst, SPR:$false, SPR:$true),
+ "fnegs", " $dst, $true",
[/*(set SPR:$dst, (ARMcneg SPR:$false, SPR:$true, imm:$cc))*/]>,
RegConstraint<"$false = $dst">;