Stop custom lowering forr x86 DEC64m from happening if the load in the lowered sequen...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150537 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86ISelDAGToDAG.cpp b/lib/Target/X86/X86ISelDAGToDAG.cpp
index 709be5f8530d75d7ebf7324002f00e39654b8ae7..16f9c46c68dd7bcdca37fa85b2d83bd7be11fd17 100644 (file)
--- a/lib/Target/X86/X86ISelDAGToDAG.cpp
+++ b/lib/Target/X86/X86ISelDAGToDAG.cpp
@@ -2379,6 +2379,7 @@ SDNode *X86DAGToDAGISel::Select(SDNode *Node) {
         StoredVal->getOpcode() != X86ISD::DEC ||
         StoredVal.getResNo() != 0 ||
         !StoredVal.getNode()->hasNUsesOfValue(1, 0) ||
+        !Chain.getNode()->hasNUsesOfValue(1, 0) ||
         StoredVal->getOperand(0).getNode() != Chain.getNode())
       break;
 

diff --git a/test/CodeGen/X86/dec-eflags-lower.ll b/test/CodeGen/X86/dec-eflags-lower.ll
index 841a4615f53992b7e2ef3b4bda0ed17d89e97792..190819f4cf8a0f435459dc06480418f212520d43 100644 (file)
--- a/test/CodeGen/X86/dec-eflags-lower.ll
+++ b/test/CodeGen/X86/dec-eflags-lower.ll
@@ -43,6 +43,20 @@ store i32 %lor.ext.i, i32* @a, align 4, !tbaa !3
 ret i32 0
 }
 
+; CHECK: test2
+define i32 @test2() nounwind uwtable ssp {
+entry:
+; CHECK-NOT: decq ({{.*}})
+%0 = load i64* @c, align 8, !tbaa !0
+%dec.i = add nsw i64 %0, -1
+store i64 %dec.i, i64* @c, align 8, !tbaa !0
+%tobool.i = icmp ne i64 %0, 0
+%lor.ext.i = zext i1 %tobool.i to i32
+store i32 %lor.ext.i, i32* @a, align 4, !tbaa !3
+%call = tail call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([5 x i8]* @.str, i64 0, i64 0), i64 %dec.i) nounwind
+ret i32 0
+}
+
 declare i32 @printf(i8* nocapture, ...) nounwind
 
 declare void @free(i8* nocapture) nounwind