Add code in MipsDAGToDAGISel for selecting constant +0.0.

MIPS64 can generate constant +0.0 with a single DMTC1 instruction.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146999 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index b33a4e6c09b611706e586a590fc149b477bbb6c5..8f3cb55715062b72dbf4242616aa156230000b41 100644 (file)
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -293,6 +293,12 @@ SDNode* MipsDAGToDAGISel::Select(SDNode *Node) {
     case ISD::ConstantFP: {
       ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
       if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
+        if (Subtarget.hasMips64()) {
+          SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
+                                                Mips::ZERO_64, MVT::i64);
+          return CurDAG->getMachineNode(Mips::DMTC1, dl, MVT::f64, Zero);
+        }
+
         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), dl,
                                               Mips::ZERO, MVT::i32);
         return CurDAG->getMachineNode(Mips::BuildPairF64, dl, MVT::f64, Zero,

diff --git a/test/CodeGen/Mips/mips64fpimm0.ll b/test/CodeGen/Mips/mips64fpimm0.ll
new file mode 100644 (file)
index 0000000..17716da
--- /dev/null
+++ b/test/CodeGen/Mips/mips64fpimm0.ll
@@ -0,0 +1,7 @@
+; RUN: llc  < %s -march=mips64el -mcpu=mips64 -mattr=n64 | FileCheck %s
+
+define double @foo1() nounwind readnone {
+entry:
+; CHECK: dmtc1 $zero
+  ret double 0.000000e+00
+}