Add a few more altivec intrinsics

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@27215 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/include/llvm/IntrinsicsPowerPC.td b/include/llvm/IntrinsicsPowerPC.td
index fd8003e1d25c078071e43264ed68cfff252ca3f5..d502369bf0907f29dba6f92d3ae3d69a70b2e977 100644 (file)
--- a/include/llvm/IntrinsicsPowerPC.td
+++ b/include/llvm/IntrinsicsPowerPC.td
@@ -131,7 +131,7 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
               Intrinsic<[llvm_int_ty, llvm_int_ty, llvm_v16i8_ty,llvm_v16i8_ty],
                         [InstrNoMem]>;
 
-  // Saturating adds and subs.
+  // Saturating adds, subs, and multiply-adds
   def int_ppc_altivec_vaddubs : GCCBuiltin<"__builtin_altivec_vaddubs">,
               Intrinsic<[llvm_v16i8_ty, llvm_v16i8_ty, llvm_v16i8_ty],
                         [InstrNoMem]>;
@@ -150,6 +150,12 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   def int_ppc_altivec_vaddsws : GCCBuiltin<"__builtin_altivec_vaddsws">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
                         [InstrNoMem]>;
+  def int_ppc_altivec_vmhaddshs : GCCBuiltin<"__builtin_altivec_vmhaddshs">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
+                         llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>;
+  def int_ppc_altivec_vmhraddshs : GCCBuiltin<"__builtin_altivec_vmhraddshs">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty,
+                         llvm_v8i16_ty, llvm_v8i16_ty], [InstrNoMem]>;
 
   def int_ppc_altivec_vmaddfp : GCCBuiltin<"__builtin_altivec_vmaddfp">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty,
@@ -219,6 +225,20 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
   def int_ppc_altivec_vrfiz : GCCBuiltin<"__builtin_altivec_vrfiz">,
               Intrinsic<[llvm_v4f32_ty, llvm_v4f32_ty], [InstrNoMem]>;
 
+  // Merges
+  def int_ppc_altivec_vmrghh : GCCBuiltin<"__builtin_altivec_vmrghh">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vmrghw : GCCBuiltin<"__builtin_altivec_vmrghw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vmrglh : GCCBuiltin<"__builtin_altivec_vmrglh">,
+              Intrinsic<[llvm_v8i16_ty, llvm_v8i16_ty, llvm_v8i16_ty],
+                        [InstrNoMem]>;
+  def int_ppc_altivec_vmrglw : GCCBuiltin<"__builtin_altivec_vmrglw">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, llvm_v4i32_ty],
+                        [InstrNoMem]>;
+
   // Left Shifts.
   def int_ppc_altivec_vsldoi : GCCBuiltin<"__builtin_altivec_vsldoi_4si">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
@@ -276,6 +296,9 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
                         [InstrNoMem]>;
 
   // Miscellaneous.
+  def int_ppc_altivec_vperm : GCCBuiltin<"__builtin_altivec_vperm_4si">,
+              Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
+                         llvm_v4i32_ty, llvm_v16i8_ty], [InstrNoMem]>;
   def int_ppc_altivec_vsel : GCCBuiltin<"__builtin_altivec_vsel_4si">,
               Intrinsic<[llvm_v4i32_ty, llvm_v4i32_ty, 
                          llvm_v4i32_ty, llvm_v4i32_ty], [InstrNoMem]>;

diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 46cf60e9981c620c73a6c1ffc1109ea1407d148a..0c50c59580f5bc023b68e439b02257a602e00159 100644 (file)
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -300,8 +300,8 @@ bool PPC::isVecSplatImm(SDNode *N, unsigned ByteSize, char *Val) {
   
   if (OpVal.Val == 0) return false;  // All UNDEF: use implicit def.
   
-  unsigned ValSizeInBytes;
-  uint64_t Value;
+  unsigned ValSizeInBytes = 0;
+  uint64_t Value = 0;
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
     Value = CN->getValue();
     ValSizeInBytes = MVT::getSizeInBits(CN->getValueType(0))/8;

diff --git a/lib/Target/PowerPC/PPCInstrAltivec.td b/lib/Target/PowerPC/PPCInstrAltivec.td
index c02f78bc9ccb3ab111c2e54301cd25d8f88e3c5c..d6a3946b85dd756a9af58ad936696bd10a6fcd68 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrAltivec.td
+++ b/lib/Target/PowerPC/PPCInstrAltivec.td
@@ -121,7 +121,14 @@ def VNMSUBFP: VAForm_1<47, (ops VRRC:$vD, VRRC:$vA, VRRC:$vC, VRRC:$vB),
                        [(set VRRC:$vD, (fneg (fsub (fmul VRRC:$vA, VRRC:$vC),
                                                    VRRC:$vB)))]>,
                        Requires<[FPContractions]>;
-
+def VMHADDSHS  : VAForm_1a<32, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+                  "vmhaddshs $vD, $vA, $vB, $vC", VecFP,
+                  [(set VRRC:$vD,
+                   (int_ppc_altivec_vmhaddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
+def VMHRADDSHS : VAForm_1a<33, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
+                  "vmhraddshs $vD, $vA, $vB, $vC", VecFP,
+                  [(set VRRC:$vD,
+                   (int_ppc_altivec_vmhraddshs VRRC:$vA, VRRC:$vB, VRRC:$vC))]>;
 def VPERM   : VAForm_1a<43, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB, VRRC:$vC),
                         "vperm $vD, $vA, $vB, $vC", VecPerm,
                         [(set VRRC:$vD,
@@ -213,6 +220,22 @@ def VMAXFP : VXForm_1<1034, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
 def VMINFP : VXForm_1<1098, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
                       "vminfp $vD, $vA, $vB", VecFP,
                       []>;
+def VMRGHH : VXForm_1<76, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmrghh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                       (int_ppc_altivec_vmrghh VRRC:$vA, VRRC:$vB))]>;
+def VMRGHW : VXForm_1<140, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmrghh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                       (int_ppc_altivec_vmrghw VRRC:$vA, VRRC:$vB))]>;
+def VMRGLH : VXForm_1<332, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmrglh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                       (int_ppc_altivec_vmrglh VRRC:$vA, VRRC:$vB))]>;
+def VMRGLW : VXForm_1<396, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB),
+                      "vmrglh $vD, $vA, $vB", VecFP,
+                      [(set VRRC:$vD,
+                       (int_ppc_altivec_vmrglw VRRC:$vA, VRRC:$vB))]>;
 def VREFP  : VXForm_2<266, (ops VRRC:$vD, VRRC:$vB),
                       "vrefp $vD, $vB", VecFP,
                       [(set VRRC:$vD, (int_ppc_altivec_vrefp VRRC:$vB))]>;
@@ -598,7 +621,8 @@ def : Pat<(int_ppc_altivec_vmaddfp VRRC:$A, VRRC:$B, VRRC:$C),
           (VMADDFP VRRC:$A, VRRC:$B, VRRC:$C)>;
 def : Pat<(int_ppc_altivec_vnmsubfp VRRC:$A, VRRC:$B, VRRC:$C),
           (VNMSUBFP VRRC:$A, VRRC:$B, VRRC:$C)>;
-
+def : Pat<(int_ppc_altivec_vperm VRRC:$A, VRRC:$B, VRRC:$C),
+          (VPERM VRRC:$A, VRRC:$B, VRRC:$C)>;
 def : Pat<(vector_shuffle (v4i32 VRRC:$vB), (undef), VSPLT_shuffle_mask:$UIMM),
           (v4i32 (VSPLTW VSPLT_shuffle_mask:$UIMM, VRRC:$vB))>;
 

diff --git a/lib/Target/PowerPC/README_ALTIVEC.txt b/lib/Target/PowerPC/README_ALTIVEC.txt
index 6439a2909e275c4f1340007b9927125733a4983b..7754f4c13c85f464b8cfc5dd2c047e0d0b73e476 100644 (file)
--- a/lib/Target/PowerPC/README_ALTIVEC.txt
+++ b/lib/Target/PowerPC/README_ALTIVEC.txt
@@ -54,13 +54,11 @@ lvsl/lvsr
 mf*
 vavg*
 vmax*
-vmhaddshs/vmhraddshs
 vmin*
 vmladduhm
 vmr*
 vmsum*
 vmul*
-vperm
 vpk*
 vsel (some aliases only accessible using builtins)
 vup*