rk3368: clk: modify relation in software of clocks under PD_VIO

It is necessary to enable hclk_vio_h2p\pclk_vio_h2p\hclk_vio_ahb_arbi
for devices under power doamin PD_VIO wen they work. Thus these clks
are modified to be parent of other clks from hclk_vio.

Signed-off-by: dkl <dkl@rock-chips.com>

diff --git a/arch/arm64/boot/dts/rk3368-clocks.dtsi b/arch/arm64/boot/dts/rk3368-clocks.dtsi
index 0e8fc0a7b615e2f1506e5f71bac5c54ef256b71e..b9fef1688692ec881bfabb7154a3e8207f7c7621 100644 (file)
--- a/arch/arm64/boot/dts/rk3368-clocks.dtsi
+++ b/arch/arm64/boot/dts/rk3368-clocks.dtsi
@@ -2432,9 +2432,9 @@
                                                 <&clk_gates16 9>,      <&clk_gates16 8>,
 
                                                <&clk_gates16 9>,       <&clk_gates16 9>,
-                                               <&clk_gates16 8>,       <&clk_gates16 8>,
+                                               <&clk_gates16 8>,       <&clk_gates17 8>,
 
-                                               <&hclk_vio>,    <&aclk_vio0>,
+                                               <&clk_gates16 7>,       <&aclk_vio0>,
                                                <&aclk_rga_pre>,        <&clk_gates16 9>,
 
                                                <&clk_gates16 8>,       <&pclkin_vip>,
@@ -2464,9 +2464,9 @@
                                                 <&pclkin_isp>, <&pclk_vio>,
 
                                                <&pclk_vio>,    <&dummy>,
-                                               <&pclk_vio>,    <&clk_gates16 8>,
+                                               <&pclk_vio>,    <&hclk_vio>,
 
-                                               <&pclk_vio>,    <&pclk_vio>,
+                                               <&clk_gates17 7>,       <&pclk_vio>,
                                                <&clk_gates16 10>,      <&pclk_vio>,
 
                                                <&clk_gates16 8>,       <&dummy>,