DAG.getValueType(EVT));
}
+ // fold sra (shl X, m), result_size - n
+ // -> (sign_extend (trunc (shl X, result_size - n - m))) for
+ // result_size - n != m. If truncate is free for the target sext(shl) is
+ // likely to result in better code.
+ if (N0.getOpcode() == ISD::SHL) {
+ // Get the two constanst of the shifts, CN0 = m, CN = n.
+ const ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N0.getOperand(1));
+ if (N01C && N1C) {
+ // Determine if the truncate type's bitsize would correspond to
+ // an integer type for this target.
+ unsigned VTValSize = MVT::getSizeInBits(VT);
+ MVT::ValueType TruncVT = MVT::getIntegerType(VTValSize - N1C->getValue());
+ unsigned ShiftAmt = N1C->getValue() - N01C->getValue();
+
+ // If the shift wouldn't be a noop, the truncated type is an actual type,
+ // and the truncate is free, then proceed with the transform.
+ if (ShiftAmt != 0 &&
+ !MVT::isExtendedVT(TruncVT) && TLI.isTruncateFree(VT, TruncVT)) {
+ SDOperand Amt = DAG.getConstant(ShiftAmt, TLI.getShiftAmountTy());
+ SDOperand Shift = DAG.getNode(ISD::SRL, VT, N0.getOperand(0), Amt);
+ SDOperand Trunc = DAG.getNode(ISD::TRUNCATE, TruncVT, Shift);
+ return DAG.getNode(ISD::SIGN_EXTEND, N->getValueType(0), Trunc);
+ }
+ }
+ }
+
// fold (sra (sra x, c1), c2) -> (sra x, c1+c2)
if (N1C && N0.getOpcode() == ISD::SRA) {
if (ConstantSDNode *C1 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
--- /dev/null
+; RUN: llvm-as < %s | llc -march=x86 | grep sar | count 1
+; RUN: llvm-as < %s | llc -march=x86-64 | not grep sar
+
+define i32 @test(i32 %f12) {
+ %tmp7.25 = lshr i32 %f12, 16
+ %tmp7.26 = trunc i32 %tmp7.25 to i8
+ %tmp78.2 = sext i8 %tmp7.26 to i32
+ ret i32 %tmp78.2
+}
+
+define i32 @test2(i32 %f12) {
+ %f11 = shl i32 %f12, 8
+ %tmp7.25 = ashr i32 %f11, 24
+ ret i32 %tmp7.25
+}
+
+define i32 @test3(i32 %f12) {
+ %f11 = shl i32 %f12, 13
+ %tmp7.25 = ashr i32 %f11, 24
+ ret i32 %tmp7.25
+}
+
+define i64 @test4(i64 %f12) {
+ %f11 = shl i64 %f12, 32
+ %tmp7.25 = ashr i64 %f11, 32
+ ret i64 %tmp7.25
+}
+
+define i16 @test5(i16 %f12) {
+ %f11 = shl i16 %f12, 2
+ %tmp7.25 = ashr i16 %f11, 8
+ ret i16 %tmp7.25
+}
+
+define i16 @test6(i16 %f12) {
+ %f11 = shl i16 %f12, 8
+ %tmp7.25 = ashr i16 %f11, 8
+ ret i16 %tmp7.25
+}
\ No newline at end of file