drm/i915: Program GuC MAX IDLE Count
authorSagar Arun Kamble <sagar.a.kamble@intel.com>
Sat, 12 Sep 2015 04:47:54 +0000 (10:17 +0530)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Wed, 23 Sep 2015 12:39:15 +0000 (14:39 +0200)
Cc: Alex Dai <yu.dai@intel.com>
Cc: Tom O'Rourke <Tom.O'Rourke@intel.com>
Cc: Akash Goel <akash.goel@intel.com>
Signed-off-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
Reviewed-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
drivers/gpu/drm/i915/i915_guc_reg.h
drivers/gpu/drm/i915/intel_pm.c

index 8c8e574e63bab76959bb9704fd49e77e51a295e1..9d79a6b7cc2fad0fd3023a1d0262469c985e1e5b 100644 (file)
@@ -53,6 +53,7 @@
 #define   START_DMA                      (1<<0)
 #define DMA_GUC_WOPCM_OFFSET           0xc340
 #define   GUC_WOPCM_OFFSET_VALUE         0x80000       /* 512KB */
+#define GUC_MAX_IDLE_COUNT             0xC3E4
 
 #define GUC_WOPCM_SIZE                 0xc050
 #define   GUC_WOPCM_SIZE_VALUE           (0x80 << 12)  /* 512KB */
index 61162b2e3feaab0946a4b79298b5ad868bfc48f3..566f5cd851016b8c65293aacafde7c0ee45d9aaf 100644 (file)
@@ -4865,6 +4865,10 @@ static void gen9_enable_rc6(struct drm_device *dev)
        I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
        for_each_ring(ring, dev_priv, unused)
                I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
+
+       if (HAS_GUC_UCODE(dev))
+               I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
+
        I915_WRITE(GEN6_RC_SLEEP, 0);
        I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */