MIPS: OCTEON: Add OCTEON_IRQ_* definitions for cn68XX chips.
authorDavid Daney <david.daney@cavium.com>
Tue, 3 Apr 2012 22:22:05 +0000 (15:22 -0700)
committerDavid Daney <david.daney@cavium.com>
Fri, 31 Aug 2012 17:46:54 +0000 (10:46 -0700)
There are 64 workqueue, 32 watchdog, and 4 mbox.

Signed-off-by: David Daney <david.daney@cavium.com>
arch/mips/include/asm/mach-cavium-octeon/irq.h

index c22a3078bf11b69f2da21547fc1c337da7b51206..ff0d4909d8480e974b68ce58e31e11da356014f7 100644 (file)
@@ -21,10 +21,11 @@ enum octeon_irq {
        OCTEON_IRQ_TIMER,
 /* sources in CIU_INTX_EN0 */
        OCTEON_IRQ_WORKQ0,
-       OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 16,
-       OCTEON_IRQ_WDOG15 = OCTEON_IRQ_WDOG0 + 15,
-       OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 16,
+       OCTEON_IRQ_WDOG0 = OCTEON_IRQ_WORKQ0 + 64,
+       OCTEON_IRQ_MBOX0 = OCTEON_IRQ_WDOG0 + 32,
        OCTEON_IRQ_MBOX1,
+       OCTEON_IRQ_MBOX2,
+       OCTEON_IRQ_MBOX3,
        OCTEON_IRQ_PCI_INT0,
        OCTEON_IRQ_PCI_INT1,
        OCTEON_IRQ_PCI_INT2,