R600: use capital letter for PV channel

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183107 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/R600/R600RegisterInfo.td b/lib/Target/R600/R600RegisterInfo.td
index df6004bd041b354cc22de88cf301ec3d4bf9bf54..a8b9b70322c5437f28d3fb4623f85e1b45436c7b 100644 (file)
--- a/lib/Target/R600/R600RegisterInfo.td
+++ b/lib/Target/R600/R600RegisterInfo.td
@@ -92,10 +92,10 @@ def ALU_LITERAL_X : R600RegWithChan<"literal.x", 253, "X">;
 def ALU_LITERAL_Y : R600RegWithChan<"literal.y", 253, "Y">;
 def ALU_LITERAL_Z : R600RegWithChan<"literal.z", 253, "Z">;
 def ALU_LITERAL_W : R600RegWithChan<"literal.w", 253, "W">;
-def PV_X : R600RegWithChan<"PV.x", 254, "X">;
-def PV_Y : R600RegWithChan<"PV.y", 254, "Y">;
-def PV_Z : R600RegWithChan<"PV.z", 254, "Z">;
-def PV_W : R600RegWithChan<"PV.w", 254, "W">;
+def PV_X : R600RegWithChan<"PV.X", 254, "X">;
+def PV_Y : R600RegWithChan<"PV.Y", 254, "Y">;
+def PV_Z : R600RegWithChan<"PV.Z", 254, "Z">;
+def PV_W : R600RegWithChan<"PV.W", 254, "W">;
 def PREDICATE_BIT : R600Reg<"PredicateBit", 0>;
 def PRED_SEL_OFF: R600Reg<"Pred_sel_off", 0>;
 def PRED_SEL_ZERO : R600Reg<"Pred_sel_zero", 2>;

diff --git a/test/CodeGen/R600/bfi_int.ll b/test/CodeGen/R600/bfi_int.ll
index f51060ffbed30eebe41b57ffd1721d9a4821b8ca..707abb3952e3c9fee279dd0bb1219a139be61ff5 100644 (file)
--- a/test/CodeGen/R600/bfi_int.ll
+++ b/test/CodeGen/R600/bfi_int.ll
@@ -37,7 +37,7 @@ entry:
 ; ((x & z) | (y & (x | z)))
 ; R600-CHECK: @bfi_sha256_ma
 ; R600-CHECK: XOR_INT * [[DST:T[0-9]+\.[XYZW]]], {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[xyzw]}}, {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; R600-CHECK: BFI_INT * {{T[0-9]+\.[XYZW]}}, {{[[DST]]|PV\.[XYZW]}}, {{T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 ; SI-CHECK: V_XOR_B32_e32 [[DST:VGPR[0-9]+]], {{VGPR[0-9]+, VGPR[0-9]+}}
 ; SI-CHECK: V_BFI_B32 {{VGPR[0-9]+}}, [[DST]], {{VGPR[0-9]+, VGPR[0-9]+}}
 

diff --git a/test/CodeGen/R600/fabs.ll b/test/CodeGen/R600/fabs.ll
index 17ac8951fb3f7c6ee68a107c62933bed9343f49e..b876c0e8d5e266a9c2496e7698b56ab17ecbbe6e 100644 (file)
--- a/test/CodeGen/R600/fabs.ll
+++ b/test/CodeGen/R600/fabs.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: MOV * T{{[0-9]+\.[XYZW], \|PV\.[xyzw]\|}}
+;CHECK: MOV * T{{[0-9]+\.[XYZW], \|PV\.[XYZW]\|}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll
index 821d329d615e27cbe6dc3fd2790283e8fbb80536..bec5043168d6e24c1dc3b9b578508f58604bc99b 100644 (file)
--- a/test/CodeGen/R600/fadd.ll
+++ b/test/CodeGen/R600/fadd.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ; CHECK: @fadd_f32
-; CHECK: ADD * T{{[0-9]+\.[XYZW], PV\.[xyzw], PV\.[xyzw]}}
+; CHECK: ADD * T{{[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
 
 define void @fadd_f32() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/floor.ll b/test/CodeGen/R600/floor.ll
index 0a807b1130a7ffdd57deb88a441eafc2d6b4bd32..7b8aa0af2bfff86b25f54d57b3335209981c812a 100644 (file)
--- a/test/CodeGen/R600/floor.ll
+++ b/test/CodeGen/R600/floor.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: FLOOR * T{{[0-9]+\.[XYZW], PV\.[xyzw]}}
+;CHECK: FLOOR * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/fmad.ll b/test/CodeGen/R600/fmad.ll
index 861411548a15ff6f9cbf109bf0910dc87bbbf452..eb82b44a1d214a69a611cc31a9551bd28ccbe0d4 100644 (file)
--- a/test/CodeGen/R600/fmad.ll
+++ b/test/CodeGen/R600/fmad.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], PV\.[xyzw], PV.[xyzw], PV\.[xyzw]}}
+;CHECK: MULADD_IEEE * {{T[0-9]+\.[XYZW], PV\.[XYZW], PV.[XYZW], PV\.[XYZW]}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/fmax.ll b/test/CodeGen/R600/fmax.ll
index ef3daad226a618295319cc63be4f94ae3fec169f..9357287b743e499e897b7247a44aca2778db2fb4 100644 (file)
--- a/test/CodeGen/R600/fmax.ll
+++ b/test/CodeGen/R600/fmax.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: MAX * T{{[0-9]+\.[XYZW], PV\.[xyzw], PV\.[xyzw]}}
+;CHECK: MAX * T{{[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/fmin.ll b/test/CodeGen/R600/fmin.ll
index 026481c26355f6b9d2bd6e8c98ed8de8bdf62dce..e38269c3a457b419840f00dacd1867e6e2185095 100644 (file)
--- a/test/CodeGen/R600/fmin.ll
+++ b/test/CodeGen/R600/fmin.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: MIN * T{{[0-9]+\.[XYZW], PV\.[xyzw], PV\.[xyzw]}}
+;CHECK: MIN * T{{[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/fmul.ll b/test/CodeGen/R600/fmul.ll
index dbb6424e2cdce6d227c05f6faa2ea7bd72dedc4a..fee5eadfdd241da32ac1155c3b9f5c0b53ee6431 100644 (file)
--- a/test/CodeGen/R600/fmul.ll
+++ b/test/CodeGen/R600/fmul.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ; CHECK: @fmul_f32
-; CHECK: MUL_IEEE * {{T[0-9]+\.[XYZW], PV\.[xyzw], PV\.[xyzw]}}
+; CHECK: MUL_IEEE * {{T[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
 
 define void @fmul_f32() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll
index f88729ef352fb058f30e16b94f7daea0446b365c..2c88cbc1aa8b20910fe098e2a05d03e23d5ed358 100644 (file)
--- a/test/CodeGen/R600/fsub.ll
+++ b/test/CodeGen/R600/fsub.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ; CHECK: @fsub_f32
-; CHECK: ADD * T{{[0-9]+\.[XYZW], PV\.[xyzw], -PV\.[xyzw]}}
+; CHECK: ADD * T{{[0-9]+\.[XYZW], PV\.[XYZW], -PV\.[XYZW]}}
 
 define void @fsub_f32() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/llvm.AMDGPU.mul.ll b/test/CodeGen/R600/llvm.AMDGPU.mul.ll
index 69fbe580cb519ed11f9d1bb669d2d1361a034ea7..be14e6f712d4b01c82fd26bbe6dc7faca312fc77 100644 (file)
--- a/test/CodeGen/R600/llvm.AMDGPU.mul.ll
+++ b/test/CodeGen/R600/llvm.AMDGPU.mul.ll
@@ -1,6 +1,6 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
-;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], PV\.[xyzw], PV\.[xyzw]}}
+;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW], PV\.[XYZW]}}
 
 define void @test() {
    %r0 = call float @llvm.R600.load.input(i32 0)

diff --git a/test/CodeGen/R600/llvm.pow.ll b/test/CodeGen/R600/llvm.pow.ll
index 3800abfc5c4ed077c89a0f70e92eecf710aaa8b2..532983f8265bd12883fab66ce4510f0146d90c9f 100644 (file)
--- a/test/CodeGen/R600/llvm.pow.ll
+++ b/test/CodeGen/R600/llvm.pow.ll
@@ -1,7 +1,7 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ;CHECK: LOG_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW]}}
+;CHECK: MUL NON-IEEE * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW]}}
 ;CHECK-NEXT: EXP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
 define void @test() {

diff --git a/test/CodeGen/R600/pv.ll b/test/CodeGen/R600/pv.ll
index 5481d6d0f54cd120c1251bba5a627e31a516085c..6e0b7440838d1204f00c488b6ddb670681cb2236 100644 (file)
--- a/test/CodeGen/R600/pv.ll
+++ b/test/CodeGen/R600/pv.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=r600 | FileCheck %s
 
 ;CHECK: DOT4 * T{{[0-9]\.W}} (MASKED)
-;CHECK: CNDGE T{{[0-9].[XYZW]}}, PV.x
+;CHECK: CNDGE T{{[0-9].[XYZW]}}, PV.X
 
 define void @main() #0 {
 main_body:

diff --git a/test/CodeGen/R600/rotr.ll b/test/CodeGen/R600/rotr.ll
index ff4da412d6b6bd458ff4452be29a16bb0fdf0f88..efbdcbf22a9b15bdd927a74be50b24bbe1d627b1 100644 (file)
--- a/test/CodeGen/R600/rotr.ll
+++ b/test/CodeGen/R600/rotr.ll
@@ -19,7 +19,7 @@ entry:
 ; R600-CHECK: @rotl
 ; R600-CHECK: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x
 ; R600-CHECK-NEXT: 32
-; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[xyzw]}}
+; R600-CHECK: BIT_ALIGN_INT {{\** T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW], PV.[XYZW]}}
 
 ; SI-CHECK: @rotl
 ; SI-CHECK: V_SUB_I32_e32 [[DST:VGPR[0-9]+]], 32, {{VGPR[0-9]+}}

diff --git a/test/CodeGen/R600/vselect.ll b/test/CodeGen/R600/vselect.ll
index a74a114a331df5396ba5e642db7f4670716ea47c..edd7ba08010abbc8a23ba9329081e52d2b304945 100644 (file)
--- a/test/CodeGen/R600/vselect.ll
+++ b/test/CodeGen/R600/vselect.ll
@@ -1,10 +1,10 @@
 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
 
 ; CHECK: @test_select_v4i32
-; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[xyzw], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: CNDE_INT T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
+; CHECK: CNDE_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
 
 define void @test_select_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in0, <4 x i32> addrspace(1)* %in1) {
 entry: