class ProfileInfoLoader {
const std::string &Filename;
- Module &M;
std::vector<std::string> CommandLines;
std::vector<unsigned> FunctionCounts;
std::vector<unsigned> BlockCounts;
public:
// ProfileInfoLoader ctor - Read the specified profiling data file, exiting
// the program if the file is invalid or broken.
- ProfileInfoLoader(const char *ToolName, const std::string &Filename,
- Module &M);
+ ProfileInfoLoader(const char *ToolName, const std::string &Filename);
static const unsigned Uncounted;
// program if the file is invalid or broken.
//
ProfileInfoLoader::ProfileInfoLoader(const char *ToolName,
- const std::string &Filename,
- Module &TheModule) :
- Filename(Filename),
- M(TheModule), Warned(false) {
+ const std::string &Filename)
+ : Filename(Filename), Warned(false) {
FILE *F = fopen(Filename.c_str(), "rb");
if (F == 0) {
errs() << ToolName << ": Error opening '" << Filename << "': ";
}
bool LoaderPass::runOnModule(Module &M) {
- ProfileInfoLoader PIL("profile-loader", Filename, M);
+ ProfileInfoLoader PIL("profile-loader", Filename);
EdgeInformation.clear();
std::vector<unsigned> Counters = PIL.getRawEdgeCounts();
namespace {
class InlineSpiller : public Spiller {
- MachineFunctionPass &Pass;
MachineFunction &MF;
LiveIntervals &LIS;
LiveStacks &LSS;
InlineSpiller(MachineFunctionPass &pass,
MachineFunction &mf,
VirtRegMap &vrm)
- : Pass(pass),
- MF(mf),
+ : MF(mf),
LIS(pass.getAnalysis<LiveIntervals>()),
LSS(pass.getAnalysis<LiveStacks>()),
AA(&pass.getAnalysis<AliasAnalysis>()),
// analyses
SlotIndexes *Indexes;
- LiveStacks *LS;
MachineDominatorTree *DomTree;
MachineLoopInfo *Loops;
EdgeBundles *Bundles;
// If the target supports JIT code generation, create the JIT.
if (TargetJITInfo *TJ = TM->getJITInfo())
- return new MCJIT(M, TM, *TJ, new MCJITMemoryManager(JMM, M), GVsWithCode);
+ return new MCJIT(M, TM, *TJ, new MCJITMemoryManager(JMM), GVsWithCode);
if (ErrorStr)
*ErrorStr = "target does not support JIT code generation";
// matching LLVM IR counterparts in the module(s) being compiled.
class MCJITMemoryManager : public RTDyldMemoryManager {
virtual void anchor();
- JITMemoryManager *JMM;
+ OwningPtr<JITMemoryManager> JMM;
- // FIXME: Multiple modules.
- Module *M;
public:
- MCJITMemoryManager(JITMemoryManager *jmm, Module *m) :
- JMM(jmm?jmm:JITMemoryManager::CreateDefaultMemManager()), M(m) {}
- // We own the JMM, so make sure to delete it.
- ~MCJITMemoryManager() { delete JMM; }
+ MCJITMemoryManager(JITMemoryManager *jmm) :
+ JMM(jmm?jmm:JITMemoryManager::CreateDefaultMemManager()) {}
uint8_t *allocateDataSection(uintptr_t Size, unsigned Alignment,
unsigned SectionID) {
// very little right now.
//===----------------------------------------------------------------------===//
-SPUHazardRecognizer::SPUHazardRecognizer(const TargetInstrInfo &tii) :
- TII(tii),
- EvenOdd(0)
-{
-}
-
/// Return the pipeline hazard type encountered or generated by this
/// instruction. Currently returns NoHazard.
///
/// SPUHazardRecognizer
class SPUHazardRecognizer : public ScheduleHazardRecognizer
{
-private:
- const TargetInstrInfo &TII;
- int EvenOdd;
-
public:
- SPUHazardRecognizer(const TargetInstrInfo &TII);
+ SPUHazardRecognizer(const TargetInstrInfo &/*TII*/) {}
virtual HazardType getHazardType(SUnit *SU, int Stalls);
virtual void EmitInstruction(SUnit *SU);
virtual void AdvanceCycle();
class SPUTargetLowering :
public TargetLowering
{
- int VarArgsFrameIndex; // FrameIndex for start of varargs area.
SPUTargetMachine &SPUTM;
public:
NVPTXRegisterInfo::NVPTXRegisterInfo(const TargetInstrInfo &tii,
const NVPTXSubtarget &st)
-: NVPTXGenRegisterInfo(0),
- TII(tii),
- ST(st) {
- Is64Bit = st.is64Bit();
-}
-
+ : NVPTXGenRegisterInfo(0),
+ Is64Bit(st.is64Bit()) {}
#define GET_REGINFO_TARGET_DESC
#include "NVPTXGenRegisterInfo.inc"
class NVPTXRegisterInfo : public NVPTXGenRegisterInfo {
private:
- const TargetInstrInfo &TII;
- const NVPTXSubtarget &ST;
bool Is64Bit;
// Hold Strings that can be free'd all together with NVPTXRegisterInfo
ManagedStringPool ManagedStrPool;
class SparcSubtarget;
class SparcFrameLowering : public TargetFrameLowering {
- const SparcSubtarget &STI;
public:
- explicit SparcFrameLowering(const SparcSubtarget &sti)
- : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, 0), STI(sti) {
+ explicit SparcFrameLowering(const SparcSubtarget &/*sti*/)
+ : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 8, 0) {
}
/// emitProlog/emitEpilog - These methods insert prolog and epilog code into
//===----------------------------------------------------------------------===//
XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
- : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0),
- STI(sti) {
+ : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0) {
// Do nothing
}
class XCoreSubtarget;
class XCoreFrameLowering: public TargetFrameLowering {
- const XCoreSubtarget &STI;
public:
XCoreFrameLowering(const XCoreSubtarget &STI);
// using the standard profile info provider pass, but for now this gives us
// access to additional information not exposed via the ProfileInfo
// interface.
- ProfileInfoLoader PIL(argv[0], ProfileDataFile, *M);
+ ProfileInfoLoader PIL(argv[0], ProfileDataFile);
// Run the printer pass.
PassManager PassMgr;
&(TypeBuilder<types::i<1>, true>::get(context2))->getContext());
}
-class MyType {
+struct MyType {
int a;
int *b;
void *array[1];
};
-class MyPortableType {
+struct MyPortableType {
int32_t a;
int32_t *b;
void *array[1];
/// and emission of the instruction selector.
///
class DAGISelEmitter : public TableGenBackend {
- RecordKeeper &Records;
CodeGenDAGPatterns CGP;
public:
- explicit DAGISelEmitter(RecordKeeper &R) : Records(R), CGP(R) {}
+ explicit DAGISelEmitter(RecordKeeper &R) : CGP(R) {}
// run - Output the isel, returning true on failure.
void run(raw_ostream &OS);