Improve comment, patch provided by Vladimir Prus!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28307 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/Target.td b/lib/Target/Target.td
index 78cf8dcaa0919b4bc533d872475fccbbc119f18f..57046b826ee9d7b7ea7a0e2ae651cb2e9353d0f0 100644 (file)
--- a/lib/Target/Target.td
+++ b/lib/Target/Target.td
@@ -72,7 +72,9 @@ class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
 
   // RegType - Specify the list ValueType of the registers in this register
   // class.  Note that all registers in a register class must have the same
-  // ValueTypes.
+  // ValueTypes.  This is a list because some targets permit storing different 
+  // types in same register, for example vector values with 128-bit total size,
+  // but different count/size of items, like SSE on x86.
   //
   list<ValueType> RegTypes = regTypes;