LDM writeback is not allowed if Rn is in the target register list.
authorOwen Anderson <resistor@mac.com>
Fri, 9 Sep 2011 23:13:33 +0000 (23:13 +0000)
committerOwen Anderson <resistor@mac.com>
Fri, 9 Sep 2011 23:13:33 +0000 (23:13 +0000)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139432 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/Disassembler/ARMDisassembler.cpp
test/MC/Disassembler/ARM/invalid-LDM-thumb.txt [new file with mode: 0644]

index 0edb7a5d93e844f114d3e2bcd13398f59e405124..da5b6b86aac5e13c33939aeda6acb911f4f3f2b2 100644 (file)
@@ -918,12 +918,31 @@ static DecodeStatus DecodeRegListOperand(llvm::MCInst &Inst, unsigned Val,
                                  uint64_t Address, const void *Decoder) {
   DecodeStatus S = MCDisassembler::Success;
 
+  bool writebackLoad = false;
+  unsigned writebackReg = 0;
+  switch (Inst.getOpcode()) {
+    default:
+      break;
+    case ARM::LDMIA_UPD:
+    case ARM::LDMDB_UPD:
+    case ARM::LDMIB_UPD:
+    case ARM::LDMDA_UPD:
+    case ARM::t2LDMIA_UPD:
+    case ARM::t2LDMDB_UPD:
+      writebackLoad = true;
+      writebackReg = Inst.getOperand(0).getReg();
+      break;
+  }
+
   // Empty register lists are not allowed.
   if (CountPopulation_32(Val) == 0) return MCDisassembler::Fail;
   for (unsigned i = 0; i < 16; ++i) {
     if (Val & (1 << i)) {
       if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
         return MCDisassembler::Fail;
+      // Writeback not allowed if Rn is in the target list.
+      if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
+        Check(S, MCDisassembler::SoftFail);
     }
   }
 
diff --git a/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt b/test/MC/Disassembler/ARM/invalid-LDM-thumb.txt
new file mode 100644 (file)
index 0000000..a42b248
--- /dev/null
@@ -0,0 +1,5 @@
+# RUN: llvm-mc --disassemble %s -triple=thumbv7-apple-darwin9 |& grep {potentially undefined instruction encoding}
+
+# Writeback is not allowed is Rn is in the target register list.
+
+0xb4 0xe8 0x34 0x04