UPSTREAM: clk: rockchip: set the clock ids for RK3228 VOP

Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
(cherry picked git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git
v4.8-clk/next from commit 0a9d4ac08ebc6bddc97228600c4d7e247d9d7a36)

Change-Id: I9e995f3e1fe35d5b3b44adec174fd58df9b90380
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>

diff --git a/drivers/clk/rockchip/clk-rk3228.c b/drivers/clk/rockchip/clk-rk3228.c
index 462d5c8de8af30ff23736d41b983ebd36a550cf5..a7aad67f7756bfe247f83173cb9813a5ee89c864 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3228.c
+++ b/drivers/clk/rockchip/clk-rk3228.c
@@ -371,7 +371,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
                        RK2928_CLKSEL_CON(29), 0, 3, DFLAGS),
        DIV(0, "sclk_vop_pre", "sclk_vop_src", 0,
                        RK2928_CLKSEL_CON(27), 8, 8, DFLAGS),
-       MUX(0, "dclk_vop", mux_dclk_vop_p, 0,
+       MUX(DCLK_VOP, "dclk_vop", mux_dclk_vop_p, 0,
                        RK2928_CLKSEL_CON(27), 1, 1, MFLAGS),
 
        FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
@@ -508,7 +508,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
        GATE(0, "aclk_iep", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 2, GFLAGS),
        GATE(0, "aclk_iep_noc", "aclk_iep_pre", 0, RK2928_CLKGATE_CON(13), 9, GFLAGS),
 
-       GATE(0, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
+       GATE(ACLK_VOP, "aclk_vop", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 5, GFLAGS),
        GATE(0, "aclk_vop_noc", "aclk_vop_pre", 0, RK2928_CLKGATE_CON(13), 12, GFLAGS),
 
        GATE(0, "aclk_hdcp", "aclk_hdcp_pre", 0, RK2928_CLKGATE_CON(14), 10, GFLAGS),
@@ -516,7 +516,7 @@ static struct rockchip_clk_branch rk3228_clk_branches[] __initdata = {
 
        GATE(0, "hclk_rga", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 1, GFLAGS),
        GATE(0, "hclk_iep", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 3, GFLAGS),
-       GATE(0, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
+       GATE(HCLK_VOP, "hclk_vop", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 6, GFLAGS),
        GATE(0, "hclk_vio_ahb_arbi", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 7, GFLAGS),
        GATE(0, "hclk_vio_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 8, GFLAGS),
        GATE(0, "hclk_vop_noc", "hclk_vio_pre", 0, RK2928_CLKGATE_CON(13), 13, GFLAGS),