Minor compile-time optimization; don't bother checking

canClobberPhysRegDefs if the successor node doesn't
clobber any physical registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67587 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 39c4f4e85ca83b4f8675e4b612d016bcd7c13ea5..30dc4768aa03cf4d72e0f75730acbfda0fd94858 100644 (file)
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1392,7 +1392,7 @@ void RegReductionPriorityQueue<SF>::AddPseudoTwoAddrDeps() {
           continue;
         // Don't constrain nodes with physical register defs if the
         // predecessor can clobber them.
-        if (SuccSU->hasPhysRegDefs) {
+        if (SuccSU->hasPhysRegDefs && SU->hasPhysRegClobbers) {
           if (canClobberPhysRegDefs(SuccSU, SU, TII, TRI))
             continue;
         }