cerr << " " << *this;
}
-static inline std::ostream &OutputValue(std::ostream &os,
- const Value* val)
+static inline std::ostream&
+OutputValue(std::ostream &os, const Value* val)
{
os << "(val ";
if (val && val->hasName())
return os << (void*) val << ")"; // print address only
}
+static inline std::ostream&
+OutputReg(std::ostream &os, unsigned int regNum)
+{
+ return os << "%mreg(" << regNum << ")";
+}
+
std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
{
os << TargetInstrDescriptors[minstr.opCode].opCodeString;
case MachineOperand::MO_VirtualRegister:
os << "%reg";
OutputValue(os, mop.getVRegValue());
+ if (mop.hasAllocatedReg())
+ os << "==" << OutputReg(os, mop.getAllocatedRegNum());
break;
case MachineOperand::MO_CCRegister:
os << "%ccreg";
OutputValue(os, mop.getVRegValue());
+ if (mop.hasAllocatedReg())
+ os << "==" << OutputReg(os, mop.getAllocatedRegNum());
break;
case MachineOperand::MO_MachineRegister:
- os << "%reg";
- os << "(" << mop.getMachineRegNum() << ")";
+ OutputReg(os, mop.getMachineRegNum());
break;
case MachineOperand::MO_SignExtendedImmed:
os << (long)mop.immedVal;