Add MBB successors and physreg Uses in the same order that

SDISel typically adds them in. This makes it a little easier
to compare FastISel output with SDISel output.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57266 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 1f2896c8b0ba63ca0abfa330209d1b5af8c89134..2ce78eccef08b812e720fd1ebb6674926cfbbf81 100644 (file)
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -784,8 +784,8 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
       default:
         return false;
       }
-      MBB->addSuccessor(TrueMBB);
       FastEmitBranch(FalseMBB);
+      MBB->addSuccessor(TrueMBB);
       return true;
     }
   }
@@ -797,9 +797,8 @@ bool X86FastISel::X86SelectBranch(Instruction *I) {
   BuildMI(MBB, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
 
   BuildMI(MBB, TII.get(X86::JNE)).addMBB(TrueMBB);
-  MBB->addSuccessor(TrueMBB);
-
   FastEmitBranch(FalseMBB);
+  MBB->addSuccessor(TrueMBB);
 
   return true;
 }
@@ -1180,10 +1179,8 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
     MIB.addReg(X86::EBX);
 
   // Add implicit physical register uses to the call.
-  while (!RegArgs.empty()) {
-    MIB.addReg(RegArgs.back());
-    RegArgs.pop_back();
-  }
+  for (unsigned i = 0, e = RegArgs.size(); i != e; ++i)
+    MIB.addReg(RegArgs[i]);
 
   // Issue CALLSEQ_END
   unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();