; Add pure 12-bit immediates:
define void @add_small() {
-; CHECK: add_small:
+; CHECK-LABEL: add_small:
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #4095
%val32 = load i32* @var_i32
; Add 12-bit immediates, shifted left by 12 bits
define void @add_med() {
-; CHECK: add_med:
+; CHECK-LABEL: add_med:
; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
%val32 = load i32* @var_i32
; Subtract 12-bit immediates
define void @sub_small() {
-; CHECK: sub_small:
+; CHECK-LABEL: sub_small:
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #4095
%val32 = load i32* @var_i32
; Subtract 12-bit immediates, shifted left by 12 bits
define void @sub_med() {
-; CHECK: sub_med:
+; CHECK-LABEL: sub_med:
; CHECK: sub {{w[0-9]+}}, {{w[0-9]+}}, #3567, lsl #12
%val32 = load i32* @var_i32
@var64 = global i64 0
define void @addsub_i8rhs() {
-; CHECK: addsub_i8rhs:
+; CHECK-LABEL: addsub_i8rhs:
%val8_tmp = load i8* @var8
%lhs32 = load i32* @var32
%lhs64 = load i64* @var64
}
define void @addsub_i16rhs() {
-; CHECK: addsub_i16rhs:
+; CHECK-LABEL: addsub_i16rhs:
%val16_tmp = load i16* @var16
%lhs32 = load i32* @var32
%lhs64 = load i64* @var64
; example), but the remaining instructions are probably not idiomatic
; in the face of "add/sub (shifted register)" so I don't intend to.
define void @addsub_i32rhs() {
-; CHECK: addsub_i32rhs:
+; CHECK-LABEL: addsub_i32rhs:
%val32_tmp = load i32* @var32
%lhs64 = load i64* @var64
; RUN: llc -mtriple=aarch64-none-linux-gnu -verify-machineinstrs < %s | FileCheck %s
define i32 @foo(i32* %var, i1 %cond) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
br i1 %cond, label %atomic_ver, label %simple_ver
simple_ver:
%oldval = load i32* %var
; CHECK-ELF: RELOCATION RECORDS FOR [.rela.text]
define i32 @get_globalvar() {
-; CHECK: get_globalvar:
+; CHECK-LABEL: get_globalvar:
%val = load i32* @var
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
}
define i32* @get_globalvaraddr() {
-; CHECK: get_globalvaraddr:
+; CHECK-LABEL: get_globalvaraddr:
%val = load i32* @var
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:var
@hiddenvar = hidden global i32 0
define i32 @get_hiddenvar() {
-; CHECK: get_hiddenvar:
+; CHECK-LABEL: get_hiddenvar:
%val = load i32* @hiddenvar
; CHECK: adrp x[[HI:[0-9]+]], hiddenvar
}
define i32* @get_hiddenvaraddr() {
-; CHECK: get_hiddenvaraddr:
+; CHECK-LABEL: get_hiddenvaraddr:
%val = load i32* @hiddenvar
; CHECK: adrp [[HI:x[0-9]+]], hiddenvar
}
define void()* @get_func() {
-; CHECK: get_func:
+; CHECK-LABEL: get_func:
ret void()* bitcast(void()*()* @get_func to void()*)
; CHECK: adrp x[[GOTHI:[0-9]+]], :got:get_func
%struct.foo = type { i8, [2 x i8], i8 }
define [1 x i64] @from_clang([1 x i64] %f.coerce, i32 %n) nounwind readnone {
-; CHECK: from_clang:
+; CHECK-LABEL: from_clang:
; CHECK: bfi w0, w1, #3, #4
; CHECK-NEXT: ret
@stored_label = global i8* null
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%lab = load i8** @stored_label
indirectbr i8* %lab, [label %otherlab, label %retlab]
; CHECK: adrp {{x[0-9]+}}, stored_label
@var = global float 0.0
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: stp d14, d15, [sp
; CHECK: stp d12, d13, [sp
@var64 = global i64 0
define i8* @global_addr() {
-; CHECK: global_addr:
+; CHECK-LABEL: global_addr:
ret i8* @var8
; The movz/movk calculation should end up returned directly in x0.
; CHECK: movz x0, #:abs_g3:var8
}
define i8 @global_i8() {
-; CHECK: global_i8:
+; CHECK-LABEL: global_i8:
%val = load i8* @var8
ret i8 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var8
}
define i16 @global_i16() {
-; CHECK: global_i16:
+; CHECK-LABEL: global_i16:
%val = load i16* @var16
ret i16 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
}
define i32 @global_i32() {
-; CHECK: global_i32:
+; CHECK-LABEL: global_i32:
%val = load i32* @var32
ret i32 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var32
}
define i64 @global_i64() {
-; CHECK: global_i64:
+; CHECK-LABEL: global_i64:
%val = load i64* @var64
ret i64 %val
; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var64
@var64 = global i64 0
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%val1 = load volatile i32* @var32
%tst1 = icmp eq i32 %val1, 0
@var64 = global i64 0
define void @rev_i32() {
-; CHECK: rev_i32:
+; CHECK-LABEL: rev_i32:
%val0_tmp = load i32* @var32
%val1_tmp = call i32 @llvm.bswap.i32(i32 %val0_tmp)
; CHECK: rev {{w[0-9]+}}, {{w[0-9]+}}
}
define void @rev_i64() {
-; CHECK: rev_i64:
+; CHECK-LABEL: rev_i64:
%val0_tmp = load i64* @var64
%val1_tmp = call i64 @llvm.bswap.i64(i64 %val0_tmp)
; CHECK: rev {{x[0-9]+}}, {{x[0-9]+}}
}
define void @rev32_i64() {
-; CHECK: rev32_i64:
+; CHECK-LABEL: rev32_i64:
%val0_tmp = load i64* @var64
%val1_tmp = shl i64 %val0_tmp, 32
%val5_tmp = sub i64 64, 32
}
define void @rev16_i32() {
-; CHECK: rev16_i32:
+; CHECK-LABEL: rev16_i32:
%val0_tmp = load i32* @var32
%val1_tmp = shl i32 %val0_tmp, 16
%val2_tmp = lshr i32 %val0_tmp, 16
}
define void @clz_zerodef_i32() {
-; CHECK: clz_zerodef_i32:
+; CHECK-LABEL: clz_zerodef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 0)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
}
define void @clz_zerodef_i64() {
-; CHECK: clz_zerodef_i64:
+; CHECK-LABEL: clz_zerodef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 0)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
}
define void @clz_zeroundef_i32() {
-; CHECK: clz_zeroundef_i32:
+; CHECK-LABEL: clz_zeroundef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctlz.i32(i32 %val0_tmp, i1 1)
; CHECK: clz {{w[0-9]+}}, {{w[0-9]+}}
}
define void @clz_zeroundef_i64() {
-; CHECK: clz_zeroundef_i64:
+; CHECK-LABEL: clz_zeroundef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctlz.i64(i64 %val0_tmp, i1 1)
; CHECK: clz {{x[0-9]+}}, {{x[0-9]+}}
}
define void @cttz_zerodef_i32() {
-; CHECK: cttz_zerodef_i32:
+; CHECK-LABEL: cttz_zerodef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
}
define void @cttz_zerodef_i64() {
-; CHECK: cttz_zerodef_i64:
+; CHECK-LABEL: cttz_zerodef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 0)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
}
define void @cttz_zeroundef_i32() {
-; CHECK: cttz_zeroundef_i32:
+; CHECK-LABEL: cttz_zeroundef_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.cttz.i32(i32 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:w[0-9]+]], {{w[0-9]+}}
}
define void @cttz_zeroundef_i64() {
-; CHECK: cttz_zeroundef_i64:
+; CHECK-LABEL: cttz_zeroundef_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.cttz.i64(i64 %val0_tmp, i1 1)
; CHECK: rbit [[REVERSED:x[0-9]+]], {{x[0-9]+}}
; These two are just compilation tests really: the operation's set to Expand in
; ISelLowering.
define void @ctpop_i32() {
-; CHECK: ctpop_i32:
+; CHECK-LABEL: ctpop_i32:
%val0_tmp = load i32* @var32
%val4_tmp = call i32 @llvm.ctpop.i32(i32 %val0_tmp)
store volatile i32 %val4_tmp, i32* @var32
}
define void @ctpop_i64() {
-; CHECK: ctpop_i64:
+; CHECK-LABEL: ctpop_i64:
%val0_tmp = load i64* @var64
%val4_tmp = call i64 @llvm.ctpop.i64(i64 %val0_tmp)
store volatile i64 %val4_tmp, i64* @var64
@var64_1 = global i64 0
define void @rorv_i64() {
-; CHECK: rorv_i64:
+; CHECK-LABEL: rorv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val2_tmp = sub i64 64, %val1_tmp
}
define void @asrv_i64() {
-; CHECK: asrv_i64:
+; CHECK-LABEL: asrv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = ashr i64 %val0_tmp, %val1_tmp
}
define void @lsrv_i64() {
-; CHECK: lsrv_i64:
+; CHECK-LABEL: lsrv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = lshr i64 %val0_tmp, %val1_tmp
}
define void @lslv_i64() {
-; CHECK: lslv_i64:
+; CHECK-LABEL: lslv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = shl i64 %val0_tmp, %val1_tmp
}
define void @udiv_i64() {
-; CHECK: udiv_i64:
+; CHECK-LABEL: udiv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = udiv i64 %val0_tmp, %val1_tmp
}
define void @sdiv_i64() {
-; CHECK: sdiv_i64:
+; CHECK-LABEL: sdiv_i64:
%val0_tmp = load i64* @var64_0
%val1_tmp = load i64* @var64_1
%val4_tmp = sdiv i64 %val0_tmp, %val1_tmp
define void @lsrv_i32() {
-; CHECK: lsrv_i32:
+; CHECK-LABEL: lsrv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
}
define void @lslv_i32() {
-; CHECK: lslv_i32:
+; CHECK-LABEL: lslv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
}
define void @rorv_i32() {
-; CHECK: rorv_i32:
+; CHECK-LABEL: rorv_i32:
%val0_tmp = load i32* @var32_0
%val6_tmp = load i32* @var32_1
%val1_tmp = add i32 1, %val6_tmp
}
define void @asrv_i32() {
-; CHECK: asrv_i32:
+; CHECK-LABEL: asrv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val2_tmp = add i32 1, %val1_tmp
}
define void @sdiv_i32() {
-; CHECK: sdiv_i32:
+; CHECK-LABEL: sdiv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val4_tmp = sdiv i32 %val0_tmp, %val1_tmp
}
define void @udiv_i32() {
-; CHECK: udiv_i32:
+; CHECK-LABEL: udiv_i32:
%val0_tmp = load i32* @var32_0
%val1_tmp = load i32* @var32_1
%val4_tmp = udiv i32 %val0_tmp, %val1_tmp
; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
define i64 @ror_i64(i64 %in) {
-; CHECK: ror_i64:
+; CHECK-LABEL: ror_i64:
%left = shl i64 %in, 19
%right = lshr i64 %in, 45
%val5 = or i64 %left, %right
}
define i32 @ror_i32(i32 %in) {
-; CHECK: ror_i32:
+; CHECK-LABEL: ror_i32:
%left = shl i32 %in, 9
%right = lshr i32 %in, 23
%val5 = or i32 %left, %right
}
define i32 @extr_i32(i32 %lhs, i32 %rhs) {
-; CHECK: extr_i32:
+; CHECK-LABEL: extr_i32:
%left = shl i32 %lhs, 6
%right = lshr i32 %rhs, 26
%val = or i32 %left, %right
}
define i64 @extr_i64(i64 %lhs, i64 %rhs) {
-; CHECK: extr_i64:
+; CHECK-LABEL: extr_i64:
%right = lshr i64 %rhs, 40
%left = shl i64 %lhs, 24
%val = or i64 %right, %left
; Regression test: a bad experimental pattern crept into git which optimised
; this pattern to a single EXTR.
define i32 @extr_regress(i32 %a, i32 %b) {
-; CHECK: extr_regress:
+; CHECK-LABEL: extr_regress:
%sh1 = shl i32 %a, 14
%sh2 = lshr i32 %b, 14
declare fastcc void @will_pop([8 x i32], i32 %val)
define fastcc void @foo(i32 %in) {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%addr = alloca i8, i32 %in
declare void @wont_pop([8 x i32], i32 %val)
define void @foo1(i32 %in) {
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
%addr = alloca i8, i32 %in
; Normal frame setup again
; stack, so try to make sure this is respected.
define fastcc void @func_stack0() {
-; CHECK: func_stack0:
+; CHECK-LABEL: func_stack0:
; CHECK: sub sp, sp, #48
-; CHECK-TAIL: func_stack0:
+; CHECK-TAIL-LABEL: func_stack0:
; CHECK-TAIL: sub sp, sp, #48
}
define fastcc void @func_stack8([8 x i32], i32 %stacked) {
-; CHECK: func_stack8:
+; CHECK-LABEL: func_stack8:
; CHECK: sub sp, sp, #48
-; CHECK-TAIL: func_stack8:
+; CHECK-TAIL-LABEL: func_stack8:
; CHECK-TAIL: sub sp, sp, #48
}
define fastcc void @func_stack32([8 x i32], i128 %stacked0, i128 %stacked1) {
-; CHECK: func_stack32:
+; CHECK-LABEL: func_stack32:
; CHECK: sub sp, sp, #48
-; CHECK-TAIL: func_stack32:
+; CHECK-TAIL-LABEL: func_stack32:
; CHECK-TAIL: sub sp, sp, #48
declare double @nearbyint(double) readonly
define void @simple_float() {
-; CHECK: simple_float:
+; CHECK-LABEL: simple_float:
%val1 = load volatile float* @varfloat
%valabs = call float @fabsf(float %val1)
}
define void @simple_double() {
-; CHECK: simple_double:
+; CHECK-LABEL: simple_double:
%val1 = load volatile double* @vardouble
%valabs = call double @fabs(double %val1)
}
define void @converts() {
-; CHECK: converts:
+; CHECK-LABEL: converts:
%val16 = load volatile half* @varhalf
%val32 = load volatile float* @varfloat
define double @testd_fmadd(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fmadd:
-; CHECK-NOFAST: testd_fmadd:
+; CHECK-NOFAST-LABEL: testd_fmadd:
%val = call double @llvm.fma.f64(double %a, double %b, double %c)
; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
; CHECK-NOFAST: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
define double @testd_fmsub(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fmsub:
-; CHECK-NOFAST: testd_fmsub:
+; CHECK-NOFAST-LABEL: testd_fmsub:
%nega = fsub double -0.0, %a
%val = call double @llvm.fma.f64(double %nega, double %b, double %c)
; CHECK: fmsub {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
define double @testd_fnmadd(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fnmadd:
-; CHECK-NOFAST: testd_fnmadd:
+; CHECK-NOFAST-LABEL: testd_fnmadd:
%negc = fsub double -0.0, %c
%val = call double @llvm.fma.f64(double %a, double %b, double %negc)
; CHECK: fnmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
define double @testd_fnmsub(double %a, double %b, double %c) {
; CHECK-LABEL: testd_fnmsub:
-; CHECK-NOFAST: testd_fnmsub:
+; CHECK-NOFAST-LABEL: testd_fnmsub:
%nega = fsub double -0.0, %a
%negc = fsub double -0.0, %c
%val = call double @llvm.fma.f64(double %nega, double %b, double %negc)
@varf64 = global double 0.0
define void @check_float() {
-; CHECK: check_float:
+; CHECK-LABEL: check_float:
%val = load float* @varf32
%newval1 = fadd float %val, 8.5
}
define void @check_double() {
-; CHECK: check_double:
+; CHECK-LABEL: check_double:
%val = load double* @varf64
%newval1 = fadd double %val, 8.5
@varstruct = global %myStruct zeroinitializer
define void @take_i8s(i8 %val1, i8 %val2) {
-; CHECK: take_i8s:
+; CHECK-LABEL: take_i8s:
store i8 %val2, i8* @var8
; Not using w1 may be technically allowed, but it would indicate a
; problem in itself.
}
define void @add_floats(float %val1, float %val2) {
-; CHECK: add_floats:
+; CHECK-LABEL: add_floats:
%newval = fadd float %val1, %val2
; CHECK: fadd [[ADDRES:s[0-9]+]], s0, s1
store float %newval, float* @varfloat
; byval pointers should be allocated to the stack and copied as if
; with memcpy.
define void @take_struct(%myStruct* byval %structval) {
-; CHECK: take_struct:
+; CHECK-LABEL: take_struct:
%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
; %structval should be at sp + 16
define void @check_byval_align(i32* byval %ignore, %myStruct* byval align 16 %structval) {
-; CHECK: check_byval_align:
+; CHECK-LABEL: check_byval_align:
%addr0 = getelementptr %myStruct* %structval, i64 0, i32 2
%addr1 = getelementptr %myStruct* %structval, i64 0, i32 0
}
define i32 @return_int() {
-; CHECK: return_int:
+; CHECK-LABEL: return_int:
%val = load i32* @var32
ret i32 %val
; CHECK: ldr w0, [{{x[0-9]+}}, #:lo12:var32]
}
define double @return_double() {
-; CHECK: return_double:
+; CHECK-LABEL: return_double:
ret double 3.14
; CHECK: ldr d0, [{{x[0-9]+}}, #:lo12:.LCPI
}
; small enough to go into registers. Not all that pretty, but it
; works.
define [2 x i64] @return_struct() {
-; CHECK: return_struct:
+; CHECK-LABEL: return_struct:
%addr = bitcast %myStruct* @varstruct to [2 x i64]*
%val = load [2 x i64]* %addr
ret [2 x i64] %val
; structs larger than 16 bytes, but C semantics can still be provided
; if LLVM does it to %myStruct too. So this is the simplest check
define void @return_large_struct(%myStruct* sret %retval) {
-; CHECK: return_large_struct:
+; CHECK-LABEL: return_large_struct:
%addr0 = getelementptr %myStruct* %retval, i64 0, i32 0
%addr1 = getelementptr %myStruct* %retval, i64 0, i32 1
%addr2 = getelementptr %myStruct* %retval, i64 0, i32 2
define i32 @struct_on_stack(i8 %var0, i16 %var1, i32 %var2, i64 %var3, i128 %var45,
i32* %var6, %myStruct* byval %struct, i32* byval %stacked,
double %notstacked) {
-; CHECK: struct_on_stack:
+; CHECK-LABEL: struct_on_stack:
%addr = getelementptr %myStruct* %struct, i64 0, i32 0
%val64 = load i64* %addr
store i64 %val64, i64* @var64
define void @stacked_fpu(float %var0, double %var1, float %var2, float %var3,
float %var4, float %var5, float %var6, float %var7,
float %var8) {
-; CHECK: stacked_fpu:
+; CHECK-LABEL: stacked_fpu:
store float %var8, float* @varfloat
; Beware as above: the offset would be different on big-endian
; machines if the first ldr were changed to use s-registers.
declare void @take_floats(float %val1, float %val2)
define void @simple_args() {
-; CHECK: simple_args:
+; CHECK-LABEL: simple_args:
%char1 = load i8* @var8
%char2 = load i8* @var8_2
call void @take_i8s(i8 %char1, i8 %char2)
declare void @return_large_struct(%myStruct* sret %retval)
define void @simple_rets() {
-; CHECK: simple_rets:
+; CHECK-LABEL: simple_rets:
%int = call i32 @return_int()
store i32 %int, i32* @var32
define void @check_i128_align() {
-; CHECK: check_i128_align:
+; CHECK-LABEL: check_i128_align:
%val = load i128* @var128
call void @check_i128_stackalign(i32 0, i32 1, i32 2, i32 3,
i32 4, i32 5, i32 6, i32 7,
@fptr = global void()* null
define void @check_indirect_call() {
-; CHECK: check_indirect_call:
+; CHECK-LABEL: check_indirect_call:
%func = load void()** @fptr
call void %func()
; CHECK: ldr [[FPTR:x[0-9]+]], [{{x[0-9]+}}, #:lo12:fptr]
declare void @func()
define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
entry:
call void @consume(i32 ptrtoint (void ()* @func to i32))
; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:func
@var = global %struct zeroinitializer
define i64 @check_size() {
-; CHECK: check_size:
+; CHECK-LABEL: check_size:
%starti = ptrtoint %struct* @var to i64
%endp = getelementptr %struct* @var, i64 1
}
define i64 @check_field() {
-; CHECK: check_field:
+; CHECK-LABEL: check_field:
%starti = ptrtoint %struct* @var to i64
%endp = getelementptr %struct* @var, i64 0, i32 1
@var_double = global double 0.0
define void @ldst_8bit(i8* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
%addr8_sxtw = getelementptr i8* %base, i32 %off32
%val8_sxtw = load volatile i8* %addr8_sxtw
define void @ldst_16bit(i16* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
%addr8_sxtwN = getelementptr i16* %base, i32 %off32
%val8_sxtwN = load volatile i16* %addr8_sxtwN
}
define void @ldst_32bit(i32* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
%addr_sxtwN = getelementptr i32* %base, i32 %off32
%val_sxtwN = load volatile i32* %addr_sxtwN
}
define void @ldst_64bit(i64* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_64bit:
+; CHECK-LABEL: ldst_64bit:
%addr_sxtwN = getelementptr i64* %base, i32 %off32
%val_sxtwN = load volatile i64* %addr_sxtwN
}
define void @ldst_float(float* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
%addr_sxtwN = getelementptr float* %base, i32 %off32
%val_sxtwN = load volatile float* %addr_sxtwN
}
define void @ldst_double(double* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
%addr_sxtwN = getelementptr double* %base, i32 %off32
%val_sxtwN = load volatile double* %addr_sxtwN
define void @ldst_128bit(fp128* %base, i32 %off32, i64 %off64) {
-; CHECK: ldst_128bit:
+; CHECK-LABEL: ldst_128bit:
%addr_sxtwN = getelementptr fp128* %base, i32 %off32
%val_sxtwN = load volatile fp128* %addr_sxtwN
@varptr = global i8* null
define void @ldst_8bit() {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
; No architectural support for loads to 16-bit or 8-bit since we
; promote i8 during lowering.
}
define void @ldst_16bit() {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
; No architectural support for loads to 16-bit or 16-bit since we
; promote i16 during lowering.
}
define void @ldst_32bit() {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
%addr_8bit = load i8** @varptr
}
define void @ldst_float() {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
%addr_8bit = load i8** @varptr
%addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
}
define void @ldst_double() {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
%addr_8bit = load i8** @varptr
%addrfp_8 = getelementptr i8* %addr_8bit, i64 4
@var_double = global double 0.0
define void @ldst_8bit() {
-; CHECK: ldst_8bit:
+; CHECK-LABEL: ldst_8bit:
; No architectural support for loads to 16-bit or 8-bit since we
; promote i8 during lowering.
}
define void @ldst_16bit() {
-; CHECK: ldst_16bit:
+; CHECK-LABEL: ldst_16bit:
; No architectural support for load volatiles to 16-bit promote i16 during
; lowering.
}
define void @ldst_32bit() {
-; CHECK: ldst_32bit:
+; CHECK-LABEL: ldst_32bit:
; Straight 32-bit load/store
%val32_noext = load volatile i32* @var_32bit
}
define void @ldst_float() {
-; CHECK: ldst_float:
+; CHECK-LABEL: ldst_float:
%valfp = load volatile float* @var_float
; CHECK: adrp {{x[0-9]+}}, var_float
}
define void @ldst_double() {
-; CHECK: ldst_double:
+; CHECK-LABEL: ldst_double:
%valfp = load volatile double* @var_double
; CHECK: adrp {{x[0-9]+}}, var_double
@var64 = global i64 0
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%val32 = load i32* @var32
%val64 = load i64* @var64
@vardouble = global double 0.0
define void @floating_lits() {
-; CHECK: floating_lits:
+; CHECK-LABEL: floating_lits:
%floatval = load float* @varfloat
%newfloat = fadd float %floatval, 128.0
}
define void @trivial_fp_func() {
-; CHECK-WITHFP: trivial_fp_func:
+; CHECK-WITHFP-LABEL: trivial_fp_func:
; CHECK-WITHFP: sub sp, sp, #16
; CHECK-WITHFP: stp x29, x30, [sp]
define void @stack_local() {
%local_var = alloca i64
-; CHECK: stack_local:
+; CHECK-LABEL: stack_local:
; CHECK: sub sp, sp, #16
%val = load i64* @var
@var2_64 = global i64 0
define void @logical_32bit() {
-; CHECK: logical_32bit:
+; CHECK-LABEL: logical_32bit:
%val1 = load i32* @var1_32
%val2 = load i32* @var2_32
}
define void @logical_64bit() {
-; CHECK: logical_64bit:
+; CHECK-LABEL: logical_64bit:
%val1 = load i64* @var1_64
%val2 = load i64* @var2_64
}
define void @flag_setting() {
-; CHECK: flag_setting:
+; CHECK-LABEL: flag_setting:
%val1 = load i64* @var1_64
%val2 = load i64* @var2_64
declare void @bar()
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
%func = load void()** @var
; Calling a function encourages @foo to use a callee-saved register,
declare void @callee_stack16([8 x i32], i64, i64)
define void @caller_to0_from0() nounwind {
-; CHECK: caller_to0_from0:
+; CHECK-LABEL: caller_to0_from0:
; CHECK-NEXT: // BB
tail call void @callee_stack0()
ret void
}
define void @caller_to0_from8([8 x i32], i64) nounwind{
-; CHECK: caller_to0_from8:
+; CHECK-LABEL: caller_to0_from8:
; CHECK-NEXT: // BB
tail call void @callee_stack0()
}
define void @caller_to8_from0() {
-; CHECK: caller_to8_from0:
+; CHECK-LABEL: caller_to8_from0:
; Caller isn't going to clean up any extra stack we allocate, so it
; can't be a tail call.
}
define void @caller_to8_from8([8 x i32], i64 %a) {
-; CHECK: caller_to8_from8:
+; CHECK-LABEL: caller_to8_from8:
; CHECK-NOT: sub sp, sp,
; This should reuse our stack area for the 42
}
define void @caller_to16_from8([8 x i32], i64 %a) {
-; CHECK: caller_to16_from8:
+; CHECK-LABEL: caller_to16_from8:
; Shouldn't be a tail call: we can't use SP+8 because our caller might
; have something there. This may sound obvious but implementation does
}
define void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
-; CHECK: caller_to8_from24:
+; CHECK-LABEL: caller_to8_from24:
; CHECK-NOT: sub sp, sp
; Reuse our area, putting "42" at incoming sp
}
define void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
-; CHECK: caller_to16_from16:
+; CHECK-LABEL: caller_to16_from16:
; CHECK-NOT: sub sp, sp,
; Here we want to make sure that both loads happen before the stores:
@func = global void(i32)* null
define void @indirect_tail() {
-; CHECK: indirect_tail:
+; CHECK-LABEL: indirect_tail:
; CHECK-NOT: sub sp, sp
%fptr = load void(i32)** @func
declare fastcc void @callee_stack16([8 x i32], i64, i64)
define fastcc void @caller_to0_from0() nounwind {
-; CHECK: caller_to0_from0:
+; CHECK-LABEL: caller_to0_from0:
; CHECK-NEXT: // BB
tail call fastcc void @callee_stack0()
ret void
}
define fastcc void @caller_to0_from8([8 x i32], i64) {
-; CHECK: caller_to0_from8:
+; CHECK-LABEL: caller_to0_from8:
tail call fastcc void @callee_stack0()
ret void
}
define fastcc void @caller_to8_from0() {
-; CHECK: caller_to8_from0:
+; CHECK-LABEL: caller_to8_from0:
; CHECK: sub sp, sp, #32
; Key point is that the "42" should go #16 below incoming stack
}
define fastcc void @caller_to8_from8([8 x i32], i64 %a) {
-; CHECK: caller_to8_from8:
+; CHECK-LABEL: caller_to8_from8:
; CHECK: sub sp, sp, #16
; Key point is that the "%a" should go where at SP on entry.
}
define fastcc void @caller_to16_from8([8 x i32], i64 %a) {
-; CHECK: caller_to16_from8:
+; CHECK-LABEL: caller_to16_from8:
; CHECK: sub sp, sp, #16
; Important point is that the call reuses the "dead" argument space
define fastcc void @caller_to8_from24([8 x i32], i64 %a, i64 %b, i64 %c) {
-; CHECK: caller_to8_from24:
+; CHECK-LABEL: caller_to8_from24:
; CHECK: sub sp, sp, #16
; Key point is that the "%a" should go where at #16 above SP on entry.
define fastcc void @caller_to16_from16([8 x i32], i64 %a, i64 %b) {
-; CHECK: caller_to16_from16:
+; CHECK-LABEL: caller_to16_from16:
; CHECK: sub sp, sp, #16
; Here we want to make sure that both loads happen before the stores:
@dequant_coef = external global [6 x [4 x [4 x i32]]] ; <[6 x [4 x [4 x i32]]]*> [#uses=1]
@A = external global [4 x [4 x i32]] ; <[4 x [4 x i32]]*> [#uses=1]
-; CHECK: dct_luma_sp:
+; CHECK-LABEL: dct_luma_sp:
define fastcc i32 @dct_luma_sp(i32 %block_x, i32 %block_y, i32* %coeff_cost) {
entry:
; Make sure to use base-updating stores for saving callee-saved registers.
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
; pr4843
define <4 x i16> @v2regbug(<4 x i16>* %B) nounwind {
-;CHECK: v2regbug:
+;CHECK-LABEL: v2regbug:
;CHECK: vzip.16
%tmp1 = load <4 x i16>* %B
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32><i32 0, i32 0, i32 1, i32 1>
%0 = type { double, double }
define void @foo(%0* noalias nocapture sret %agg.result, double %x.0, double %y.0) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: bl __aeabi_dadd
; CHECK-NOT: strd
; CHECK: mov
%3 = fmul float %0, %1 ; <float> [#uses=1]
%4 = fadd float 0.000000e+00, %3 ; <float> [#uses=1]
%5 = fsub float 1.000000e+00, %4 ; <float> [#uses=1]
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: vmov.f32 s{{[0-9]+}}, #1.000000e+00
%6 = fsub float 1.000000e+00, undef ; <float> [#uses=2]
%7 = fsub float %2, undef ; <float> [#uses=1]
define zeroext i8 @t(%struct.foo* %this) noreturn optsize {
entry:
-; ARM: t:
+; ARM-LABEL: t:
; ARM: str r2, [r1], r0
-; THUMB: t:
+; THUMB-LABEL: t:
; THUMB-NOT: str r0, [r1], r0
; THUMB: str r1, [r0]
%0 = getelementptr inbounds %struct.foo* %this, i32 0, i32 1 ; <i64*> [#uses=1]
define i32* @t(i32* %x) nounwind {
entry:
-; ARM: t:
+; ARM-LABEL: t:
; ARM: push
; ARM: mov r7, sp
; ARM: bl _foo
; ARM: bl _foo
; ARM: pop {r7, pc}
-; THUMB2: t:
+; THUMB2-LABEL: t:
; THUMB2: push
; THUMB2: mov r7, sp
; THUMB2: blx _foo
define hidden void @foo() nounwind ssp {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: mov r7, sp
; CHECK-NEXT: vpush {d8}
; CHECK-NEXT: vpush {d10, d11}
@oStruct = external global %struct.Outer, align 4
define void @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK-NOT: ldrd
; CHECK: mul
for.body.lr.ph:
; rdar://9172742
define i32 @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
entry:
br label %bb2
; Make sure the scheduler schedules all uses of the preincrement
; induction variable before defining the postincrement value.
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: %bb
; CHECK-NOT: mov
bb: ; preds = %entry, %bb
; rdar://9266679
define zeroext i1 @t(i32* nocapture %A, i32 %size, i32 %value) nounwind readonly ssp {
-; CHECK: t:
+; CHECK-LABEL: t:
entry:
br label %for.cond
@infoBlock = external global %struct.InformationBlock
define hidden void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: ldr.w
; CHECK: ldr.w
; CHECK-NOT: ldm
;
; rdar://11116189
define i64 @t(i64 %aInput) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movs [[REG:(r[0-9]+)]], #0
; CHECK: movt [[REG]], #46540
; CHECK: adds r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
; v4i8
;
define void @sextload_v4i8_c(<4 x i8>* %v) nounwind {
-;CHECK: sextload_v4i8_c:
+;CHECK-LABEL: sextload_v4i8_c:
entry:
%0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
; v2i8
;
define void @sextload_v2i8_c(<2 x i8>* %v) nounwind {
-;CHECK: sextload_v2i8_c:
+;CHECK-LABEL: sextload_v2i8_c:
entry:
%0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
; v2i16
;
define void @sextload_v2i16_c(<2 x i16>* %v) nounwind {
-;CHECK: sextload_v2i16_c:
+;CHECK-LABEL: sextload_v2i16_c:
entry:
%0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
; v4i8
;
define void @sextload_v4i8_v(<4 x i8>* %v, <4 x i8>* %p) nounwind {
-;CHECK: sextload_v4i8_v:
+;CHECK-LABEL: sextload_v4i8_v:
entry:
%0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
; v2i8
;
define void @sextload_v2i8_v(<2 x i8>* %v, <2 x i8>* %p) nounwind {
-;CHECK: sextload_v2i8_v:
+;CHECK-LABEL: sextload_v2i8_v:
entry:
%0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
; v2i16
;
define void @sextload_v2i16_v(<2 x i16>* %v, <2 x i16>* %p) nounwind {
-;CHECK: sextload_v2i16_v:
+;CHECK-LABEL: sextload_v2i16_v:
entry:
%0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
; v4i8 x v4i16
;
define void @sextload_v4i8_vs(<4 x i8>* %v, <4 x i16>* %p) nounwind {
-;CHECK: sextload_v4i8_vs:
+;CHECK-LABEL: sextload_v4i8_vs:
entry:
%0 = load <4 x i8>* %v, align 8
%v0 = sext <4 x i8> %0 to <4 x i32>
; v2i8
; v2i8 x v2i16
define void @sextload_v2i8_vs(<2 x i8>* %v, <2 x i16>* %p) nounwind {
-;CHECK: sextload_v2i8_vs:
+;CHECK-LABEL: sextload_v2i8_vs:
entry:
%0 = load <2 x i8>* %v, align 8
%v0 = sext <2 x i8> %0 to <2 x i64>
; v2i16
; v2i16 x v2i32
define void @sextload_v2i16_vs(<2 x i16>* %v, <2 x i32>* %p) nounwind {
-;CHECK: sextload_v2i16_vs:
+;CHECK-LABEL: sextload_v2i16_vs:
entry:
%0 = load <2 x i16>* %v, align 8
%v0 = sext <2 x i16> %0 to <2 x i64>
; rdar://12300648
define i32 @t(i32 %x) {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK-NOT: movw
%tmp = add i32 %x, -65535
ret i32 %tmp
ret void
}
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
; CHECK: movt [[BASE]], :upper16:static_val
; ldm is not formed when the coalescer failed to coalesce everything.
ret void
}
-; CHECK: main_fixed_arg:
+; CHECK-LABEL: main_fixed_arg:
; CHECK: movw [[BASE:r[0-9]+]], :lower16:static_val
; CHECK: movt [[BASE]], :upper16:static_val
; ldm is not formed when the coalescer failed to coalesce everything.
declare void @f(i32 %n1, i32 %n2, i32 %n3, %my_struct_t* byval %val);
-; CHECK: main:
+; CHECK-LABEL: main:
define i32 @main() nounwind {
entry:
; CHECK: ldrb {{(r[0-9]+)}}, {{(\[r[0-9]+\])}}, #1
declare void @f(%struct.s* %p);
-; CHECK: t:
+; CHECK-LABEL: t:
define void @t(i32 %a, %struct.s* byval %s) nounwind {
entry:
ret void
}
-; CHECK: caller:
+; CHECK-LABEL: caller:
define void @caller() {
; CHECK: ldm r0, {r1, r2, r3}
;RUN: llc -mtriple=thumbv7 < %s | FileCheck -check-prefix=EXPECTED %s
;RUN: llc -mtriple=thumbv7 < %s | FileCheck %s
-;EXPECTED: foo:
-;CHECK: foo:
+;EXPECTED-LABEL: foo:
+;CHECK-LABEL: foo:
define i32 @foo(i32* %a) nounwind optsize {
entry:
%0 = load i32* %a, align 4
; RUN: llc < %s -mtriple=armv7s-apple-darwin | FileCheck %s -check-prefix=VFP4
define <4 x float> @muladd(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind {
-; CHECK: muladd:
+; CHECK-LABEL: muladd:
; CHECK: fmaf
; CHECK: fmaf
; CHECK: fmaf
declare <4 x float> @llvm.fma.v4f32(<4 x float>, <4 x float>, <4 x float>) #1
define <2 x float> @muladd2(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind {
-; CHECK: muladd2:
+; CHECK-LABEL: muladd2:
; CHECK: fmaf
; CHECK: fmaf
; CHECK-NOT: fmaf
;PR15293: ARM codegen ice - expected larger existing stack allocation
;RUN: llc -mtriple=arm-linux-gnueabihf < %s | FileCheck %s
-;CHECK: foo:
+;CHECK-LABEL: foo:
;CHECK: sub sp, sp, #8
;CHECK: push {r11, lr}
;CHECK: str r0, [sp, #8]
;CHECK: add sp, sp, #8
;CHECK: mov pc, lr
-;CHECK: foo2:
+;CHECK-LABEL: foo2:
;CHECK: sub sp, sp, #8
;CHECK: push {r11, lr}
;CHECK: str r0, [sp, #8]
;CHECK: add sp, sp, #8
;CHECK: mov pc, lr
-;CHECK: doFoo:
+;CHECK-LABEL: doFoo:
;CHECK: push {r11, lr}
;CHECK: ldr r0,
;CHECK: ldr r0, [r0]
;CHECK: mov pc, lr
-;CHECK: doFoo2:
+;CHECK-LABEL: doFoo2:
;CHECK: push {r11, lr}
;CHECK: ldr r0,
;CHECK: mov r1, #0
;RUN: llc -mtriple=thumbv7-linux-gnueabihf -float-abi=hard < %s | FileCheck %s
;
-;CHECK: foo:
+;CHECK-LABEL: foo:
;CHECK-NOT: mov r0
;CHECK-NOT: ldr r0
;CHECK: bl fooUseI32
-;CHECK: doFoo:
+;CHECK-LABEL: doFoo:
;CHECK: movs r0, #43
;CHECK: bl foo
@.str = private unnamed_addr constant [13 x i8] c"%d %d %f %i\0A\00", align 1
-;CHECK: printfn:
+;CHECK-LABEL: printfn:
define void @printfn(i32 %a, i16 signext %b, double %C, i8 signext %E) {
entry:
%conv = sext i16 %b to i32
; rdar://13782395
define i32 @t1(i32 %a, i32 %b, i8** %retaddr) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: Block address taken
; CHECK-NOT: Address of block that was removed by CodeGen
store i8* blockaddress(@t1, %cond_true), i8** %retaddr
}
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d, i8** %retaddr) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: Block address taken
; CHECK: %cond_true
; CHECK: add
}
define hidden fastcc void @t3(i8** %retaddr) {
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: Block address taken
; CHECK-NOT: Address of block that was removed by CodeGen
bb:
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -disable-a15-sd-optimization -verify-machineinstrs < %s | FileCheck -check-prefix=DISABLED %s
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck -check-prefix=ENABLED %s
-; CHECK-ENABLED: t1:
-; CHECK-DISABLED: t1:
+; CHECK-ENABLED-LABEL: t1:
+; CHECK-DISABLED-LABEL: t1:
define <2 x float> @t1(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
ret <2 x float> %i2
}
-; CHECK-ENABLED: t2:
-; CHECK-DISABLED: t2:
+; CHECK-ENABLED-LABEL: t2:
+; CHECK-DISABLED-LABEL: t2:
define <4 x float> @t2(float %g, float %f) {
; CHECK-ENABLED: vdup.32 q{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
ret <4 x float> %i2
}
-; CHECK-ENABLED: t3:
-; CHECK-DISABLED: t3:
+; CHECK-ENABLED-LABEL: t3:
+; CHECK-DISABLED-LABEL: t3:
define arm_aapcs_vfpcc <2 x float> @t3(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup.32 d{{[0-9]*}}, d0[0]
ret <2 x float> %i2
}
-; CHECK-ENABLED: t4:
-; CHECK-DISABLED: t4:
+; CHECK-ENABLED-LABEL: t4:
+; CHECK-DISABLED-LABEL: t4:
define <2 x float> @t4(float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d0[0]
; CHECK-DISABLED-NOT: vdup
ret <2 x float> %i2
}
-; CHECK-ENABLED: t5:
-; CHECK-DISABLED: t5:
+; CHECK-ENABLED-LABEL: t5:
+; CHECK-DISABLED-LABEL: t5:
define arm_aapcs_vfpcc <4 x float> @t5(<4 x float> %q, float %f) {
; CHECK-ENABLED: vdup.32 d{{[0-9]*}}, d{{[0-9]*}}[0]
; CHECK-ENABLED: vadd.f32
; RUN: llc -O1 -mcpu=cortex-a15 -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
-; CHECK: t1:
+; CHECK-LABEL: t1:
define <2 x float> @t1(float* %A, <2 x float> %B) {
; The generated code for this test uses a vld1.32 instruction
; to write the lane 1 of a D register containing the value of
ret <2 x float> %tmp3
}
-; CHECK: t2:
+; CHECK-LABEL: t2:
define void @t2(<4 x i8> *%in, <4 x i8> *%out, i32 %n) {
entry:
br label %loop
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+vfp2 | FileCheck %s -check-prefix=DARWIN
define i32 @f1(i32 %a, i64 %b) {
-; ELF: f1:
+; ELF-LABEL: f1:
; ELF: mov r0, r2
-; DARWIN: f1:
+; DARWIN-LABEL: f1:
; DARWIN: mov r0, r1
%tmp = call i32 @g1(i64 %b)
ret i32 %tmp
; test that allocating the double to r2/r3 makes r1 unavailable on gnueabi.
define i32 @f2() nounwind optsize {
-; ELF: f2:
+; ELF-LABEL: f2:
; ELF: mov [[REGISTER:(r[0-9]+)]], #128
; ELF: str [[REGISTER]], [
-; DARWIN: f2:
+; DARWIN-LABEL: f2:
; DARWIN: mov r3, #128
entry:
%0 = tail call i32 (i32, ...)* @g2(i32 5, double 1.600000e+01, i32 128) nounwind optsize ; <i32> [#uses=1]
; test that on gnueabi a 64 bit value at this position will cause r3 to go
; unused and the value stored in [sp]
-; ELF: f3:
+; ELF-LABEL: f3:
; ELF: ldr r0, [sp]
; ELF-NEXT: mov pc, lr
-; DARWIN: f3:
+; DARWIN-LABEL: f3:
; DARWIN: mov r0, r3
; DARWIN-NEXT: mov pc, lr
define i32 @f3(i32 %i, i32 %j, i32 %k, i64 %l, ...) {
define i8* @t() nounwind {
entry:
-; DARWIN: t:
+; DARWIN-LABEL: t:
; DARWIN: mov r0, r7
-; LINUX: t:
+; LINUX-LABEL: t:
; LINUX: mov r0, r11
%0 = call i8* @llvm.frameaddress(i32 0)
ret i8* %0
define i8* @rt0(i32 %x) nounwind readnone {
entry:
-; CHECK: rt0:
+; CHECK-LABEL: rt0:
; CHECK: {r7, lr}
; CHECK: mov r0, lr
%0 = tail call i8* @llvm.returnaddress(i32 0)
define i8* @rt2() nounwind readnone {
entry:
-; CHECK: rt2:
+; CHECK-LABEL: rt2:
; CHECK: {r7, lr}
; CHECK: ldr r[[R0:[0-9]+]], [r7]
; CHECK: ldr r0, [r0]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test1:
+; CHECK-THUMB-LABEL: test1:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test2:
+; CHECK-THUMB-LABEL: test2:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test3:
+; CHECK-THUMB-LABEL: test3:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: and.w [[REG3:[a-z0-9]+]], [[REG1]]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test4:
+; CHECK-THUMB-LABEL: test4:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test5:
+; CHECK-THUMB-LABEL: test5:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test6:
+; CHECK-THUMB-LABEL: test6:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test7:
+; CHECK-THUMB-LABEL: test7:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: cmp [[REG1]]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test8:
+; CHECK-THUMB-LABEL: test8:
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: cmp [[REG1]]
; CHECK-THUMB: it eq
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test9:
+; CHECK-THUMB-LABEL: test9:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test10:
+; CHECK-THUMB-LABEL: test10:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test11:
+; CHECK-THUMB-LABEL: test11:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test12:
+; CHECK-THUMB-LABEL: test12:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
; CHECK: bne
; CHECK: dmb {{ish$}}
-; CHECK-THUMB: test13:
+; CHECK-THUMB-LABEL: test13:
; CHECK-THUMB: dmb {{ish$}}
; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
; CHECK-THUMB: subs.w {{[a-z0-9]+}}, [[REG1]], [[REG3:[a-z0-9]+]]
; rdar://8964854
define i8 @t(i8* %a, i8 %b, i8 %c) nounwind {
-; ARM: t:
+; ARM-LABEL: t:
; ARM: ldrexb
; ARM: strexb
-; T2: t:
+; T2-LABEL: t:
; T2: ldrexb
; T2: strexb
%tmp0 = cmpxchg i8* %a, i8 %b, i8 %c monotonic
; RUN: llc -march=arm -mcpu=cortex-a9 < %s | FileCheck %s
-; CHECK: max:
+; CHECK-LABEL: max:
define i32 @max(i8 %ctx, i32* %ptr, i32 %val)
{
; CHECK: ldrex
ret i32 %old
}
-; CHECK: min:
+; CHECK-LABEL: min:
define i32 @min(i8 %ctx, i32* %ptr, i32 %val)
{
; CHECK: ldrex
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind readnone {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: muls [[REG:(r[0-9]+)]], r3, r2
; CHECK-NEXT: mul [[REG2:(r[0-9]+)]], r1, r0
; CHECK-NEXT: muls r0, [[REG]], [[REG2]]
; rdar://10357570
define void @t2(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
%tobool7 = icmp eq i32* %ptr2, null
br i1 %tobool7, label %while.end, label %while.body
; rdar://12878928
define void @t3(i32* nocapture %ptr1, i32* %ptr2, i32 %c) nounwind minsize {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
%tobool7 = icmp eq i32* %ptr2, null
br i1 %tobool7, label %while.end, label %while.body
; 4278190095 = 0xff00000f
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: bfc
%tmp = and i32 %a, 4278190095
ret i32 %tmp
; 4286578688 = 0xff800000
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: bfc
%tmp = and i32 %a, 4286578688
ret i32 %tmp
; 4095 = 0x00000fff
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: bfc
%tmp = and i32 %a, 4095
ret i32 %tmp
; rdar://8458663
define i32 @f5(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: bfc
; CHECK: bfi r0, r1, #20, #4
%0 = and i32 %a, -15728641
; rdar://9609030
define i32 @f6(i32 %a, i32 %b) nounwind readnone {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: bic
; CHECK: bfi r0, r1, #8, #9
%and = and i32 %a, -130817
; RUN: llc < %s -mtriple=arm-apple-darwin -mattr=+v6 | FileCheck %s
define i32 @t1(i32 %x) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK-NOT: InlineAsm
; CHECK: rev
%asmtmp = tail call i32 asm "rev $0, $1\0A", "=l,l"(i32 %x) nounwind
define void @t1() noreturn minsize nounwind ssp {
entry:
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM: bl _bar
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
; SWIFT: bl _bar
tail call void @bar() noreturn nounwind
unreachable
define void @t2() noreturn minsize nounwind ssp {
entry:
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: bl _t1
-; SWIFT: t2:
+; SWIFT-LABEL: t2:
; SWIFT: bl _t1
tail call void @t1() noreturn nounwind
unreachable
define void @t1() noreturn nounwind ssp {
entry:
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM: mov lr, pc
; ARM: b _bar
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
; SWIFT: mov lr, pc
; SWIFT: b _bar
tail call void @bar() noreturn nounwind
define void @t2() noreturn nounwind ssp {
entry:
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: mov lr, pc
; ARM: b _t1
-; SWIFT: t2:
+; SWIFT-LABEL: t2:
; SWIFT: mov lr, pc
; SWIFT: b _t1
tail call void @t1() noreturn nounwind
declare void @g(i32, i32, i32, i32)
define void @t1() {
-; CHECKELF: t1:
+; CHECKELF-LABEL: t1:
; CHECKELF: bl g(PLT)
call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
define void @t2() {
-; CHECKV6: t2:
+; CHECKV6-LABEL: t2:
; CHECKV6: bx r0
-; CHECKT2D: t2:
+; CHECKT2D-LABEL: t2:
; CHECKT2D: ldr
; CHECKT2D-NEXT: ldr
; CHECKT2D-NEXT: bx r0
}
define void @t3() {
-; CHECKV6: t3:
+; CHECKV6-LABEL: t3:
; CHECKV6: b _t2
-; CHECKELF: t3:
+; CHECKELF-LABEL: t3:
; CHECKELF: b t2(PLT)
-; CHECKT2D: t3:
+; CHECKT2D-LABEL: t3:
; CHECKT2D: b.w _t2
tail call void @t2( ) ; <i32> [#uses=0]
; Sibcall optimization of expanded libcalls. rdar://8707777
define double @t4(double %a) nounwind readonly ssp {
entry:
-; CHECKV6: t4:
+; CHECKV6-LABEL: t4:
; CHECKV6: b _sin
-; CHECKELF: t4:
+; CHECKELF-LABEL: t4:
; CHECKELF: b sin(PLT)
%0 = tail call double @sin(double %a) nounwind readonly ; <double> [#uses=1]
ret double %0
define float @t5(float %a) nounwind readonly ssp {
entry:
-; CHECKV6: t5:
+; CHECKV6-LABEL: t5:
; CHECKV6: b _sinf
-; CHECKELF: t5:
+; CHECKELF-LABEL: t5:
; CHECKELF: b sinf(PLT)
%0 = tail call float @sinf(float %a) nounwind readonly ; <float> [#uses=1]
ret float %0
define i32 @t6(i32 %a, i32 %b) nounwind readnone {
entry:
-; CHECKV6: t6:
+; CHECKV6-LABEL: t6:
; CHECKV6: b ___divsi3
-; CHECKELF: t6:
+; CHECKELF-LABEL: t6:
; CHECKELF: b __aeabi_idiv(PLT)
%0 = sdiv i32 %a, %b
ret i32 %0
define void @t7() nounwind {
entry:
-; CHECKT2D: t7:
+; CHECKT2D-LABEL: t7:
; CHECKT2D: blxeq _foo
; CHECKT2D-NEXT: pop.w
; CHECKT2D-NEXT: b.w _foo
; rdar://11140249
define i32 @t8(i32 %x) nounwind ssp {
entry:
-; CHECKT2D: t8:
+; CHECKT2D-LABEL: t8:
; CHECKT2D-NOT: push
%and = and i32 %x, 1
%tobool = icmp eq i32 %and, 0
@x = external global i32, align 4
define i32 @t9() nounwind {
-; CHECKT2D: t9:
+; CHECKT2D-LABEL: t9:
; CHECKT2D: blx __ZN9MutexLockC1Ev
; CHECKT2D: blx __ZN9MutexLockD1Ev
; CHECKT2D: b.w ___divsi3
; Correctly preserve the input chain for the tailcall node in the bitcast case,
; otherwise the call to floorf is lost.
define float @libcall_tc_test2(float* nocapture %a, float %b) {
-; CHECKT2D: libcall_tc_test2:
+; CHECKT2D-LABEL: libcall_tc_test2:
; CHECKT2D: blx _floorf
; CHECKT2D: b.w _truncf
%1 = load float* %a, align 4
@numi = external global i32 ; <i32*> [#uses=1]
@counter = external global [2 x i32] ; <[2 x i32]*> [#uses=1]
-; CHECK: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
+; CHECK-LABEL: main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i:
; CHECK-NOT: bx lr
define void @main_bb_2E_i_bb205_2E_i_2E_i_bb115_2E_i_2E_i() {
call void %fn()
ret void
-; CHECK: PR15520:
+; CHECK-LABEL: PR15520:
; CHECK: mov lr, pc
; CHECK: mov pc, r0
}
; RUN: llc < %s -march=arm | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: subs r
; CHECK: sbc r
entry:
}
define i64 @f2(i64 %a, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: adc r
; CHECK: subs r
; CHECK: sbc r
; add with live carry
define i64 @f3(i32 %al, i32 %bl) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: adds r
; CHECK: adc r
entry:
; rdar://10073745
define i64 @f4(i64 %x) nounwind readnone {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: rsbs r
; CHECK: rsc r
%0 = sub nsw i64 0, %x
; rdar://12559385
define i64 @f5(i32 %vi) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: movw [[REG:r[0-9]+]], #36102
; CHECK: sbc r{{[0-9]+}}, r{{[0-9]+}}, [[REG]]
%v0 = zext i32 %vi to i64
define arm_apcscc %struct.list_head* @t1(%struct.list_head* %list) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
%0 = icmp eq %struct.list_head* %list, null
br i1 %0, label %bb2, label %bb
; rdar://8117827
define i32 @t2(i32 %passes, i32* nocapture %src, i32 %size) nounwind readonly {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: beq LBB1_[[RET:.]]
%0 = icmp eq i32 %passes, 0 ; <i1> [#uses=1]
br i1 %0, label %bb5, label %bb.nph15
declare i32 @llvm.cttz.i32(i32, i1)
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: rbit
; CHECK: clz
%tmp = call i32 @llvm.cttz.i32( i32 %a, i1 true )
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
-; CHECK: f:
+; CHECK-LABEL: f:
define float @f(<4 x i16>* nocapture %in) {
; CHECK: vldr
; CHECK: vmovl.u16
; RUN: llc < %s -mtriple=armv7-apple-darwin | FileCheck %s
define double @f1() nounwind {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .data_region
; CHECK: .long 1413754129
; CHECK: .long 1074340347
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .data_region jt32
; CHECK: .end_data_region
define void @foo(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
entry:
-; A8: foo:
+; A8-LABEL: foo:
; A8: bl ___divmodsi4
; A8-NOT: bl ___divmodsi4
-; SWIFT: foo:
+; SWIFT-LABEL: foo:
; SWIFT: sdiv
; SWIFT: mls
; SWIFT-NOT: bl __divmodsi4
define void @bar(i32 %x, i32 %y, i32* nocapture %P) nounwind ssp {
entry:
-; A8: bar:
+; A8-LABEL: bar:
; A8: bl ___udivmodsi4
; A8-NOT: bl ___udivmodsi4
-; SWIFT: bar:
+; SWIFT-LABEL: bar:
; SWIFT: udiv
; SWIFT: mls
; SWIFT-NOT: bl __udivmodsi4
define void @do_indent(i32 %cols) nounwind {
entry:
-; A8: do_indent:
-; SWIFT: do_indent:
+; A8-LABEL: do_indent:
+; SWIFT-LABEL: do_indent:
%0 = load i32* @flags, align 4
%1 = and i32 %0, 67108864
%2 = icmp eq i32 %1, 0
; rdar://11714607
define i32 @howmany(i32 %x, i32 %y) nounwind {
entry:
-; A8: howmany:
+; A8-LABEL: howmany:
; A8: bl ___udivmodsi4
; A8-NOT: ___udivsi3
-; SWIFT: howmany:
+; SWIFT-LABEL: howmany:
; SWIFT: udiv
; SWIFT: mls
; SWIFT-NOT: bl __udivmodsi4
declare void @__cxa_call_unexpected(i8*)
define i32 @main() {
-; CHECK: main:
+; CHECK-LABEL: main:
entry:
%exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
%0 = bitcast i8* %exception.i to i32*
declare void @_ZSt9terminatev()
-; CHECK-FP: _Z4testiiiiiddddd:
+; CHECK-FP-LABEL: _Z4testiiiiiddddd:
; CHECK-FP: .fnstart
; CHECK-FP: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP: .handlerdata
; CHECK-FP: .fnend
-; CHECK-FP-ELIM: _Z4testiiiiiddddd:
+; CHECK-FP-ELIM-LABEL: _Z4testiiiiiddddd:
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP-ELIM: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK-FP-ELIM: .handlerdata
; CHECK-FP-ELIM: .fnend
-; CHECK-V7-FP: _Z4testiiiiiddddd:
+; CHECK-V7-FP-LABEL: _Z4testiiiiiddddd:
; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r4, r11, lr}
; CHECK-V7-FP: push {r4, r11, lr}
; CHECK-V7-FP: .handlerdata
; CHECK-V7-FP: .fnend
-; CHECK-V7-FP-ELIM: _Z4testiiiiiddddd:
+; CHECK-V7-FP-ELIM-LABEL: _Z4testiiiiiddddd:
; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r4, lr}
; CHECK-V7-FP-ELIM: push {r4, lr}
ret void
}
-; CHECK-FP: test2:
+; CHECK-FP-LABEL: test2:
; CHECK-FP: .fnstart
; CHECK-FP: .save {r11, lr}
; CHECK-FP: push {r11, lr}
; CHECK-FP: mov pc, lr
; CHECK-FP: .fnend
-; CHECK-FP-ELIM: test2:
+; CHECK-FP-ELIM-LABEL: test2:
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r11, lr}
; CHECK-FP-ELIM: push {r11, lr}
; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .fnend
-; CHECK-V7-FP: test2:
+; CHECK-V7-FP-LABEL: test2:
; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r11, lr}
; CHECK-V7-FP: push {r11, lr}
; CHECK-V7-FP: pop {r11, pc}
; CHECK-V7-FP: .fnend
-; CHECK-V7-FP-ELIM: test2:
+; CHECK-V7-FP-ELIM-LABEL: test2:
; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r11, lr}
; CHECK-V7-FP-ELIM: push {r11, lr}
ret i32 %add6
}
-; CHECK-FP: test3:
+; CHECK-FP-LABEL: test3:
; CHECK-FP: .fnstart
; CHECK-FP: .save {r4, r5, r11, lr}
; CHECK-FP: push {r4, r5, r11, lr}
; CHECK-FP: mov pc, lr
; CHECK-FP: .fnend
-; CHECK-FP-ELIM: test3:
+; CHECK-FP-ELIM-LABEL: test3:
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: .save {r4, r5, r11, lr}
; CHECK-FP-ELIM: push {r4, r5, r11, lr}
; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .fnend
-; CHECK-V7-FP: test3:
+; CHECK-V7-FP-LABEL: test3:
; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: .save {r4, r5, r11, lr}
; CHECK-V7-FP: push {r4, r5, r11, lr}
; CHECK-V7-FP: pop {r4, r5, r11, pc}
; CHECK-V7-FP: .fnend
-; CHECK-V7-FP-ELIM: test3:
+; CHECK-V7-FP-ELIM-LABEL: test3:
; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: .save {r4, r5, r11, lr}
; CHECK-V7-FP-ELIM: push {r4, r5, r11, lr}
ret void
}
-; CHECK-FP: test4:
+; CHECK-FP-LABEL: test4:
; CHECK-FP: .fnstart
; CHECK-FP: mov pc, lr
; CHECK-FP: .cantunwind
; CHECK-FP: .fnend
-; CHECK-FP-ELIM: test4:
+; CHECK-FP-ELIM-LABEL: test4:
; CHECK-FP-ELIM: .fnstart
; CHECK-FP-ELIM: mov pc, lr
; CHECK-FP-ELIM: .cantunwind
; CHECK-FP-ELIM: .fnend
-; CHECK-V7-FP: test4:
+; CHECK-V7-FP-LABEL: test4:
; CHECK-V7-FP: .fnstart
; CHECK-V7-FP: bx lr
; CHECK-V7-FP: .cantunwind
; CHECK-V7-FP: .fnend
-; CHECK-V7-FP-ELIM: test4:
+; CHECK-V7-FP-ELIM-LABEL: test4:
; CHECK-V7-FP-ELIM: .fnstart
; CHECK-V7-FP-ELIM: bx lr
; CHECK-V7-FP-ELIM: .cantunwind
define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
%tmp1 = icmp ult i32 %a, 100
br i1 %tmp1, label %bb1, label %bb2
bb1:
define i32 @t1(i32 %a, i32 %b) nounwind uwtable ssp {
entry:
-; THUMB: t1:
-; ARM: t1:
+; THUMB-LABEL: t1:
+; ARM-LABEL: t1:
%x = add i32 %a, %b
br i1 1, label %if.then, label %if.else
; THUMB-NOT: b {{\.?}}LBB0_1
; zext
define i8 @zext_1_8(i1 %a) nounwind ssp {
-; v7: zext_1_8:
+; v7-LABEL: zext_1_8:
; v7: and r0, r0, #1
-; prev6: zext_1_8:
+; prev6-LABEL: zext_1_8:
; prev6: and r0, r0, #1
%r = zext i1 %a to i8
ret i8 %r
}
define i16 @zext_1_16(i1 %a) nounwind ssp {
-; v7: zext_1_16:
+; v7-LABEL: zext_1_16:
; v7: and r0, r0, #1
-; prev6: zext_1_16:
+; prev6-LABEL: zext_1_16:
; prev6: and r0, r0, #1
%r = zext i1 %a to i16
ret i16 %r
}
define i32 @zext_1_32(i1 %a) nounwind ssp {
-; v7: zext_1_32:
+; v7-LABEL: zext_1_32:
; v7: and r0, r0, #1
-; prev6: zext_1_32:
+; prev6-LABEL: zext_1_32:
; prev6: and r0, r0, #1
%r = zext i1 %a to i32
ret i32 %r
}
define i16 @zext_8_16(i8 %a) nounwind ssp {
-; v7: zext_8_16:
+; v7-LABEL: zext_8_16:
; v7: and r0, r0, #255
-; prev6: zext_8_16:
+; prev6-LABEL: zext_8_16:
; prev6: and r0, r0, #255
%r = zext i8 %a to i16
ret i16 %r
}
define i32 @zext_8_32(i8 %a) nounwind ssp {
-; v7: zext_8_32:
+; v7-LABEL: zext_8_32:
; v7: and r0, r0, #255
-; prev6: zext_8_32:
+; prev6-LABEL: zext_8_32:
; prev6: and r0, r0, #255
%r = zext i8 %a to i32
ret i32 %r
}
define i32 @zext_16_32(i16 %a) nounwind ssp {
-; v7: zext_16_32:
+; v7-LABEL: zext_16_32:
; v7: uxth r0, r0
-; prev6: zext_16_32:
+; prev6-LABEL: zext_16_32:
; prev6: lsl{{s?}} r0, r0, #16
; prev6: lsr{{s?}} r0, r0, #16
%r = zext i16 %a to i32
; sext
define i8 @sext_1_8(i1 %a) nounwind ssp {
-; v7: sext_1_8:
+; v7-LABEL: sext_1_8:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_8:
+; prev6-LABEL: sext_1_8:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i8
}
define i16 @sext_1_16(i1 %a) nounwind ssp {
-; v7: sext_1_16:
+; v7-LABEL: sext_1_16:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_16:
+; prev6-LABEL: sext_1_16:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i16
}
define i32 @sext_1_32(i1 %a) nounwind ssp {
-; v7: sext_1_32:
+; v7-LABEL: sext_1_32:
; v7: lsl{{s?}} r0, r0, #31
; v7: asr{{s?}} r0, r0, #31
-; prev6: sext_1_32:
+; prev6-LABEL: sext_1_32:
; prev6: lsl{{s?}} r0, r0, #31
; prev6: asr{{s?}} r0, r0, #31
%r = sext i1 %a to i32
}
define i16 @sext_8_16(i8 %a) nounwind ssp {
-; v7: sext_8_16:
+; v7-LABEL: sext_8_16:
; v7: sxtb r0, r0
-; prev6: sext_8_16:
+; prev6-LABEL: sext_8_16:
; prev6: lsl{{s?}} r0, r0, #24
; prev6: asr{{s?}} r0, r0, #24
%r = sext i8 %a to i16
}
define i32 @sext_8_32(i8 %a) nounwind ssp {
-; v7: sext_8_32:
+; v7-LABEL: sext_8_32:
; v7: sxtb r0, r0
-; prev6: sext_8_32:
+; prev6-LABEL: sext_8_32:
; prev6: lsl{{s?}} r0, r0, #24
; prev6: asr{{s?}} r0, r0, #24
%r = sext i8 %a to i32
}
define i32 @sext_16_32(i16 %a) nounwind ssp {
-; v7: sext_16_32:
+; v7-LABEL: sext_16_32:
; v7: sxth r0, r0
-; prev6: sext_16_32:
+; prev6-LABEL: sext_16_32:
; prev6: lsl{{s?}} r0, r0, #16
; prev6: asr{{s?}} r0, r0, #16
%r = sext i16 %a to i32
define i8* @frameaddr_index0() nounwind {
entry:
-; DARWIN-ARM: frameaddr_index0:
+; DARWIN-ARM-LABEL: frameaddr_index0:
; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7
-; DARWIN-THUMB2: frameaddr_index0:
+; DARWIN-THUMB2-LABEL: frameaddr_index0:
; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7
-; LINUX-ARM: frameaddr_index0:
+; LINUX-ARM-LABEL: frameaddr_index0:
; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp
; LINUX-ARM: mov r0, r11
-; LINUX-THUMB2: frameaddr_index0:
+; LINUX-THUMB2-LABEL: frameaddr_index0:
; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7
define i8* @frameaddr_index1() nounwind {
entry:
-; DARWIN-ARM: frameaddr_index1:
+; DARWIN-ARM-LABEL: frameaddr_index1:
; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7
; DARWIN-ARM: ldr r0, [r0]
-; DARWIN-THUMB2: frameaddr_index1:
+; DARWIN-THUMB2-LABEL: frameaddr_index1:
; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7
; DARWIN-THUMB2: ldr r0, [r0]
-; LINUX-ARM: frameaddr_index1:
+; LINUX-ARM-LABEL: frameaddr_index1:
; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp
; LINUX-ARM: ldr r0, [r11]
-; LINUX-THUMB2: frameaddr_index1:
+; LINUX-THUMB2-LABEL: frameaddr_index1:
; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7
define i8* @frameaddr_index3() nounwind {
entry:
-; DARWIN-ARM: frameaddr_index3:
+; DARWIN-ARM-LABEL: frameaddr_index3:
; DARWIN-ARM: push {r7}
; DARWIN-ARM: mov r7, sp
; DARWIN-ARM: mov r0, r7
; DARWIN-ARM: ldr r0, [r0]
; DARWIN-ARM: ldr r0, [r0]
-; DARWIN-THUMB2: frameaddr_index3:
+; DARWIN-THUMB2-LABEL: frameaddr_index3:
; DARWIN-THUMB2: str r7, [sp, #-4]!
; DARWIN-THUMB2: mov r7, sp
; DARWIN-THUMB2: mov r0, r7
; DARWIN-THUMB2: ldr r0, [r0]
; DARWIN-THUMB2: ldr r0, [r0]
-; LINUX-ARM: frameaddr_index3:
+; LINUX-ARM-LABEL: frameaddr_index3:
; LINUX-ARM: push {r11}
; LINUX-ARM: mov r11, sp
; LINUX-ARM: ldr r0, [r11]
; LINUX-ARM: ldr r0, [r0]
; LINUX-ARM: ldr r0, [r0]
-; LINUX-THUMB2: frameaddr_index3:
+; LINUX-THUMB2-LABEL: frameaddr_index3:
; LINUX-THUMB2: str r7, [sp, #-4]!
; LINUX-THUMB2: mov r7, sp
; LINUX-THUMB2: mov r0, r7
define float @t1(float %acc, float %a, float %b) {
entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
; VFP2: vmla.f32
-; NEON: t1:
+; NEON-LABEL: t1:
; NEON: vmla.f32
-; A8: t1:
+; A8-LABEL: t1:
; A8: vmul.f32
; A8: vadd.f32
%0 = fmul float %a, %b
define double @t2(double %acc, double %a, double %b) {
entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
; VFP2: vmla.f64
-; NEON: t2:
+; NEON-LABEL: t2:
; NEON: vmla.f64
-; A8: t2:
+; A8-LABEL: t2:
; A8: vmul.f64
; A8: vadd.f64
%0 = fmul double %a, %b
define float @t3(float %acc, float %a, float %b) {
entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
; VFP2: vmla.f32
-; NEON: t3:
+; NEON-LABEL: t3:
; NEON: vmla.f32
-; A8: t3:
+; A8-LABEL: t3:
; A8: vmul.f32
; A8: vadd.f32
%0 = fmul float %a, %b
; rdar://8659675
define void @t4(float %acc1, float %a, float %b, float %acc2, float %c, float* %P1, float* %P2) {
entry:
-; A8: t4:
+; A8-LABEL: t4:
; A8: vmul.f32
; A8: vmul.f32
; A8: vadd.f32
; A8: vadd.f32
; Two vmla with now RAW hazard
-; A9: t4:
+; A9-LABEL: t4:
; A9: vmla.f32
; A9: vmla.f32
-; HARD: t4:
+; HARD-LABEL: t4:
; HARD: vmla.f32 s0, s1, s2
; HARD: vmla.f32 s3, s1, s4
%0 = fmul float %a, %b
define float @t5(float %a, float %b, float %c, float %d, float %e) {
entry:
-; A8: t5:
+; A8-LABEL: t5:
; A8: vmul.f32
; A8: vmul.f32
; A8: vadd.f32
; A8: vadd.f32
-; A9: t5:
+; A9-LABEL: t5:
; A9: vmla.f32
; A9: vmul.f32
; A9: vadd.f32
-; HARD: t5:
+; HARD-LABEL: t5:
; HARD: vmla.f32 s4, s0, s1
; HARD: vmul.f32 s0, s2, s3
; HARD: vadd.f32 s0, s4, s0
define float @t1(float %acc, float %a, float %b) {
entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
; VFP2: vnmls.f32
-; NEON: t1:
+; NEON-LABEL: t1:
; NEON: vnmls.f32
-; A8: t1:
+; A8-LABEL: t1:
; A8: vmul.f32
; A8: vsub.f32
%0 = fmul float %a, %b
define double @t2(double %acc, double %a, double %b) {
entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
; VFP2: vnmls.f64
-; NEON: t2:
+; NEON-LABEL: t2:
; NEON: vnmls.f64
-; A8: t2:
+; A8-LABEL: t2:
; A8: vmul.f64
; A8: vsub.f64
%0 = fmul double %a, %b
define float @t1(float %acc, float %a, float %b) {
entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
; VFP2: vmls.f32
-; NEON: t1:
+; NEON-LABEL: t1:
; NEON: vmls.f32
-; A8: t1:
+; A8-LABEL: t1:
; A8: vmul.f32
; A8: vsub.f32
%0 = fmul float %a, %b
define double @t2(double %acc, double %a, double %b) {
entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
; VFP2: vmls.f64
-; NEON: t2:
+; NEON-LABEL: t2:
; NEON: vmls.f64
-; A8: t2:
+; A8-LABEL: t2:
; A8: vmul.f64
; A8: vsub.f64
%0 = fmul double %a, %b
define float @t1(float %acc, float %a, float %b) nounwind {
entry:
-; VFP2: t1:
+; VFP2-LABEL: t1:
; VFP2: vnmla.f32
-; NEON: t1:
+; NEON-LABEL: t1:
; NEON: vnmla.f32
-; A8U: t1:
+; A8U-LABEL: t1:
; A8U: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
-; A8: t1:
+; A8-LABEL: t1:
; A8: vnmul.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
%0 = fmul float %a, %b
define float @t2(float %acc, float %a, float %b) nounwind {
entry:
-; VFP2: t2:
+; VFP2-LABEL: t2:
; VFP2: vnmla.f32
-; NEON: t2:
+; NEON-LABEL: t2:
; NEON: vnmla.f32
-; A8U: t2:
+; A8U-LABEL: t2:
; A8U: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
; A8U: vsub.f32 d{{[0-9]}}, d{{[0-9]}}, d{{[0-9]}}
-; A8: t2:
+; A8-LABEL: t2:
; A8: vnmul.f32 s{{[01234]}}, s{{[01234]}}, s{{[01234]}}
; A8: vsub.f32 s{{[0-9]}}, s{{[0-9]}}, s{{[0-9]}}
%0 = fmul float %a, %b
define double @t3(double %acc, double %a, double %b) nounwind {
entry:
-; VFP2: t3:
+; VFP2-LABEL: t3:
; VFP2: vnmla.f64
-; NEON: t3:
+; NEON-LABEL: t3:
; NEON: vnmla.f64
-; A8U: t3:
+; A8U-LABEL: t3:
; A8U: vnmul.f64 d
; A8U: vsub.f64 d
-; A8: t3:
+; A8-LABEL: t3:
; A8: vnmul.f64 d
; A8: vsub.f64 d
%0 = fmul double %a, %b
define double @t4(double %acc, double %a, double %b) nounwind {
entry:
-; VFP2: t4:
+; VFP2-LABEL: t4:
; VFP2: vnmla.f64
-; NEON: t4:
+; NEON-LABEL: t4:
; NEON: vnmla.f64
-; A8U: t4:
+; A8U-LABEL: t4:
; A8U: vnmul.f64 d
; A8U: vsub.f64 d
-; A8: t4:
+; A8-LABEL: t4:
; A8: vnmul.f64 d
; A8: vsub.f64 d
%0 = fmul double %a, %b
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define float @f(i32 %a) {
-;CHECK: f:
+;CHECK-LABEL: f:
;CHECK: vmov
;CHECK-NEXT: vcvt.f32.s32
;CHECK-NEXT: vmov
}
define double @g(i32 %a) {
-;CHECK: g:
+;CHECK-LABEL: g:
;CHECK: vmov
;CHECK-NEXT: vcvt.f64.s32
;CHECK-NEXT: vmov
}
define double @uint_to_double(i32 %a) {
-;CHECK: uint_to_double:
+;CHECK-LABEL: uint_to_double:
;CHECK: vmov
;CHECK-NEXT: vcvt.f64.u32
;CHECK-NEXT: vmov
}
define float @uint_to_float(i32 %a) {
-;CHECK: uint_to_float:
+;CHECK-LABEL: uint_to_float:
;CHECK: vmov
;CHECK-NEXT: vcvt.f32.u32
;CHECK-NEXT: vmov
}
define double @h(double* %v) {
-;CHECK: h:
+;CHECK-LABEL: h:
;CHECK: vldr
;CHECK-NEXT: vmov
entry:
}
define float @h2() {
-;CHECK: h2:
+;CHECK-LABEL: h2:
;CHECK: mov r0, #1065353216
entry:
ret float 1.000000e+00
}
define double @f2(double %a) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK-NOT: vmov
ret double %a
}
define void @f3() {
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK-NOT: vmov
;CHECK: f4
entry:
@z = common global i16 0
define arm_aapcs_vfpcc void @foo() nounwind {
-; CHECK: foo:
-; CHECK-FP6: foo:
+; CHECK-LABEL: foo:
+; CHECK-FP6-LABEL: foo:
entry:
%0 = load i16* @x, align 2
%1 = load i16* @y, align 2
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+vfp2 | FileCheck %s
define float @f1(float %a, float %b) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
;CHECK: vadd.f32
entry:
%tmp = fadd float %a, %b ; <float> [#uses=1]
}
define double @f2(double %a, double %b) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK: vadd.f64
entry:
%tmp = fadd double %a, %b ; <double> [#uses=1]
}
define float @f3(float %a, float %b) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK: vmul.f32
entry:
%tmp = fmul float %a, %b ; <float> [#uses=1]
}
define double @f4(double %a, double %b) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
;CHECK: vmul.f64
entry:
%tmp = fmul double %a, %b ; <double> [#uses=1]
}
define float @f5(float %a, float %b) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
;CHECK: vsub.f32
entry:
%tmp = fsub float %a, %b ; <float> [#uses=1]
}
define double @f6(double %a, double %b) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
;CHECK: vsub.f64
entry:
%tmp = fsub double %a, %b ; <double> [#uses=1]
}
define float @f7(float %a) {
-;CHECK: f7:
+;CHECK-LABEL: f7:
;CHECK: eor
entry:
%tmp1 = fsub float -0.000000e+00, %a ; <float> [#uses=1]
}
define double @f8(double %a) {
-;CHECK: f8:
+;CHECK-LABEL: f8:
;CHECK: vneg.f64
entry:
%tmp1 = fsub double -0.000000e+00, %a ; <double> [#uses=1]
}
define float @f9(float %a, float %b) {
-;CHECK: f9:
+;CHECK-LABEL: f9:
;CHECK: vdiv.f32
entry:
%tmp1 = fdiv float %a, %b ; <float> [#uses=1]
}
define double @f10(double %a, double %b) {
-;CHECK: f10:
+;CHECK-LABEL: f10:
;CHECK: vdiv.f64
entry:
%tmp1 = fdiv double %a, %b ; <double> [#uses=1]
}
define float @f11(float %a) {
-;CHECK: f11:
+;CHECK-LABEL: f11:
;CHECK: bic
entry:
%tmp1 = call float @fabsf( float %a ) readnone ; <float> [#uses=1]
declare float @fabsf(float)
define double @f12(double %a) {
-;CHECK: f12:
+;CHECK-LABEL: f12:
;CHECK: vabs.f64
entry:
%tmp1 = call double @fabs( double %a ) readnone ; <double> [#uses=1]
; Disable this optimization unless we know one of them is zero.
define arm_apcscc i32 @t1(float* %a, float* %b) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: vldr [[S0:s[0-9]+]],
; CHECK: vldr [[S1:s[0-9]+]],
; CHECK: vcmpe.f32 [[S1]], [[S0]]
; +0.0 == -0.0
define arm_apcscc i32 @t2(double* %a, double* %b) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK-NOT: vldr
; CHECK: ldr [[REG1:(r[0-9]+)]], [r0]
; CHECK: ldr [[REG2:(r[0-9]+)]], [r0, #4]
define arm_apcscc i32 @t3(float* %a, float* %b) nounwind {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK-NOT: vldr
; CHECK: ldr [[REG3:(r[0-9]+)]], [r0]
; CHECK: mvn [[REG4:(r[0-9]+)]], #-2147483648
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define i32 @f1(float %a) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
;CHECK: vcmpe.f32
;CHECK: movmi
entry:
}
define i32 @f2(float %a) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK: vcmpe.f32
;CHECK: moveq
entry:
}
define i32 @f3(float %a) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK: vcmpe.f32
;CHECK: movgt
entry:
}
define i32 @f4(float %a) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
;CHECK: vcmpe.f32
;CHECK: movge
entry:
}
define i32 @f5(float %a) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
;CHECK: vcmpe.f32
;CHECK: movls
entry:
}
define i32 @f6(float %a) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
;CHECK: vcmpe.f32
;CHECK: movne
entry:
}
define i32 @g1(double %a) {
-;CHECK: g1:
+;CHECK-LABEL: g1:
;CHECK: vcmpe.f64
;CHECK: movmi
entry:
define i32 @f7(float %a, float %b) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: vcmpe.f32
; CHECK: vmrs APSR_nzcv, fpscr
; CHECK: movweq
define float @t1(float %x) nounwind readnone optsize {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: vmov.f32 s{{.*}}, #4.000000e+00
%0 = fadd float %x, 4.000000e+00
ret float %0
define double @t2(double %x) nounwind readnone optsize {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: vmov.f64 d{{.*}}, #3.000000e+00
%0 = fadd double %x, 3.000000e+00
ret double %0
define double @t3(double %x) nounwind readnone optsize {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: vmov.f64 d{{.*}}, #-1.300000e+01
%0 = fmul double %x, -1.300000e+01
ret double %0
define float @t4(float %x) nounwind readnone optsize {
entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: vmov.f32 s{{.*}}, #-2.400000e+01
%0 = fmul float %x, -2.400000e+01
ret float %0
; RUN: llc < %s -mtriple=arm-apple-darwin | FileCheck %s
define float @f1(double %x) {
-;CHECK-VFP: f1:
+;CHECK-VFP-LABEL: f1:
;CHECK-VFP: vcvt.f32.f64
-;CHECK: f1:
+;CHECK-LABEL: f1:
;CHECK: truncdfsf2
entry:
%tmp1 = fptrunc double %x to float ; <float> [#uses=1]
}
define double @f2(float %x) {
-;CHECK-VFP: f2:
+;CHECK-VFP-LABEL: f2:
;CHECK-VFP: vcvt.f64.f32
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK: extendsfdf2
entry:
%tmp1 = fpext float %x to double ; <double> [#uses=1]
}
define i32 @f3(float %x) {
-;CHECK-VFP: f3:
+;CHECK-VFP-LABEL: f3:
;CHECK-VFP: vcvt.s32.f32
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK: fixsfsi
entry:
%tmp = fptosi float %x to i32 ; <i32> [#uses=1]
}
define i32 @f4(float %x) {
-;CHECK-VFP: f4:
+;CHECK-VFP-LABEL: f4:
;CHECK-VFP: vcvt.u32.f32
-;CHECK: f4:
+;CHECK-LABEL: f4:
;CHECK: fixunssfsi
entry:
%tmp = fptoui float %x to i32 ; <i32> [#uses=1]
}
define i32 @f5(double %x) {
-;CHECK-VFP: f5:
+;CHECK-VFP-LABEL: f5:
;CHECK-VFP: vcvt.s32.f64
-;CHECK: f5:
+;CHECK-LABEL: f5:
;CHECK: fixdfsi
entry:
%tmp = fptosi double %x to i32 ; <i32> [#uses=1]
}
define i32 @f6(double %x) {
-;CHECK-VFP: f6:
+;CHECK-VFP-LABEL: f6:
;CHECK-VFP: vcvt.u32.f64
-;CHECK: f6:
+;CHECK-LABEL: f6:
;CHECK: fixunsdfsi
entry:
%tmp = fptoui double %x to i32 ; <i32> [#uses=1]
}
define float @f7(i32 %a) {
-;CHECK-VFP: f7:
+;CHECK-VFP-LABEL: f7:
;CHECK-VFP: vcvt.f32.s32
-;CHECK: f7:
+;CHECK-LABEL: f7:
;CHECK: floatsisf
entry:
%tmp = sitofp i32 %a to float ; <float> [#uses=1]
}
define double @f8(i32 %a) {
-;CHECK-VFP: f8:
+;CHECK-VFP-LABEL: f8:
;CHECK-VFP: vcvt.f64.s32
-;CHECK: f8:
+;CHECK-LABEL: f8:
;CHECK: floatsidf
entry:
%tmp = sitofp i32 %a to double ; <double> [#uses=1]
}
define float @f9(i32 %a) {
-;CHECK-VFP: f9:
+;CHECK-VFP-LABEL: f9:
;CHECK-VFP: vcvt.f32.u32
-;CHECK: f9:
+;CHECK-LABEL: f9:
;CHECK: floatunsisf
entry:
%tmp = uitofp i32 %a to float ; <float> [#uses=1]
}
define double @f10(i32 %a) {
-;CHECK-VFP: f10:
+;CHECK-VFP-LABEL: f10:
;CHECK-VFP: vcvt.f64.u32
-;CHECK: f10:
+;CHECK-LABEL: f10:
;CHECK: floatunsidf
entry:
%tmp = uitofp i32 %a to double ; <double> [#uses=1]
; RUN: llc < %s -march=arm -mattr=+vfp2 | FileCheck %s
define float @f1(float %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mov r0, #0
ret float 0.000000e+00
}
define float @f2(float* %v, float %u) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: vldr{{.*}}[
%tmp = load float* %v ; <float> [#uses=1]
%tmp1 = fadd float %tmp, %u ; <float> [#uses=1]
}
define float @f2offset(float* %v, float %u) {
-; CHECK: f2offset:
+; CHECK-LABEL: f2offset:
; CHECK: vldr{{.*}}, #4]
%addr = getelementptr float* %v, i32 1
%tmp = load float* %addr
}
define float @f2noffset(float* %v, float %u) {
-; CHECK: f2noffset:
+; CHECK-LABEL: f2noffset:
; CHECK: vldr{{.*}}, #-4]
%addr = getelementptr float* %v, i32 -1
%tmp = load float* %addr
}
define void @f3(float %a, float %b, float* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: vstr{{.*}}[
%tmp = fadd float %a, %b ; <float> [#uses=1]
store float %tmp, float* %v
store i16 %tmp, i16* null
ret void
}
-; CHECK: foo9:
+; CHECK-LABEL: foo9:
; CHECK: vmov r0, s0
; Check generated fused MAC and MLS.
define double @fusedMACTest1(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest1:
+;CHECK-LABEL: fusedMACTest1:
;CHECK: vfma.f64
%1 = fmul double %d1, %d2
%2 = fadd double %1, %d3
}
define float @fusedMACTest2(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest2:
+;CHECK-LABEL: fusedMACTest2:
;CHECK: vfma.f32
%1 = fmul float %f1, %f2
%2 = fadd float %1, %f3
}
define double @fusedMACTest3(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest3:
+;CHECK-LABEL: fusedMACTest3:
;CHECK: vfms.f64
%1 = fmul double %d2, %d3
%2 = fsub double %d1, %1
}
define float @fusedMACTest4(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest4:
+;CHECK-LABEL: fusedMACTest4:
;CHECK: vfms.f32
%1 = fmul float %f2, %f3
%2 = fsub float %f1, %1
}
define double @fusedMACTest5(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest5:
+;CHECK-LABEL: fusedMACTest5:
;CHECK: vfnma.f64
%1 = fmul double %d1, %d2
%2 = fsub double -0.0, %1
}
define float @fusedMACTest6(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest6:
+;CHECK-LABEL: fusedMACTest6:
;CHECK: vfnma.f32
%1 = fmul float %f1, %f2
%2 = fsub float -0.0, %1
}
define double @fusedMACTest7(double %d1, double %d2, double %d3) {
-;CHECK: fusedMACTest7:
+;CHECK-LABEL: fusedMACTest7:
;CHECK: vfnms.f64
%1 = fmul double %d1, %d2
%2 = fsub double %1, %d3
}
define float @fusedMACTest8(float %f1, float %f2, float %f3) {
-;CHECK: fusedMACTest8:
+;CHECK-LABEL: fusedMACTest8:
;CHECK: vfnms.f32
%1 = fmul float %f1, %f2
%2 = fsub float %1, %f3
}
define <2 x float> @fusedMACTest9(<2 x float> %a, <2 x float> %b) {
-;CHECK: fusedMACTest9:
+;CHECK-LABEL: fusedMACTest9:
;CHECK: vfma.f32
%mul = fmul <2 x float> %a, %b
%add = fadd <2 x float> %mul, %a
}
define <2 x float> @fusedMACTest10(<2 x float> %a, <2 x float> %b) {
-;CHECK: fusedMACTest10:
+;CHECK-LABEL: fusedMACTest10:
;CHECK: vfms.f32
%mul = fmul <2 x float> %a, %b
%sub = fsub <2 x float> %a, %mul
}
define <4 x float> @fusedMACTest11(<4 x float> %a, <4 x float> %b) {
-;CHECK: fusedMACTest11:
+;CHECK-LABEL: fusedMACTest11:
;CHECK: vfma.f32
%mul = fmul <4 x float> %a, %b
%add = fadd <4 x float> %mul, %a
}
define <4 x float> @fusedMACTest12(<4 x float> %a, <4 x float> %b) {
-;CHECK: fusedMACTest12:
+;CHECK-LABEL: fusedMACTest12:
;CHECK: vfms.f32
%mul = fmul <4 x float> %a, %b
%sub = fsub <4 x float> %a, %mul
-; LinuxPIC: test1:
+; LinuxPIC-LABEL: test1:
; LinuxPIC: ldr r0, .LCPI0_0
; LinuxPIC: ldr r1, .LCPI0_1
define i32 @t() nounwind readonly {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: ldr
; CHECK-NEXT: ldr
%0 = load i32* @x, align 4 ; <i32> [#uses=1]
define weak hidden void @t1() nounwind {
; LINUX: .hidden t1
-; LINUX: t1:
+; LINUX-LABEL: t1:
; DARWIN: .private_extern _t1
-; DARWIN: t1:
+; DARWIN-LABEL: t1:
ret void
}
define weak void @t2() nounwind {
-; LINUX: t2:
+; LINUX-LABEL: t2:
; LINUX: .hidden a
-; DARWIN: t2:
+; DARWIN-LABEL: t2:
; DARWIN: .private_extern _a
ret void
}
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s -check-prefix=SWIFT
define i32 @t1(i32 %a, i32 %b) {
-; A8: t1:
-; SWIFT: t1:
+; A8-LABEL: t1:
+; SWIFT-LABEL: t1:
%tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true
define void @t(double %a, double %b, double %c, double %d, i32* nocapture %solutions, double* nocapture %x) nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: vpop {d8}
; CHECK-NOT: vpopne
; CHECK: pop {r7, pc}
%struct.xyz_t = type { double, double, double }
define i32 @effie(i32 %tsets, %struct.xyz_t* nocapture %p, i32 %a, i32 %b, i32 %c) nounwind readonly noinline {
-; CHECK: effie:
+; CHECK-LABEL: effie:
entry:
%0 = icmp sgt i32 %tsets, 0
br i1 %0, label %bb.nph, label %bb6
; RUN: llc < %s -mtriple=arm-apple-darwin -mcpu=cortex-a8 | FileCheck %s
define i32 @f1(i32 %a, i32 %b, i32 %c) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mlsne r0, r0, r1, r2
%tmp1 = icmp eq i32 %a, 0
br i1 %tmp1, label %cond_false, label %cond_true
; RUN: llc < %s -march=arm -mattr=+v4t | FileCheck %s
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: bxlt lr
%tmp2 = icmp sgt i32 %c, 10
%tmp5 = icmp slt i32 %d, 4
}
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: bxgt lr
; CHECK: cmp
; CHECK: addge
; RUN: llc < %s -march=arm -mattr=+v4t | grep bx | count 2
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: cmp r2, #1
; CHECK: cmpne r2, #7
switch i32 %c, label %cond_next [
; RUN: llc < %s -march=arm | FileCheck %s
; Do not if-convert when branches go to the different loops.
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK-NOT: subgt
; CHECK-NOT: suble
; Don't use
}
define i32 @t1(i32 %a, i32 %b) {
-; A8: t1:
+; A8-LABEL: t1:
; A8: poplt {r7, pc}
-; SWIFT: t1:
+; SWIFT-LABEL: t1:
; SWIFT: pop {r7, pc}
; SWIFT: pop {r7, pc}
entry:
; The indirect branch has the two destinations as successors. The lone PHI
; statement shouldn't be implicitly defined.
-; CHECK: func:
+; CHECK-LABEL: func:
; CHECK: Ltmp1: @ Block address taken
; CHECK-NOT: @ implicit-def: R0
; CHECK: @ 4-byte Reload
@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
define internal i32 @foo(i32 %i) nounwind {
-; ARM: foo:
-; THUMB: foo:
-; THUMB2: foo:
+; ARM-LABEL: foo:
+; THUMB-LABEL: foo:
+; THUMB2-LABEL: foo:
entry:
%0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
; RUN: llc -mtriple=thumbv7-none-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s
; check if regs are passing correctly
define void @i64_write(i64* %p, i64 %val) nounwind {
-; CHECK: i64_write:
+; CHECK-LABEL: i64_write:
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
%1 = tail call i64 asm sideeffect "1: ldrexd $0, ${0:H}, [$2]\0A strexd $0, $3, ${3:H}, [$2]\0A teq $0, #0\0A bne 1b", "=&r,=*Qo,r,r,~{cc}"(i64* %p, i64* %p, i64 %val) nounwind
; check if register allocation can reuse the registers
define void @multi_writes(i64* %p, i64 %val1, i64 %val2, i64 %val3, i64 %val4, i64 %val5, i64 %val6) nounwind {
entry:
-; CHECK: multi_writes:
+; CHECK-LABEL: multi_writes:
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; check: strexd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; check if callee-saved registers used by inline asm are saved/restored
define void @foo(i64* %p, i64 %i) nounwind {
-; CHECK:foo:
+; CHECK-LABEL:foo:
; CHECK: {{push|push.w}} {{{r[4-9]|r10|r11}}
; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], {{r[0-9]?[13579]}}, [r{{[0-9]+}}]
; CHECK: strexd [[REG1]], {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
; return *p;
define i64 @ldrd_test(i64* %p) nounwind {
-; CHECK: ldrd_test:
+; CHECK-LABEL: ldrd_test:
%1 = tail call i64 asm "ldrd $0, ${0:H}, [$1]", "=r,r"(i64* %p) nounwind
ret i64 %1
}
define i64 @QR_test(i64* %p) nounwind {
-; CHECK: QR_test:
+; CHECK-LABEL: QR_test:
; CHECK: ldrd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
%1 = tail call i64 asm "ldrd ${0:Q}, ${0:R}, [$1]", "=r,r"(i64* %p) nounwind
ret i64 %1
}
define i64 @defuse_test(i64 %p) nounwind {
-; CHECK: defuse_test:
+; CHECK-LABEL: defuse_test:
; CHECK: add {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}, #1
%1 = tail call i64 asm "add $0, ${0:H}, #1", "=r,0"(i64 %p) nounwind
ret i64 %1
; *p = (hi << 32) | lo;
define void @strd_test(i64* %p, i32 %lo, i32 %hi) nounwind {
-; CHECK: strd_test:
+; CHECK-LABEL: strd_test:
; CHECK: strd {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
%1 = zext i32 %hi to i64
%2 = shl nuw i64 %1, 32
entry:
%0 = tail call double asm "mov ${0:R}, #4\0A", "=&r"()
ret double %0
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: mov r1, #4
}
entry:
%0 = tail call double asm "mov ${0:Q}, #4\0A", "=&r"()
ret double %0
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: mov r0, #4
}
@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
define i32 @t1() {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: pop
-; V4T: t1:
+; V4T-LABEL: t1:
; V4T: pop
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
}
define i32 @t2() {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: pop
-; V4T: t2:
+; V4T-LABEL: t2:
; V4T: pop
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 2) ; <i32> [#uses=1]
%tmp3 = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 3) ; <i32> [#uses=1]
}
define i32 @t3() {
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: ldmib
; CHECK: pop
-; V4T: t3:
+; V4T-LABEL: t3:
; V4T: ldmib
; V4T: pop
; V4T-NEXT: bx lr
; RUN: llc < %s -march=arm | FileCheck %s
define i32 @f1(i32* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldr r0
entry:
%tmp = load i32* %v
}
define i32 @f2(i32* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldr r0
entry:
%tmp2 = getelementptr i32* %v, i32 1023
}
define i32 @f3(i32* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov
; CHECK: ldr r0
entry:
}
define i32 @f4(i32 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: mvn
; CHECK: ldr r0
entry:
}
define i32 @f5(i32 %base, i32 %offset) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldr r0
entry:
%tmp1 = add i32 %base, %offset
}
define i32 @f6(i32 %base, i32 %offset) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ldr r0{{.*}}lsl{{.*}}
entry:
%tmp1 = shl i32 %offset, 2
}
define i32 @f7(i32 %base, i32 %offset) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ldr r0{{.*}}lsr{{.*}}
entry:
%tmp1 = lshr i32 %offset, 2
define i64 @t(i64 %a) nounwind readonly {
entry:
-; A8: t:
+; A8-LABEL: t:
; A8: ldrd r2, r3, [r2]
-; M3: t:
+; M3-LABEL: t:
; M3-NOT: ldrd
%0 = load i64** @b, align 4
; rdar://8944252
define void @t(i32 %width, float* nocapture %src, float* nocapture %dst, i32 %index) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
entry:
%src6 = bitcast float* %src to i8*
%0 = icmp eq i32 %width, 0
%0 = type { i32, i32 }
-; CHECK: f0:
+; CHECK-LABEL: f0:
; CHECK: ldrexd
define i64 @f0(i8* %p) nounwind readonly {
entry:
ret i64 %4
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: strexd
define i32 @f1(i8* %ptr, i64 %val) nounwind {
entry:
ret i32 and (i32 ptrtoint (i32* @a to i32), i32 255)
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: ldrb r0, .LCPI0_0
; Codegen should only compare one bit of the loaded value.
; rdar://10887484
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: ldrb r[[R0:[0-9]+]], [r0]
; CHECK: tst.w r[[R0]], #1
define void @foo(i8* %call, double* %p) nounwind {
; RUN: llc < %s -march=arm | FileCheck %s
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
entry:
ret i64 0
}
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
entry:
ret i64 1
}
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvn r0, #-2147483648
entry:
ret i64 2147483647
}
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mov r0, #-2147483648
entry:
ret i64 2147483648
}
define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvn r0, #0
; CHECK: mvn r1, #-2147483648
entry:
}
define i64 @f6(i64 %x, i64 %y) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: adds
; CHECK: adc
entry:
}
define void @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
entry:
%tmp = call i64 @f8( ) ; <i64> [#uses=0]
ret void
declare i64 @f8()
define i64 @f9(i64 %a, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: subs r
; CHECK: sbc
entry:
}
define i64 @f(i32 %a, i32 %b) {
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: smull
entry:
%tmp = sext i32 %a to i64 ; <i64> [#uses=1]
}
define i64 @g(i32 %a, i32 %b) {
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: umull
entry:
%tmp = zext i32 %a to i64 ; <i64> [#uses=1]
}
define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
entry:
%a = alloca i64, align 8 ; <i64*> [#uses=1]
%retval = load i64* %a ; <i64> [#uses=1]
; Check generated signed and unsigned multiply accumulate long.
define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest1:
+;CHECK-LABEL: MACLongTest1:
;CHECK: umlal
%conv = zext i32 %a to i64
%conv1 = zext i32 %b to i64
}
define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest2:
+;CHECK-LABEL: MACLongTest2:
;CHECK: smlal
%conv = sext i32 %a to i64
%conv1 = sext i32 %b to i64
}
define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest3:
+;CHECK-LABEL: MACLongTest3:
;CHECK: umlal
%conv = zext i32 %b to i64
%conv1 = zext i32 %a to i64
}
define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest4:
+;CHECK-LABEL: MACLongTest4:
;CHECK: smlal
%conv = sext i32 %b to i64
%conv1 = sext i32 %a to i64
; LSR should compare against the post-incremented induction variable.
; In this case, the immediate value is -2 which requires a cmn instruction.
;
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: %for.body
; CHECK: sub{{.*}}[[IV:r[0-9]+]], #2
; CHECK: cmn{{.*}}[[IV]], #2
define i32 @f1(i32 %cond1, i32 %x1, i32 %x2, i32 %x3) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cmp
; CHECK: moveq
; CHECK-NOT: cmp
; rdar://10660865
define void @f2() nounwind ssp {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cmp
; CHECK: poplt
; CHECK-NOT: cmp
; rdar://12462006
define i8* @f3(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: sub
; CHECK: cmp
; CHECK: blt
define void @t(i32* nocapture %vals, i32 %c) nounwind {
entry:
-; ARM: t:
+; ARM-LABEL: t:
; ARM: ldr [[REGISTER_1:r[0-9]+]], LCPI0_0
; Unfortunately currently ARM codegen doesn't cse the ldr from constantpool.
; The issue is it can be read by an "add pc" or a "ldr [pc]" so it's messy
; ARM: ldr r{{[0-9]+}}, [pc, [[REGISTER_1]]]
; ARM: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
-; MOVT: t:
+; MOVT-LABEL: t:
; MOVT: movw [[REGISTER_2:r[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+8))
; MOVT: movt [[REGISTER_2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+8))
; MOVT: LPC0_0:
; MOVT: ldr r{{[0-9]+}}, [pc, [[REGISTER_2]]]
; MOVT: ldr r{{[0-9]+}}, [r{{[0-9]+}}]
-; THUMB: t:
+; THUMB-LABEL: t:
%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
br i1 %0, label %return, label %bb.nph
define i32 @t0() {
entry:
-; CHECK: t0:
+; CHECK-LABEL: t0:
; CHECK: vldr [[REG1:d[0-9]+]],
; CHECK: vstr [[REG1]],
call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds (%struct.x* @dst, i32 0, i32 0), i8* getelementptr inbounds (%struct.x* @src, i32 0, i32 0), i32 11, i32 8, i1 false)
define void @t1(i8* nocapture %C) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
; CHECK: adds r0, #15
define void @t2(i8* nocapture %C) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: ldr [[REG2:r[0-9]+]], [r1, #32]
; CHECK: str [[REG2]], [r0, #32]
; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
define void @t3(i8* nocapture %C) nounwind {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
; CHECK: vst1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r0]
; CHECK: adds r0, #16
define void @t4(i8* nocapture %C) nounwind {
entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: vld1.8 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
; CHECK: vst1.8 {[[REG3]], [[REG4]]}, [r0]
tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([18 x i8]* @.str4, i64 0, i64 0), i64 18, i32 1, i1 false)
define void @t5(i8* nocapture %C) nounwind {
entry:
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: movs [[REG5:r[0-9]+]], #0
; CHECK: strb [[REG5]], [r0, #6]
; CHECK: movw [[REG6:r[0-9]+]], #21587
define void @t6() nounwind {
entry:
-; CHECK: t6:
+; CHECK-LABEL: t6:
; CHECK: vld1.8 {[[REG8:d[0-9]+]]}, [r0]
; CHECK: vstr [[REG8]], [r1]
; CHECK: adds r1, #6
define void @t1(i8* nocapture %c) nounwind optsize {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: movs r1, #0
; CHECK: str r1, [r0]
; CHECK: str r1, [r0, #4]
define void @t2() nounwind ssp {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: add.w r1, r0, #10
; CHECK: vmov.i32 {{q[0-9]+}}, #0x0
; CHECK: vst1.16 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
ret i32 %tmp2
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mls r0, r0, r1, r2
-; NO_MULOPS: f1:
+; NO_MULOPS-LABEL: f1:
; NO_MULOPS: mul r0, r0, r1
; NO_MULOPS-NEXT: sub r0, r2, r0
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mul r0, r0, r1
; CHECK-NEXT: sub r0, r0, r2
-; NO_MULOPS: f2:
+; NO_MULOPS-LABEL: f2:
; NO_MULOPS: mul r0, r0, r1
; NO_MULOPS-NEXT: sub r0, r0, r2
; rdar://7317664
define i32 @t(i32 %X) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movt r0, #65535
entry:
%0 = or i32 %X, -65536
}
define i32 @t2(i32 %X) nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: movt r0, #65534
entry:
%0 = or i32 %X, -131072
define i32 @t9(i32 %v) nounwind readnone {
entry:
-; CHECK: t9:
+; CHECK-LABEL: t9:
; CHECK: add r0, r0, r0, lsl #3
%0 = mul i32 %v, 9
ret i32 %0
define i32 @t7(i32 %v) nounwind readnone {
entry:
-; CHECK: t7:
+; CHECK-LABEL: t7:
; CHECK: rsb r0, r0, r0, lsl #3
%0 = mul i32 %v, 7
ret i32 %0
define i32 @t5(i32 %v) nounwind readnone {
entry:
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: add r0, r0, r0, lsl #2
%0 = mul i32 %v, 5
ret i32 %0
define i32 @t3(i32 %v) nounwind readnone {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: add r0, r0, r0, lsl #1
%0 = mul i32 %v, 3
ret i32 %0
define i32 @t12288(i32 %v) nounwind readnone {
entry:
-; CHECK: t12288:
+; CHECK-LABEL: t12288:
; CHECK: add r0, r0, r0, lsl #1
; CHECK: lsl{{.*}}#12
%0 = mul i32 %v, 12288
define i32 @tn9(i32 %v) nounwind readnone {
entry:
-; CHECK: tn9:
+; CHECK-LABEL: tn9:
; CHECK: add r0, r0, r0, lsl #3
; CHECK: rsb r0, r0, #0
%0 = mul i32 %v, -9
define i32 @tn7(i32 %v) nounwind readnone {
entry:
-; CHECK: tn7:
+; CHECK-LABEL: tn7:
; CHECK: sub r0, r0, r0, lsl #3
%0 = mul i32 %v, -7
ret i32 %0
define i32 @tn5(i32 %v) nounwind readnone {
entry:
-; CHECK: tn5:
+; CHECK-LABEL: tn5:
; CHECK: add r0, r0, r0, lsl #2
; CHECK: rsb r0, r0, #0
%0 = mul i32 %v, -5
define i32 @tn3(i32 %v) nounwind readnone {
entry:
-; CHECK: tn3:
+; CHECK-LABEL: tn3:
; CHECK: sub r0, r0, r0, lsl #2
%0 = mul i32 %v, -3
ret i32 %0
define i32 @tn12288(i32 %v) nounwind readnone {
entry:
-; CHECK: tn12288:
+; CHECK-LABEL: tn12288:
; CHECK: sub r0, r0, r0, lsl #2
; CHECK: lsl{{.*}}#12
%0 = mul i32 %v, -12288
; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s -check-prefix=M3
define i32 @smulhi(i32 %x, i32 %y) nounwind {
-; V6: smulhi:
+; V6-LABEL: smulhi:
; V6: smmul
-; V4: smulhi:
+; V4-LABEL: smulhi:
; V4: smull
-; M3: smulhi:
+; M3-LABEL: smulhi:
; M3: smull
%tmp = sext i32 %x to i64 ; <i64> [#uses=1]
%tmp1 = sext i32 %y to i64 ; <i64> [#uses=1]
}
define i32 @umulhi(i32 %x, i32 %y) nounwind {
-; V6: umulhi:
+; V6-LABEL: umulhi:
; V6: umull
-; V4: umulhi:
+; V4-LABEL: umulhi:
; V4: umull
-; M3: umulhi:
+; M3-LABEL: umulhi:
; M3: umull
%tmp = zext i32 %x to i64 ; <i64> [#uses=1]
%tmp1 = zext i32 %y to i64 ; <i64> [#uses=1]
; rdar://r10152911
define i32 @t3(i32 %a) nounwind {
-; V6: t3:
+; V6-LABEL: t3:
; V6: smmla
-; V4: t3:
+; V4-LABEL: t3:
; V4: smull
-; M3: t3:
+; M3-LABEL: t3:
; M3-NOT: smmla
; M3: smull
entry:
@.str = private unnamed_addr constant [12 x i8] c"S317\09%.5g \0A\00", align 1
-; CHECK-LINUXA5: main:
-; CHECK-LINUXA8: main:
-; CHECK-LINUXA9: main:
-; CHECK-LINUXA15: main:
-; CHECK-LINUXSWIFT: main:
-; CHECK-UNSAFEA5: main:
-; CHECK-UNSAFEA8: main:
-; CHECK-UNSAFEA9: main:
-; CHECK-UNSAFEA15: main:
-; CHECK-UNSAFESWIFT: main:
-; CHECK-DARWINA5: main:
-; CHECK-DARWINA8: main:
-; CHECK-DARWINA9: main:
-; CHECK-DARWINA15: main:
-; CHECK-DARWINSWIFT: main:
+; CHECK-LINUXA5-LABEL: main:
+; CHECK-LINUXA8-LABEL: main:
+; CHECK-LINUXA9-LABEL: main:
+; CHECK-LINUXA15-LABEL: main:
+; CHECK-LINUXSWIFT-LABEL: main:
+; CHECK-UNSAFEA5-LABEL: main:
+; CHECK-UNSAFEA8-LABEL: main:
+; CHECK-UNSAFEA9-LABEL: main:
+; CHECK-UNSAFEA15-LABEL: main:
+; CHECK-UNSAFESWIFT-LABEL: main:
+; CHECK-DARWINA5-LABEL: main:
+; CHECK-DARWINA8-LABEL: main:
+; CHECK-DARWINA9-LABEL: main:
+; CHECK-DARWINA15-LABEL: main:
+; CHECK-DARWINSWIFT-LABEL: main:
define i32 @main() {
entry:
br label %for.body
; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
define float @fmin_ole(float %x) nounwind {
-;CHECK: fmin_ole:
+;CHECK-LABEL: fmin_ole:
;CHECK: vmin.f32
%cond = fcmp ole float 1.0, %x
%min1 = select i1 %cond, float 1.0, float %x
}
define float @fmin_ole_zero(float %x) nounwind {
-;CHECK: fmin_ole_zero:
+;CHECK-LABEL: fmin_ole_zero:
;CHECK-NOT: vmin.f32
%cond = fcmp ole float 0.0, %x
%min1 = select i1 %cond, float 0.0, float %x
}
define float @fmin_ult(float %x) nounwind {
-;CHECK: fmin_ult:
+;CHECK-LABEL: fmin_ult:
;CHECK: vmin.f32
%cond = fcmp ult float %x, 1.0
%min1 = select i1 %cond, float %x, float 1.0
}
define float @fmax_ogt(float %x) nounwind {
-;CHECK: fmax_ogt:
+;CHECK-LABEL: fmax_ogt:
;CHECK: vmax.f32
%cond = fcmp ogt float 1.0, %x
%max1 = select i1 %cond, float 1.0, float %x
}
define float @fmax_uge(float %x) nounwind {
-;CHECK: fmax_uge:
+;CHECK-LABEL: fmax_uge:
;CHECK: vmax.f32
%cond = fcmp uge float %x, 1.0
%max1 = select i1 %cond, float %x, float 1.0
}
define float @fmax_uge_zero(float %x) nounwind {
-;CHECK: fmax_uge_zero:
+;CHECK-LABEL: fmax_uge_zero:
;CHECK-NOT: vmax.f32
%cond = fcmp uge float %x, 0.0
%max1 = select i1 %cond, float %x, float 0.0
}
define float @fmax_olt_reverse(float %x) nounwind {
-;CHECK: fmax_olt_reverse:
+;CHECK-LABEL: fmax_olt_reverse:
;CHECK: vmax.f32
%cond = fcmp olt float %x, 1.0
%max1 = select i1 %cond, float 1.0, float %x
}
define float @fmax_ule_reverse(float %x) nounwind {
-;CHECK: fmax_ule_reverse:
+;CHECK-LABEL: fmax_ule_reverse:
;CHECK: vmax.f32
%cond = fcmp ult float 1.0, %x
%max1 = select i1 %cond, float %x, float 1.0
}
define float @fmin_oge_reverse(float %x) nounwind {
-;CHECK: fmin_oge_reverse:
+;CHECK-LABEL: fmin_oge_reverse:
;CHECK: vmin.f32
%cond = fcmp oge float %x, 1.0
%min1 = select i1 %cond, float 1.0, float %x
}
define float @fmin_ugt_reverse(float %x) nounwind {
-;CHECK: fmin_ugt_reverse:
+;CHECK-LABEL: fmin_ugt_reverse:
;CHECK: vmin.f32
%cond = fcmp ugt float 1.0, %x
%min1 = select i1 %cond, float %x, float 1.0
define void @t(float %x) nounwind ssp {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK-NOT: vmov
; CHECK: bl
%0 = bitcast float %x to i32
; Implement ctpop with vcnt
define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
-;CHECK: vcnt8:
+;CHECK-LABEL: vcnt8:
;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
}
define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
-;CHECK: vcntQ8:
+;CHECK-LABEL: vcntQ8:
;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
}
define <4 x i16> @vcnt16(<4 x i16>* %A) nounwind {
-; CHECK: vcnt16:
+; CHECK-LABEL: vcnt16:
; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
}
define <8 x i16> @vcntQ16(<8 x i16>* %A) nounwind {
-; CHECK: vcntQ16:
+; CHECK-LABEL: vcntQ16:
; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
}
define <2 x i32> @vcnt32(<2 x i32>* %A) nounwind {
-; CHECK: vcnt32:
+; CHECK-LABEL: vcnt32:
; CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
; CHECK: vrev16.8 {{d[0-9]+}}, {{d[0-9]+}}
; CHECK: vadd.i8 {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
}
define <4 x i32> @vcntQ32(<4 x i32>* %A) nounwind {
-; CHECK: vcntQ32:
+; CHECK-LABEL: vcntQ32:
; CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vrev16.8 {{q[0-9]+}}, {{q[0-9]+}}
; CHECK: vadd.i8 {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32>) nounwind readnone
define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
-;CHECK: vclz8:
+;CHECK-LABEL: vclz8:
;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
}
define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
-;CHECK: vclz16:
+;CHECK-LABEL: vclz16:
;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
}
define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
-;CHECK: vclz32:
+;CHECK-LABEL: vclz32:
;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
}
define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
-;CHECK: vclzQ8:
+;CHECK-LABEL: vclzQ8:
;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
}
define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
-;CHECK: vclzQ16:
+;CHECK-LABEL: vclzQ16:
;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
}
define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
-;CHECK: vclzQ32:
+;CHECK-LABEL: vclzQ32:
;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
-;CHECK: vclss8:
+;CHECK-LABEL: vclss8:
;CHECK: vcls.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
}
define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
-;CHECK: vclss16:
+;CHECK-LABEL: vclss16:
;CHECK: vcls.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
}
define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
-;CHECK: vclss32:
+;CHECK-LABEL: vclss32:
;CHECK: vcls.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
}
define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vclsQs8:
+;CHECK-LABEL: vclsQs8:
;CHECK: vcls.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
}
define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vclsQs16:
+;CHECK-LABEL: vclsQs16:
;CHECK: vcls.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
}
define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vclsQs32:
+;CHECK-LABEL: vclsQs32:
;CHECK: vcls.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
define void @t1(i8* %ptr) nounwind {
entry:
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM-NOT: pldw [r0]
; ARM: pld [r0]
-; ARM-MP: t1:
+; ARM-MP-LABEL: t1:
; ARM-MP: pldw [r0]
; ARM-MP: pld [r0]
-; THUMB2: t1:
+; THUMB2-LABEL: t1:
; THUMB2-NOT: pldw [r0]
; THUMB2: pld [r0]
tail call void @llvm.prefetch( i8* %ptr, i32 1, i32 3, i32 1 )
define void @t2(i8* %ptr) nounwind {
entry:
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: pld [r0, #1023]
-; THUMB2: t2:
+; THUMB2-LABEL: t2:
; THUMB2: pld [r0, #1023]
%tmp = getelementptr i8* %ptr, i32 1023
tail call void @llvm.prefetch( i8* %tmp, i32 0, i32 3, i32 1 )
define void @t3(i32 %base, i32 %offset) nounwind {
entry:
-; ARM: t3:
+; ARM-LABEL: t3:
; ARM: pld [r0, r1, lsr #2]
-; THUMB2: t3:
+; THUMB2-LABEL: t3:
; THUMB2: lsrs r1, r1, #2
; THUMB2: pld [r0, r1]
%tmp1 = lshr i32 %offset, 2
define void @t4(i32 %base, i32 %offset) nounwind {
entry:
-; ARM: t4:
+; ARM-LABEL: t4:
; ARM: pld [r0, r1, lsl #2]
-; THUMB2: t4:
+; THUMB2-LABEL: t4:
; THUMB2: pld [r0, r1, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
define void @t5(i8* %ptr) nounwind {
entry:
-; ARM: t5:
+; ARM-LABEL: t5:
; ARM: pli [r0]
-; THUMB2: t5:
+; THUMB2-LABEL: t5:
; THUMB2: pli [r0]
tail call void @llvm.prefetch( i8* %ptr, i32 0, i32 3, i32 0 )
ret void
;
; RUN: llc < %s -mtriple=arm-linux-gnueabi | FileCheck %s
; CHECK: .Lfoo:
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: bl .Lfoo
; CHECK: .long .Lbaz
; CHECK: .Lbaz:
define void @t1(i16* %i_ptr, i16* %o_ptr, %struct.int32x4_t* nocapture %vT0ptr, %struct.int32x4_t* nocapture %vT1ptr) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: vld1.16
; CHECK-NOT: vmov d
; CHECK: vmovl.s16
define void @t2(i16* %i_ptr, i16* %o_ptr, %struct.int16x8_t* nocapture %vT0ptr, %struct.int16x8_t* nocapture %vT1ptr) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: vld1.16
; CHECK-NOT: vmov
; CHECK: vmul.i16
}
define <8 x i8> @t3(i8* %A, i8* %B) nounwind {
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: vld3.8
; CHECK: vmul.i8
; CHECK: vmov r
define void @t4(i32* %in, i32* %out) nounwind {
entry:
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: vld2.32
; CHECK-NOT: vmov
; CHECK: vld2.32
}
define <8 x i16> @t5(i16* %A, <8 x i16>* %B) nounwind {
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: vld1.32
; How can FileCheck match Q and D registers? We need a lisp interpreter.
; CHECK: vorr {{q[0-9]+}}, {{q[0-9]+}}, {{q[0-9]+}}
}
define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
-; CHECK: t6:
+; CHECK-LABEL: t6:
; CHECK: vldr
; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]
; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]}
define void @t7(i32* %iptr, i32* %optr) nounwind {
entry:
-; CHECK: t7:
+; CHECK-LABEL: t7:
; CHECK: vld2.32
; CHECK: vst2.32
; CHECK: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}},
; PR7156
define arm_aapcs_vfpcc i32 @t8() nounwind {
-; CHECK: t8:
+; CHECK-LABEL: t8:
; CHECK: vrsqrte.f32 q8, q8
bb.nph55.bb.nph55.split_crit_edge:
br label %bb3
; PR7157
define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
-; CHECK: t9:
+; CHECK-LABEL: t9:
; CHECK: vldr
; CHECK-NOT: vmov d{{.*}}, d16
; CHECK: vmov.i32 d17
; PR7162
define arm_aapcs_vfpcc i32 @t10() nounwind {
entry:
-; CHECK: t10:
+; CHECK-LABEL: t10:
; CHECK: vmov.i32 q[[Q0:[0-9]+]], #0x3f000000
; CHECK: vmul.f32 q8, q8, d[[DREG:[0-1]+]]
; CHECK: vadd.f32 q8, q8, q8
define <4 x double> @PR14337(<4 x double> %a, <4 x double> %b) {
%foo = fadd <4 x double> %a, %b
ret <4 x double> %foo
-; CHECK: PR14337:
+; CHECK-LABEL: PR14337:
; CHECK: vst1.64
; CHECK: vst1.64
}
define i32 @f1(i32 %a) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sbfx r0, r0, #0, #20
%tmp = shl i32 %a, 12
%tmp2 = ashr i32 %tmp, 12
define i32 @f2(i32 %a) {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: bfc r0, #20, #12
%tmp = shl i32 %a, 12
%tmp2 = lshr i32 %tmp, 12
define i32 @f3(i32 %a) {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sbfx r0, r0, #5, #3
%tmp = shl i32 %a, 24
%tmp2 = ashr i32 %tmp, 29
define i32 @f4(i32 %a) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ubfx r0, r0, #5, #3
%tmp = shl i32 %a, 24
%tmp2 = lshr i32 %tmp, 29
define i32 @f5(i32 %a) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: sbfx
; CHECK: bx
%tmp = shl i32 %a, 3
define i32 @t1(i32 %c) nounwind readnone {
entry:
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM: mov [[R1:r[0-9]+]], #101
; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
; ARM: movgt r0, #123
-; ARMT2: t1:
+; ARMT2-LABEL: t1:
; ARMT2: movw r0, #357
; ARMT2: movgt r0, #123
-; THUMB2: t1:
+; THUMB2-LABEL: t1:
; THUMB2: movw r0, #357
; THUMB2: movgt r0, #123
define i32 @t2(i32 %c) nounwind readnone {
entry:
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: mov r0, #123
; ARM: movgt r0, #101
; ARM: orrgt r0, r0, #256
-; ARMT2: t2:
+; ARMT2-LABEL: t2:
; ARMT2: mov r0, #123
; ARMT2: movwgt r0, #357
-; THUMB2: t2:
+; THUMB2-LABEL: t2:
; THUMB2: mov{{(s|\.w)}} r0, #123
; THUMB2: movwgt r0, #357
define i32 @t3(i32 %a) nounwind readnone {
entry:
-; ARM: t3:
+; ARM-LABEL: t3:
; ARM: mov r0, #0
; ARM: moveq r0, #1
-; ARMT2: t3:
+; ARMT2-LABEL: t3:
; ARMT2: mov r0, #0
; ARMT2: moveq r0, #1
-; THUMB2: t3:
+; THUMB2-LABEL: t3:
; THUMB2: mov{{(s|\.w)}} r0, #0
; THUMB2: moveq r0, #1
%0 = icmp eq i32 %a, 160
define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind {
entry:
-; ARM: t4:
+; ARM-LABEL: t4:
; ARM: ldr
; ARM: mov{{lt|ge}}
-; ARMT2: t4:
+; ARMT2-LABEL: t4:
; ARMT2: movwlt [[R0:r[0-9]+]], #65365
; ARMT2: movtlt [[R0]], #65365
-; THUMB2: t4:
+; THUMB2-LABEL: t4:
; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
%0 = icmp slt i32 %a, %b
%1 = select i1 %0, i32 4283826005, i32 %x
; rdar://9758317
define i32 @t5(i32 %a) nounwind {
entry:
-; ARM: t5:
+; ARM-LABEL: t5:
; ARM-NOT: mov
; ARM: cmp r0, #1
; ARM-NOT: mov
; ARM: movne r0, #0
-; THUMB2: t5:
+; THUMB2-LABEL: t5:
; THUMB2-NOT: mov
; THUMB2: cmp r0, #1
; THUMB2: it ne
define i32 @t6(i32 %a) nounwind {
entry:
-; ARM: t6:
+; ARM-LABEL: t6:
; ARM-NOT: mov
; ARM: cmp r0, #0
; ARM: movne r0, #1
-; THUMB2: t6:
+; THUMB2-LABEL: t6:
; THUMB2-NOT: mov
; THUMB2: cmp r0, #0
; THUMB2: it ne
; RUN: llc < %s -mattr=+neon,+thumb2 -mtriple=thumbv7-apple-darwin | FileCheck %s --check-prefix=CHECK-NEON
define i32 @f1(i32 %a.s) {
-;CHECK: f1:
+;CHECK-LABEL: f1:
;CHECK: moveq
entry:
%tmp = icmp eq i32 %a.s, 4
}
define i32 @f2(i32 %a.s) {
-;CHECK: f2:
+;CHECK-LABEL: f2:
;CHECK: movgt
entry:
%tmp = icmp sgt i32 %a.s, 4
}
define i32 @f3(i32 %a.s, i32 %b.s) {
-;CHECK: f3:
+;CHECK-LABEL: f3:
;CHECK: movlt
entry:
%tmp = icmp slt i32 %a.s, %b.s
}
define i32 @f4(i32 %a.s, i32 %b.s) {
-;CHECK: f4:
+;CHECK-LABEL: f4:
;CHECK: movle
entry:
%tmp = icmp sle i32 %a.s, %b.s
}
define i32 @f5(i32 %a.u, i32 %b.u) {
-;CHECK: f5:
+;CHECK-LABEL: f5:
;CHECK: movls
entry:
%tmp = icmp ule i32 %a.u, %b.u
}
define i32 @f6(i32 %a.u, i32 %b.u) {
-;CHECK: f6:
+;CHECK-LABEL: f6:
;CHECK: movhi
entry:
%tmp = icmp ugt i32 %a.u, %b.u
}
define double @f7(double %a, double %b) {
-;CHECK: f7:
+;CHECK-LABEL: f7:
;CHECK: movlt
;CHECK: movlt
-;CHECK-VFP: f7:
+;CHECK-VFP-LABEL: f7:
;CHECK-VFP: vmovmi
%tmp = fcmp olt double %a, 1.234e+00
%tmp1 = select i1 %tmp, double -1.000e+00, double %b
; Glue values can only have a single use, but the following test exposed a
; case where a SELECT was lowered with 2 uses of a comparison, causing the
; scheduler to assert.
-; CHECK-VFP: f9:
+; CHECK-VFP-LABEL: f9:
declare i8* @objc_msgSend(i8*, i8*, ...)
define void @f9() optsize {
; rdar://8662825
define i32 @t1(i32 %a, i32 %b, i32 %c) nounwind {
-; ARM: t1:
+; ARM-LABEL: t1:
; ARM: suble r1, r1, #-2147483647
; ARM: mov r0, r1
-; T2: t1:
+; T2-LABEL: t1:
; T2: mvn r0, #-2147483648
; T2: addle r1, r0
; T2: mov r0, r1
}
define i32 @t2(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t2:
+; ARM-LABEL: t2:
; ARM: suble r1, r1, #10
; ARM: mov r0, r1
-; T2: t2:
+; T2-LABEL: t2:
; T2: suble r1, #10
; T2: mov r0, r1
%tmp1 = icmp sgt i32 %c, 10
}
define i32 @t3(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
-; ARM: t3:
+; ARM-LABEL: t3:
; ARM: andge r3, r3, r2
; ARM: mov r0, r3
-; T2: t3:
+; T2-LABEL: t3:
; T2: andge r3, r2
; T2: mov r0, r3
%cond = icmp slt i32 %a, %b
}
define i32 @t4(i32 %a, i32 %b, i32 %x, i32 %y) nounwind {
-; ARM: t4:
+; ARM-LABEL: t4:
; ARM: orrge r3, r3, r2
; ARM: mov r0, r3
-; T2: t4:
+; T2-LABEL: t4:
; T2: orrge r3, r2
; T2: mov r0, r3
%cond = icmp slt i32 %a, %b
define i32 @t5(i32 %a, i32 %b, i32 %c) nounwind {
entry:
-; ARM: t5:
+; ARM-LABEL: t5:
; ARM-NOT: moveq
; ARM: orreq r2, r2, #1
-; T2: t5:
+; T2-LABEL: t5:
; T2-NOT: moveq
; T2: orreq r2, r2, #1
%tmp1 = icmp eq i32 %a, %b
}
define i32 @t6(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t6:
+; ARM-LABEL: t6:
; ARM-NOT: movge
; ARM: eorlt r3, r3, r2
-; T2: t6:
+; T2-LABEL: t6:
; T2-NOT: movge
; T2: eorlt r3, r2
%cond = icmp slt i32 %a, %b
define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind {
entry:
-; ARM: t7:
+; ARM-LABEL: t7:
; ARM-NOT: lsleq
; ARM: andeq r2, r2, r2, lsl #1
-; T2: t7:
+; T2-LABEL: t7:
; T2-NOT: lsleq.w
; T2: andeq.w r2, r2, r2, lsl #1
%tmp1 = shl i32 %c, 1
; Fold ORRri into movcc.
define i32 @t8(i32 %a, i32 %b) nounwind {
-; ARM: t8:
+; ARM-LABEL: t8:
; ARM: cmp r0, r1
; ARM: orrge r0, r1, #1
-; T2: t8:
+; T2-LABEL: t8:
; T2: cmp r0, r1
; T2: orrge r0, r1, #1
%x = or i32 %b, 1
; Fold ANDrr into movcc.
define i32 @t9(i32 %a, i32 %b, i32 %c) nounwind {
-; ARM: t9:
+; ARM-LABEL: t9:
; ARM: cmp r0, r1
; ARM: andge r0, r1, r2
-; T2: t9:
+; T2-LABEL: t9:
; T2: cmp r0, r1
; T2: andge.w r0, r1, r2
%x = and i32 %b, %c
; Fold EORrs into movcc.
define i32 @t10(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; ARM: t10:
+; ARM-LABEL: t10:
; ARM: cmp r0, r1
; ARM: eorge r0, r1, r2, lsl #7
-; T2: t10:
+; T2-LABEL: t10:
; T2: cmp r0, r1
; T2: eorge.w r0, r1, r2, lsl #7
%s = shl i32 %c, 7
; Fold ORRri into movcc, reversing the condition.
define i32 @t11(i32 %a, i32 %b) nounwind {
-; ARM: t11:
+; ARM-LABEL: t11:
; ARM: cmp r0, r1
; ARM: orrlt r0, r1, #1
-; T2: t11:
+; T2-LABEL: t11:
; T2: cmp r0, r1
; T2: orrlt r0, r1, #1
%x = or i32 %b, 1
; Fold ADDri12 into movcc
define i32 @t12(i32 %a, i32 %b) nounwind {
-; ARM: t12:
+; ARM-LABEL: t12:
; ARM: cmp r0, r1
; ARM: addge r0, r1,
-; T2: t12:
+; T2-LABEL: t12:
; T2: cmp r0, r1
; T2: addwge r0, r1, #3000
%x = add i32 %b, 3000
declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
define void @aaa(%quuz* %this, i8* %block) {
-; CHECK: aaa:
+; CHECK-LABEL: aaa:
; CHECK: bic {{.*}}, #15
; CHECK: vst1.64 {{.*}}sp:128
; CHECK: vld1.64 {{.*}}sp:128
define i32 @f() nounwind ssp {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: ldr
; CHECK: str
; CHECK-NOT:bne
; Generate a loop for large struct byval
define i32 @g() nounwind ssp {
entry:
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: ldr
; CHECK: sub
; CHECK: str
; Generate a loop using NEON instructions
define i32 @h() nounwind ssp {
entry:
-; CHECK: h:
+; CHECK-LABEL: h:
; CHECK: vld1
; CHECK: sub
; CHECK: vst1
define i32 @f(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, %b
define i32 @g(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp slt i32 %a, %b
define i32 @h(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: h:
+; CHECK-LABEL: h:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, 3
; rdar://11725965
define i32 @i(i32 %a, i32 %b) nounwind readnone ssp {
entry:
-; CHECK: i:
+; CHECK-LABEL: i:
; CHECK: subs
; CHECK-NOT: cmp
%cmp = icmp ult i32 %a, %b
; a swapped sub.
define i32 @j(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: j:
+; CHECK-LABEL: j:
; CHECK: sub
; CHECK: cmp
%cmp = icmp eq i32 %b, %a
; We should be able to tail-duplicate the basic block containing the indirectbr
; into all of its predecessors.
-; CHECK: fn:
+; CHECK-LABEL: fn:
; CHECK: mov pc
; CHECK: mov pc
; CHECK: mov pc
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.
-; CHECK: tail_duplicate_me:
+; CHECK-LABEL: tail_duplicate_me:
; CHECK: qux
; CHECK: movw r{{[0-9]+}}, :lower16:_GHJK
; CHECK: movt r{{[0-9]+}}, :upper16:_GHJK
; rdar://10674430
define void @sharedidx(i8* nocapture %a, i8* nocapture %b, i8* nocapture %c, i32 %s, i32 %len) nounwind ssp {
entry:
-; CHECK: sharedidx:
+; CHECK-LABEL: sharedidx:
%cmp8 = icmp eq i32 %len, 0
br i1 %cmp8, label %for.end, label %for.body
ret i32* @external_gd
; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
- ; CHECK-NONPIC: f1:
+ ; CHECK-NONPIC-LABEL: f1:
; CHECK-NONPIC: external_gd(gottpoff)
- ; CHECK-PIC: f1:
+ ; CHECK-PIC-LABEL: f1:
; CHECK-PIC: external_gd(tlsgd)
}
; Non-PIC code can use local exec, PIC code can use local dynamic,
; but that is not implemented, so falls back to general dynamic.
- ; CHECK-NONPIC: f2:
+ ; CHECK-NONPIC-LABEL: f2:
; CHECK-NONPIC: internal_gd(tpoff)
- ; CHECK-PIC: f2:
+ ; CHECK-PIC-LABEL: f2:
; CHECK-PIC: internal_gd(tlsgd)
}
; Non-PIC code can use initial exec, PIC should use local dynamic,
; but that is not implemented, so falls back to general dynamic.
- ; CHECK-NONPIC: f3:
+ ; CHECK-NONPIC-LABEL: f3:
; CHECK-NONPIC: external_ld(gottpoff)
- ; CHECK-PIC: f3:
+ ; CHECK-PIC-LABEL: f3:
; CHECK-PIC: external_ld(tlsgd)
}
; Non-PIC code can use local exec, PIC code can use local dynamic,
; but that is not implemented, so it falls back to general dynamic.
- ; CHECK-NONPIC: f4:
+ ; CHECK-NONPIC-LABEL: f4:
; CHECK-NONPIC: internal_ld(tpoff)
- ; CHECK-PIC: f4:
+ ; CHECK-PIC-LABEL: f4:
; CHECK-PIC: internal_ld(tlsgd)
}
ret i32* @external_ie
; Non-PIC and PIC code will use initial exec as specified.
- ; CHECK-NONPIC: f5:
+ ; CHECK-NONPIC-LABEL: f5:
; CHECK-NONPIC: external_ie(gottpoff)
- ; CHECK-PIC: f5:
+ ; CHECK-PIC-LABEL: f5:
; CHECK-PIC: external_ie(gottpoff)
}
ret i32* @internal_ie
; Non-PIC code can use local exec, PIC code use initial exec as specified.
- ; CHECK-NONPIC: f6:
+ ; CHECK-NONPIC-LABEL: f6:
; CHECK-NONPIC: internal_ie(tpoff)
- ; CHECK-PIC: f6:
+ ; CHECK-PIC-LABEL: f6:
; CHECK-PIC: internal_ie(gottpoff)
}
ret i32* @external_le
; Non-PIC and PIC code will use local exec as specified.
- ; CHECK-NONPIC: f7:
+ ; CHECK-NONPIC-LABEL: f7:
; CHECK-NONPIC: external_le(tpoff)
- ; CHECK-PIC: f7:
+ ; CHECK-PIC-LABEL: f7:
; CHECK-PIC: external_le(tpoff)
}
ret i32* @internal_le
; Non-PIC and PIC code will use local exec as specified.
- ; CHECK-NONPIC: f8:
+ ; CHECK-NONPIC-LABEL: f8:
; CHECK-NONPIC: internal_le(tpoff)
- ; CHECK-PIC: f8:
+ ; CHECK-PIC-LABEL: f8:
; CHECK-PIC: internal_le(tpoff)
}
@i = external thread_local global i32 ; <i32*> [#uses=2]
define i32 @f() {
-; CHECK-NONPIC: f:
+; CHECK-NONPIC-LABEL: f:
; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
; CHECK-NONPIC: i(gottpoff)
-; CHECK-PIC: f:
+; CHECK-PIC-LABEL: f:
; CHECK-PIC: __tls_get_addr
entry:
%tmp1 = load i32* @i ; <i32> [#uses=1]
}
define i32* @g() {
-; CHECK-NONPIC: g:
+; CHECK-NONPIC-LABEL: g:
; CHECK-NONPIC: ldr {{r.}}, [pc, {{r.}}]
; CHECK-NONPIC: i(gottpoff)
-; CHECK-PIC: g:
+; CHECK-PIC-LABEL: g:
; CHECK-PIC: __tls_get_addr
entry:
ret i32* @i
define void @t() nounwind {
entry:
-; INSTR: t:
+; INSTR-LABEL: t:
; INSTR: trap
-; FUNC: t:
+; FUNC-LABEL: t:
; FUNC: bl __trap
; ENCODING-NACL: f0 de fe e7
define void @t2() nounwind {
entry:
-; INSTR: t2:
+; INSTR-LABEL: t2:
; INSTR: trap
-; FUNC: t2:
+; FUNC-LABEL: t2:
; FUNC: bl __trap
; ENCODING-NACL: f0 de fe e7
define void @PR13378() nounwind {
; This was orriginally a crasher trying to schedule the instructions.
-; CHECK: PR13378:
+; CHECK-LABEL: PR13378:
; CHECK: vld1.32
; CHECK-NEXT: vst1.32
; CHECK-NEXT: vst1.32
define void @t(i8* nocapture %a, i8* nocapture %b) nounwind {
entry:
-; EXPANDED: t:
+; EXPANDED-LABEL: t:
; EXPANDED: ldrb [[R2:r[0-9]+]]
; EXPANDED: ldrb [[R3:r[0-9]+]]
; EXPANDED: ldrb [[R12:r[0-9]+]]
; EXPANDED: strb [[R3]]
; EXPANDED: strb [[R2]]
-; UNALIGNED: t:
+; UNALIGNED-LABEL: t:
; UNALIGNED: ldr r1
; UNALIGNED: str r1
define void @hword(double* %a, double* %b) nounwind {
entry:
-; EXPANDED: hword:
+; EXPANDED-LABEL: hword:
; EXPANDED-NOT: vld1
; EXPANDED: ldrh
; EXPANDED-NOT: str1
; EXPANDED: strh
-; UNALIGNED: hword:
+; UNALIGNED-LABEL: hword:
; UNALIGNED: vld1.16
; UNALIGNED: vst1.16
%tmp = load double* %a, align 2
define void @byte(double* %a, double* %b) nounwind {
entry:
-; EXPANDED: byte:
+; EXPANDED-LABEL: byte:
; EXPANDED-NOT: vld1
; EXPANDED: ldrb
; EXPANDED-NOT: str1
; EXPANDED: strb
-; UNALIGNED: byte:
+; UNALIGNED-LABEL: byte:
; UNALIGNED: vld1.8
; UNALIGNED: vst1.8
%tmp = load double* %a, align 1
define void @byte_word_ops(i32* %a, i32* %b) nounwind {
entry:
-; EXPANDED: byte_word_ops:
+; EXPANDED-LABEL: byte_word_ops:
; EXPANDED: ldrb
; EXPANDED: strb
-; UNALIGNED: byte_word_ops:
+; UNALIGNED-LABEL: byte_word_ops:
; UNALIGNED-NOT: ldrb
; UNALIGNED: ldr
; UNALIGNED-NOT: strb
;SIZE = 64
;TYPE = <8 x i8>
define void @v64_v8i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_1:
+;CHECK-LABEL: v64_v8i8_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <4 x i16>
define void @v64_v4i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_1:
+;CHECK-LABEL: v64_v4i16_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <2 x i32>
define void @v64_v2i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_1:
+;CHECK-LABEL: v64_v2i32_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <2 x float>
define void @v64_v2f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_1:
+;CHECK-LABEL: v64_v2f32_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <16 x i8>
define void @v128_v16i8_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_1:
+;CHECK-LABEL: v128_v16i8_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <8 x i16>
define void @v128_v8i16_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_1:
+;CHECK-LABEL: v128_v8i16_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <4 x i32>
define void @v128_v4i32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_1:
+;CHECK-LABEL: v128_v4i32_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <2 x i64>
define void @v128_v2i64_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_1:
+;CHECK-LABEL: v128_v2i64_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <4 x float>
define void @v128_v4f32_1(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_1:
+;CHECK-LABEL: v128_v4f32_1:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <8 x i8>
define void @v64_v8i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_2:
+;CHECK-LABEL: v64_v8i8_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <4 x i16>
define void @v64_v4i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_2:
+;CHECK-LABEL: v64_v4i16_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <2 x i32>
define void @v64_v2i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_2:
+;CHECK-LABEL: v64_v2i32_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <2 x float>
define void @v64_v2f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_2:
+;CHECK-LABEL: v64_v2f32_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <16 x i8>
define void @v128_v16i8_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_2:
+;CHECK-LABEL: v128_v16i8_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <8 x i16>
define void @v128_v8i16_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_2:
+;CHECK-LABEL: v128_v8i16_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <4 x i32>
define void @v128_v4i32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_2:
+;CHECK-LABEL: v128_v4i32_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <2 x i64>
define void @v128_v2i64_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_2:
+;CHECK-LABEL: v128_v2i64_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <4 x float>
define void @v128_v4f32_2(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_2:
+;CHECK-LABEL: v128_v4f32_2:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <8 x i8>
define void @v64_v8i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v8i8_4:
+;CHECK-LABEL: v64_v8i8_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <4 x i16>
define void @v64_v4i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v4i16_4:
+;CHECK-LABEL: v64_v4i16_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <2 x i32>
define void @v64_v2i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2i32_4:
+;CHECK-LABEL: v64_v2i32_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 64
;TYPE = <2 x float>
define void @v64_v2f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v64_v2f32_4:
+;CHECK-LABEL: v64_v2f32_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <16 x i8>
define void @v128_v16i8_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v16i8_4:
+;CHECK-LABEL: v128_v16i8_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <8 x i16>
define void @v128_v8i16_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v8i16_4:
+;CHECK-LABEL: v128_v8i16_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <4 x i32>
define void @v128_v4i32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4i32_4:
+;CHECK-LABEL: v128_v4i32_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <2 x i64>
define void @v128_v2i64_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v2i64_4:
+;CHECK-LABEL: v128_v2i64_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
;SIZE = 128
;TYPE = <4 x float>
define void @v128_v4f32_4(i8* noalias nocapture %out, i8* noalias nocapture %in) nounwind {
-;CHECK: v128_v4f32_4:
+;CHECK-LABEL: v128_v4f32_4:
entry:
%po = getelementptr i8* %out, i32 0
%pi = getelementptr i8* %in, i32 0
define i32 @t(i32* %a) nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: ldr r0, [r0]
; CHECK: bx lr
%0 = sext i16 undef to i32
ret void
}
-; CHECK: calls_unwind_init:
+; CHECK-LABEL: calls_unwind_init:
; CHECK: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; CHECK: vpush {d8, d9, d10, d11, d12, d13, d14, d15}
; CHECK: vpop {d8, d9, d10, d11, d12, d13, d14, d15}
; PR15611. Check that we don't crash when constant folding v1i32 types.
-; CHECK: foo:
+; CHECK-LABEL: foo:
define void @foo(i32 %arg) {
bb:
%tmp = insertelement <4 x i32> undef, i32 %arg, i32 0
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabas8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabas8:
+;CHECK-LABEL: vabas8:
;CHECK: vaba.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vabas16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabas16:
+;CHECK-LABEL: vabas16:
;CHECK: vaba.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vabas32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabas32:
+;CHECK-LABEL: vabas32:
;CHECK: vaba.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vabau8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabau8:
+;CHECK-LABEL: vabau8:
;CHECK: vaba.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vabau16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabau16:
+;CHECK-LABEL: vabau16:
;CHECK: vaba.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vabau32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabau32:
+;CHECK-LABEL: vabau32:
;CHECK: vaba.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <16 x i8> @vabaQs8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: vabaQs8:
+;CHECK-LABEL: vabaQs8:
;CHECK: vaba.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vabaQs16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vabaQs16:
+;CHECK-LABEL: vabaQs16:
;CHECK: vaba.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vabaQs32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vabaQs32:
+;CHECK-LABEL: vabaQs32:
;CHECK: vaba.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vabaQu8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: vabaQu8:
+;CHECK-LABEL: vabaQu8:
;CHECK: vaba.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vabaQu16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vabaQu16:
+;CHECK-LABEL: vabaQu16:
;CHECK: vaba.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vabaQu32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vabaQu32:
+;CHECK-LABEL: vabaQu32:
;CHECK: vaba.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
declare <4 x i32> @llvm.arm.neon.vabdu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <8 x i16> @vabals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabals8:
+;CHECK-LABEL: vabals8:
;CHECK: vabal.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vabals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabals16:
+;CHECK-LABEL: vabals16:
;CHECK: vabal.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vabals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabals32:
+;CHECK-LABEL: vabals32:
;CHECK: vabal.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vabalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vabalu8:
+;CHECK-LABEL: vabalu8:
;CHECK: vabal.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vabalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vabalu16:
+;CHECK-LABEL: vabalu16:
;CHECK: vabal.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vabalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vabalu32:
+;CHECK-LABEL: vabalu32:
;CHECK: vabal.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabds8:
+;CHECK-LABEL: vabds8:
;CHECK: vabd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vabds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabds16:
+;CHECK-LABEL: vabds16:
;CHECK: vabd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vabds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabds32:
+;CHECK-LABEL: vabds32:
;CHECK: vabd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vabdu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdu8:
+;CHECK-LABEL: vabdu8:
;CHECK: vabd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vabdu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdu16:
+;CHECK-LABEL: vabdu16:
;CHECK: vabd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vabdu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdu32:
+;CHECK-LABEL: vabdu32:
;CHECK: vabd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vabdf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vabdf32:
+;CHECK-LABEL: vabdf32:
;CHECK: vabd.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vabdQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vabdQs8:
+;CHECK-LABEL: vabdQs8:
;CHECK: vabd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vabdQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vabdQs16:
+;CHECK-LABEL: vabdQs16:
;CHECK: vabd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vabdQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vabdQs32:
+;CHECK-LABEL: vabdQs32:
;CHECK: vabd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vabdQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vabdQu8:
+;CHECK-LABEL: vabdQu8:
;CHECK: vabd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vabdQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vabdQu16:
+;CHECK-LABEL: vabdQu16:
;CHECK: vabd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vabdQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vabdQu32:
+;CHECK-LABEL: vabdQu32:
;CHECK: vabd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x float> @vabdQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vabdQf32:
+;CHECK-LABEL: vabdQf32:
;CHECK: vabd.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
declare <4 x float> @llvm.arm.neon.vabds.v4f32(<4 x float>, <4 x float>) nounwind readnone
define <8 x i16> @vabdls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdls8:
+;CHECK-LABEL: vabdls8:
;CHECK: vabdl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vabdls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdls16:
+;CHECK-LABEL: vabdls16:
;CHECK: vabdl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vabdls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdls32:
+;CHECK-LABEL: vabdls32:
;CHECK: vabdl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vabdlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vabdlu8:
+;CHECK-LABEL: vabdlu8:
;CHECK: vabdl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vabdlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vabdlu16:
+;CHECK-LABEL: vabdlu16:
;CHECK: vabdl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vabdlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vabdlu32:
+;CHECK-LABEL: vabdlu32:
;CHECK: vabdl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vabss8(<8 x i8>* %A) nounwind {
-;CHECK: vabss8:
+;CHECK-LABEL: vabss8:
;CHECK: vabs.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vabs.v8i8(<8 x i8> %tmp1)
}
define <4 x i16> @vabss16(<4 x i16>* %A) nounwind {
-;CHECK: vabss16:
+;CHECK-LABEL: vabss16:
;CHECK: vabs.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vabs.v4i16(<4 x i16> %tmp1)
}
define <2 x i32> @vabss32(<2 x i32>* %A) nounwind {
-;CHECK: vabss32:
+;CHECK-LABEL: vabss32:
;CHECK: vabs.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vabs.v2i32(<2 x i32> %tmp1)
}
define <2 x float> @vabsf32(<2 x float>* %A) nounwind {
-;CHECK: vabsf32:
+;CHECK-LABEL: vabsf32:
;CHECK: vabs.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vabs.v2f32(<2 x float> %tmp1)
}
define <16 x i8> @vabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vabsQs8:
+;CHECK-LABEL: vabsQs8:
;CHECK: vabs.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vabs.v16i8(<16 x i8> %tmp1)
}
define <8 x i16> @vabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vabsQs16:
+;CHECK-LABEL: vabsQs16:
;CHECK: vabs.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vabs.v8i16(<8 x i16> %tmp1)
}
define <4 x i32> @vabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vabsQs32:
+;CHECK-LABEL: vabsQs32:
;CHECK: vabs.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vabs.v4i32(<4 x i32> %tmp1)
}
define <4 x float> @vabsQf32(<4 x float>* %A) nounwind {
-;CHECK: vabsQf32:
+;CHECK-LABEL: vabsQf32:
;CHECK: vabs.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float> %tmp1)
declare <4 x float> @llvm.arm.neon.vabs.v4f32(<4 x float>) nounwind readnone
define <8 x i8> @vqabss8(<8 x i8>* %A) nounwind {
-;CHECK: vqabss8:
+;CHECK-LABEL: vqabss8:
;CHECK: vqabs.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqabs.v8i8(<8 x i8> %tmp1)
}
define <4 x i16> @vqabss16(<4 x i16>* %A) nounwind {
-;CHECK: vqabss16:
+;CHECK-LABEL: vqabss16:
;CHECK: vqabs.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqabs.v4i16(<4 x i16> %tmp1)
}
define <2 x i32> @vqabss32(<2 x i32>* %A) nounwind {
-;CHECK: vqabss32:
+;CHECK-LABEL: vqabss32:
;CHECK: vqabs.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqabs.v2i32(<2 x i32> %tmp1)
}
define <16 x i8> @vqabsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vqabsQs8:
+;CHECK-LABEL: vqabsQs8:
;CHECK: vqabs.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqabs.v16i8(<16 x i8> %tmp1)
}
define <8 x i16> @vqabsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vqabsQs16:
+;CHECK-LABEL: vqabsQs16:
;CHECK: vqabs.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqabs.v8i16(<8 x i16> %tmp1)
}
define <4 x i32> @vqabsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vqabsQs32:
+;CHECK-LABEL: vqabsQs32:
;CHECK: vqabs.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqabs.v4i32(<4 x i32> %tmp1)
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddi8:
+;CHECK-LABEL: vaddi8:
;CHECK: vadd.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddi16:
+;CHECK-LABEL: vaddi16:
;CHECK: vadd.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddi32:
+;CHECK-LABEL: vaddi32:
;CHECK: vadd.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vaddi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vaddi64:
+;CHECK-LABEL: vaddi64:
;CHECK: vadd.i64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <2 x float> @vaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vaddf32:
+;CHECK-LABEL: vaddf32:
;CHECK: vadd.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vaddQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vaddQi8:
+;CHECK-LABEL: vaddQi8:
;CHECK: vadd.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vaddQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vaddQi16:
+;CHECK-LABEL: vaddQi16:
;CHECK: vadd.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vaddQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vaddQi32:
+;CHECK-LABEL: vaddQi32:
;CHECK: vadd.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vaddQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vaddQi64:
+;CHECK-LABEL: vaddQi64:
;CHECK: vadd.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <4 x float> @vaddQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vaddQf32:
+;CHECK-LABEL: vaddQf32:
;CHECK: vadd.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
}
define <8 x i8> @vaddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vaddhni16:
+;CHECK-LABEL: vaddhni16:
;CHECK: vaddhn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i16> @vaddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vaddhni32:
+;CHECK-LABEL: vaddhni32:
;CHECK: vaddhn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i32> @vaddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vaddhni64:
+;CHECK-LABEL: vaddhni64:
;CHECK: vaddhn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
declare <2 x i32> @llvm.arm.neon.vaddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vraddhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vraddhni16:
+;CHECK-LABEL: vraddhni16:
;CHECK: vraddhn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i16> @vraddhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vraddhni32:
+;CHECK-LABEL: vraddhni32:
;CHECK: vraddhn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i32> @vraddhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vraddhni64:
+;CHECK-LABEL: vraddhni64:
;CHECK: vraddhn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
declare <2 x i32> @llvm.arm.neon.vraddhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i16> @vaddls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddls8:
+;CHECK-LABEL: vaddls8:
;CHECK: vaddl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vaddls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddls16:
+;CHECK-LABEL: vaddls16:
;CHECK: vaddl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vaddls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddls32:
+;CHECK-LABEL: vaddls32:
;CHECK: vaddl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vaddlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddlu8:
+;CHECK-LABEL: vaddlu8:
;CHECK: vaddl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vaddlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddlu16:
+;CHECK-LABEL: vaddlu16:
;CHECK: vaddl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vaddlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddlu32:
+;CHECK-LABEL: vaddlu32:
;CHECK: vaddl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vaddws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddws8:
+;CHECK-LABEL: vaddws8:
;CHECK: vaddw.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vaddws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddws16:
+;CHECK-LABEL: vaddws16:
;CHECK: vaddw.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vaddws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddws32:
+;CHECK-LABEL: vaddws32:
;CHECK: vaddw.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vaddwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vaddwu8:
+;CHECK-LABEL: vaddwu8:
;CHECK: vaddw.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vaddwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vaddwu16:
+;CHECK-LABEL: vaddwu16:
;CHECK: vaddw.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vaddwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vaddwu32:
+;CHECK-LABEL: vaddwu32:
;CHECK: vaddw.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon -mcpu=cortex-a8 | FileCheck %s
define <8 x i8> @v_andi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_andi8:
+;CHECK-LABEL: v_andi8:
;CHECK: vand
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @v_andi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_andi16:
+;CHECK-LABEL: v_andi16:
;CHECK: vand
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @v_andi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_andi32:
+;CHECK-LABEL: v_andi32:
;CHECK: vand
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @v_andi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_andi64:
+;CHECK-LABEL: v_andi64:
;CHECK: vand
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @v_andQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_andQi8:
+;CHECK-LABEL: v_andQi8:
;CHECK: vand
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @v_andQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_andQi16:
+;CHECK-LABEL: v_andQi16:
;CHECK: vand
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @v_andQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_andQi32:
+;CHECK-LABEL: v_andQi32:
;CHECK: vand
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @v_andQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_andQi64:
+;CHECK-LABEL: v_andQi64:
;CHECK: vand
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @v_bici8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_bici8:
+;CHECK-LABEL: v_bici8:
;CHECK: vbic
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @v_bici16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_bici16:
+;CHECK-LABEL: v_bici16:
;CHECK: vbic
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @v_bici32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_bici32:
+;CHECK-LABEL: v_bici32:
;CHECK: vbic
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @v_bici64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_bici64:
+;CHECK-LABEL: v_bici64:
;CHECK: vbic
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @v_bicQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_bicQi8:
+;CHECK-LABEL: v_bicQi8:
;CHECK: vbic
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @v_bicQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_bicQi16:
+;CHECK-LABEL: v_bicQi16:
;CHECK: vbic
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @v_bicQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_bicQi32:
+;CHECK-LABEL: v_bicQi32:
;CHECK: vbic
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @v_bicQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_bicQi64:
+;CHECK-LABEL: v_bicQi64:
;CHECK: vbic
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @v_eori8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_eori8:
+;CHECK-LABEL: v_eori8:
;CHECK: veor
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @v_eori16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_eori16:
+;CHECK-LABEL: v_eori16:
;CHECK: veor
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @v_eori32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_eori32:
+;CHECK-LABEL: v_eori32:
;CHECK: veor
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @v_eori64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_eori64:
+;CHECK-LABEL: v_eori64:
;CHECK: veor
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @v_eorQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_eorQi8:
+;CHECK-LABEL: v_eorQi8:
;CHECK: veor
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @v_eorQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_eorQi16:
+;CHECK-LABEL: v_eorQi16:
;CHECK: veor
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @v_eorQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_eorQi32:
+;CHECK-LABEL: v_eorQi32:
;CHECK: veor
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @v_eorQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_eorQi64:
+;CHECK-LABEL: v_eorQi64:
;CHECK: veor
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @v_mvni8(<8 x i8>* %A) nounwind {
-;CHECK: v_mvni8:
+;CHECK-LABEL: v_mvni8:
;CHECK: vmvn
%tmp1 = load <8 x i8>* %A
%tmp2 = xor <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
}
define <4 x i16> @v_mvni16(<4 x i16>* %A) nounwind {
-;CHECK: v_mvni16:
+;CHECK-LABEL: v_mvni16:
;CHECK: vmvn
%tmp1 = load <4 x i16>* %A
%tmp2 = xor <4 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1 >
}
define <2 x i32> @v_mvni32(<2 x i32>* %A) nounwind {
-;CHECK: v_mvni32:
+;CHECK-LABEL: v_mvni32:
;CHECK: vmvn
%tmp1 = load <2 x i32>* %A
%tmp2 = xor <2 x i32> %tmp1, < i32 -1, i32 -1 >
}
define <1 x i64> @v_mvni64(<1 x i64>* %A) nounwind {
-;CHECK: v_mvni64:
+;CHECK-LABEL: v_mvni64:
;CHECK: vmvn
%tmp1 = load <1 x i64>* %A
%tmp2 = xor <1 x i64> %tmp1, < i64 -1 >
}
define <16 x i8> @v_mvnQi8(<16 x i8>* %A) nounwind {
-;CHECK: v_mvnQi8:
+;CHECK-LABEL: v_mvnQi8:
;CHECK: vmvn
%tmp1 = load <16 x i8>* %A
%tmp2 = xor <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
}
define <8 x i16> @v_mvnQi16(<8 x i16>* %A) nounwind {
-;CHECK: v_mvnQi16:
+;CHECK-LABEL: v_mvnQi16:
;CHECK: vmvn
%tmp1 = load <8 x i16>* %A
%tmp2 = xor <8 x i16> %tmp1, < i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1 >
}
define <4 x i32> @v_mvnQi32(<4 x i32>* %A) nounwind {
-;CHECK: v_mvnQi32:
+;CHECK-LABEL: v_mvnQi32:
;CHECK: vmvn
%tmp1 = load <4 x i32>* %A
%tmp2 = xor <4 x i32> %tmp1, < i32 -1, i32 -1, i32 -1, i32 -1 >
}
define <2 x i64> @v_mvnQi64(<2 x i64>* %A) nounwind {
-;CHECK: v_mvnQi64:
+;CHECK-LABEL: v_mvnQi64:
;CHECK: vmvn
%tmp1 = load <2 x i64>* %A
%tmp2 = xor <2 x i64> %tmp1, < i64 -1, i64 -1 >
}
define <8 x i8> @v_orri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_orri8:
+;CHECK-LABEL: v_orri8:
;CHECK: vorr
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @v_orri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_orri16:
+;CHECK-LABEL: v_orri16:
;CHECK: vorr
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @v_orri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_orri32:
+;CHECK-LABEL: v_orri32:
;CHECK: vorr
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @v_orri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_orri64:
+;CHECK-LABEL: v_orri64:
;CHECK: vorr
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @v_orrQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_orrQi8:
+;CHECK-LABEL: v_orrQi8:
;CHECK: vorr
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @v_orrQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_orrQi16:
+;CHECK-LABEL: v_orrQi16:
;CHECK: vorr
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @v_orrQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_orrQi32:
+;CHECK-LABEL: v_orrQi32:
;CHECK: vorr
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @v_orrQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_orrQi64:
+;CHECK-LABEL: v_orrQi64:
;CHECK: vorr
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @v_orni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: v_orni8:
+;CHECK-LABEL: v_orni8:
;CHECK: vorn
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @v_orni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: v_orni16:
+;CHECK-LABEL: v_orni16:
;CHECK: vorn
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @v_orni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: v_orni32:
+;CHECK-LABEL: v_orni32:
;CHECK: vorn
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @v_orni64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: v_orni64:
+;CHECK-LABEL: v_orni64:
;CHECK: vorn
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @v_ornQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: v_ornQi8:
+;CHECK-LABEL: v_ornQi8:
;CHECK: vorn
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @v_ornQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: v_ornQi16:
+;CHECK-LABEL: v_ornQi16:
;CHECK: vorn
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @v_ornQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: v_ornQi32:
+;CHECK-LABEL: v_ornQi32:
;CHECK: vorn
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @v_ornQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: v_ornQi64:
+;CHECK-LABEL: v_ornQi64:
;CHECK: vorn
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @vtsti8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtsti8:
+;CHECK-LABEL: vtsti8:
;CHECK: vtst.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vtsti16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtsti16:
+;CHECK-LABEL: vtsti16:
;CHECK: vtst.16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vtsti32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtsti32:
+;CHECK-LABEL: vtsti32:
;CHECK: vtst.32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <16 x i8> @vtstQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtstQi8:
+;CHECK-LABEL: vtstQi8:
;CHECK: vtst.8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vtstQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtstQi16:
+;CHECK-LABEL: vtstQi16:
;CHECK: vtst.16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vtstQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtstQi32:
+;CHECK-LABEL: vtstQi32:
;CHECK: vtst.32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
-; CHECK: v_orrimm:
+; CHECK-LABEL: v_orrimm:
; CHECK-NOT: vmov
; CHECK-NOT: vmvn
; CHECK: vorr
}
define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
-; CHECK: v_bicimm:
+; CHECK-LABEL: v_bicimm:
; CHECK-NOT: vmov
; CHECK-NOT: vmvn
; CHECK: vbic
}
define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
-; CHECK: v_bicimmQ:
+; CHECK-LABEL: v_bicimmQ:
; CHECK-NOT: vmov
; CHECK-NOT: vmvn
; CHECK: vbic
; RUN: llc < %s -mtriple=arm-apple-ios -mattr=+neon | FileCheck %s
define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
+;CHECK-LABEL: v_bsli8:
;CHECK: vldr
;CHECK: vldr
;CHECK: vbsl
}
define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
+;CHECK-LABEL: v_bsli16:
;CHECK: vldr
;CHECK: vldr
;CHECK: vbsl
}
define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
+;CHECK-LABEL: v_bsli32:
;CHECK: vldr
;CHECK: vldr
;CHECK: vbsl
}
define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
+;CHECK-LABEL: v_bsli64:
;CHECK: vldr
;CHECK: vldr
;CHECK: vldr
}
define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
+;CHECK-LABEL: v_bslQi8:
;CHECK: vld1.32
;CHECK: vld1.32
;CHECK: vbsl
}
define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
+;CHECK-LABEL: v_bslQi16:
;CHECK: vld1.32
;CHECK: vld1.32
;CHECK: vbsl
}
define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
+;CHECK-LABEL: v_bslQi32:
;CHECK: vld1.32
;CHECK: vld1.32
;CHECK: vbsl
}
define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
+;CHECK-LABEL: v_bslQi64:
;CHECK: vld1.32
;CHECK: vld1.32
;CHECK: vld1.64
; rdar://12471808
define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: v_bsli8:
+;CHECK-LABEL: v_bsli8:
;CHECK: vbsl
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: v_bsli16:
+;CHECK-LABEL: v_bsli16:
;CHECK: vbsl
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: v_bsli32:
+;CHECK-LABEL: v_bsli32:
;CHECK: vbsl
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
-;CHECK: v_bsli64:
+;CHECK-LABEL: v_bsli64:
;CHECK: vbsl
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @v_bslQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8>* %C) nounwind {
-;CHECK: v_bslQi8:
+;CHECK-LABEL: v_bslQi8:
;CHECK: vbsl
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @v_bslQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: v_bslQi16:
+;CHECK-LABEL: v_bslQi16:
;CHECK: vbsl
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @v_bslQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: v_bslQi32:
+;CHECK-LABEL: v_bslQi32:
;CHECK: vbsl
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @v_bslQi64(<2 x i64>* %A, <2 x i64>* %B, <2 x i64>* %C) nounwind {
-;CHECK: v_bslQi64:
+;CHECK-LABEL: v_bslQi64:
;CHECK: vbsl
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @f1(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind readnone optsize ssp {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: vbsl
%vbsl.i = tail call <8 x i8> @llvm.arm.neon.vbsl.v8i8(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) nounwind
ret <8 x i8> %vbsl.i
}
define <4 x i16> @f2(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind readnone optsize ssp {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: vbsl
%vbsl3.i = tail call <4 x i16> @llvm.arm.neon.vbsl.v4i16(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c) nounwind
ret <4 x i16> %vbsl3.i
}
define <2 x i32> @f3(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind readnone optsize ssp {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: vbsl
%vbsl3.i = tail call <2 x i32> @llvm.arm.neon.vbsl.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) nounwind
ret <2 x i32> %vbsl3.i
}
define <2 x float> @f4(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind readnone optsize ssp {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: vbsl
%vbsl4.i = tail call <2 x float> @llvm.arm.neon.vbsl.v2f32(<2 x float> %a, <2 x float> %b, <2 x float> %c) nounwind
ret <2 x float> %vbsl4.i
}
define <16 x i8> @g1(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind readnone optsize ssp {
-; CHECK: g1:
+; CHECK-LABEL: g1:
; CHECK: vbsl
%vbsl.i = tail call <16 x i8> @llvm.arm.neon.vbsl.v16i8(<16 x i8> %a, <16 x i8> %b, <16 x i8> %c) nounwind
ret <16 x i8> %vbsl.i
}
define <8 x i16> @g2(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind readnone optsize ssp {
-; CHECK: g2:
+; CHECK-LABEL: g2:
; CHECK: vbsl
%vbsl3.i = tail call <8 x i16> @llvm.arm.neon.vbsl.v8i16(<8 x i16> %a, <8 x i16> %b, <8 x i16> %c) nounwind
ret <8 x i16> %vbsl3.i
}
define <4 x i32> @g3(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind readnone optsize ssp {
-; CHECK: g3:
+; CHECK-LABEL: g3:
; CHECK: vbsl
%vbsl3.i = tail call <4 x i32> @llvm.arm.neon.vbsl.v4i32(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) nounwind
ret <4 x i32> %vbsl3.i
}
define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind readnone optsize ssp {
-; CHECK: g4:
+; CHECK-LABEL: g4:
; CHECK: vbsl
%vbsl4.i = tail call <4 x float> @llvm.arm.neon.vbsl.v4f32(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
ret <4 x float> %vbsl4.i
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vceqi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vceqi8:
+;CHECK-LABEL: vceqi8:
;CHECK: vceq.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vceqi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vceqi16:
+;CHECK-LABEL: vceqi16:
;CHECK: vceq.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vceqi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vceqi32:
+;CHECK-LABEL: vceqi32:
;CHECK: vceq.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x i32> @vceqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vceqf32:
+;CHECK-LABEL: vceqf32:
;CHECK: vceq.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vceqQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vceqQi8:
+;CHECK-LABEL: vceqQi8:
;CHECK: vceq.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vceqQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vceqQi16:
+;CHECK-LABEL: vceqQi16:
;CHECK: vceq.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vceqQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vceqQi32:
+;CHECK-LABEL: vceqQi32:
;CHECK: vceq.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x i32> @vceqQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vceqQf32:
+;CHECK-LABEL: vceqQf32:
;CHECK: vceq.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
}
define <8 x i8> @vceqi8Z(<8 x i8>* %A) nounwind {
-;CHECK: vceqi8Z:
+;CHECK-LABEL: vceqi8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vceq.i8
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vcges8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcges8:
+;CHECK-LABEL: vcges8:
;CHECK: vcge.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vcges16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcges16:
+;CHECK-LABEL: vcges16:
;CHECK: vcge.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vcges32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcges32:
+;CHECK-LABEL: vcges32:
;CHECK: vcge.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vcgeu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgeu8:
+;CHECK-LABEL: vcgeu8:
;CHECK: vcge.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vcgeu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgeu16:
+;CHECK-LABEL: vcgeu16:
;CHECK: vcge.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vcgeu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgeu32:
+;CHECK-LABEL: vcgeu32:
;CHECK: vcge.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x i32> @vcgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcgef32:
+;CHECK-LABEL: vcgef32:
;CHECK: vcge.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vcgeQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgeQs8:
+;CHECK-LABEL: vcgeQs8:
;CHECK: vcge.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vcgeQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgeQs16:
+;CHECK-LABEL: vcgeQs16:
;CHECK: vcge.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vcgeQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgeQs32:
+;CHECK-LABEL: vcgeQs32:
;CHECK: vcge.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vcgeQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgeQu8:
+;CHECK-LABEL: vcgeQu8:
;CHECK: vcge.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vcgeQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgeQu16:
+;CHECK-LABEL: vcgeQu16:
;CHECK: vcge.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vcgeQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgeQu32:
+;CHECK-LABEL: vcgeQu32:
;CHECK: vcge.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x i32> @vcgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgeQf32:
+;CHECK-LABEL: vcgeQf32:
;CHECK: vcge.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
}
define <2 x i32> @vacgef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vacgef32:
+;CHECK-LABEL: vacgef32:
;CHECK: vacge.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <4 x i32> @vacgeQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vacgeQf32:
+;CHECK-LABEL: vacgeQf32:
;CHECK: vacge.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
declare <4 x i32> @llvm.arm.neon.vacgeq(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @vcgei8Z(<8 x i8>* %A) nounwind {
-;CHECK: vcgei8Z:
+;CHECK-LABEL: vcgei8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vcge.s8
}
define <8 x i8> @vclei8Z(<8 x i8>* %A) nounwind {
-;CHECK: vclei8Z:
+;CHECK-LABEL: vclei8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vcle.s8
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
define <8 x i8> @vcgts8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgts8:
+;CHECK-LABEL: vcgts8:
;CHECK: vcgt.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vcgts16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgts16:
+;CHECK-LABEL: vcgts16:
;CHECK: vcgt.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vcgts32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgts32:
+;CHECK-LABEL: vcgts32:
;CHECK: vcgt.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vcgtu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcgtu8:
+;CHECK-LABEL: vcgtu8:
;CHECK: vcgt.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vcgtu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcgtu16:
+;CHECK-LABEL: vcgtu16:
;CHECK: vcgt.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vcgtu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcgtu32:
+;CHECK-LABEL: vcgtu32:
;CHECK: vcgt.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x i32> @vcgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcgtf32:
+;CHECK-LABEL: vcgtf32:
;CHECK: vcgt.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vcgtQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgtQs8:
+;CHECK-LABEL: vcgtQs8:
;CHECK: vcgt.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vcgtQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgtQs16:
+;CHECK-LABEL: vcgtQs16:
;CHECK: vcgt.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vcgtQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgtQs32:
+;CHECK-LABEL: vcgtQs32:
;CHECK: vcgt.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vcgtQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcgtQu8:
+;CHECK-LABEL: vcgtQu8:
;CHECK: vcgt.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vcgtQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcgtQu16:
+;CHECK-LABEL: vcgtQu16:
;CHECK: vcgt.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vcgtQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcgtQu32:
+;CHECK-LABEL: vcgtQu32:
;CHECK: vcgt.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x i32> @vcgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgtQf32:
+;CHECK-LABEL: vcgtQf32:
;CHECK: vcgt.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
}
define <2 x i32> @vacgtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vacgtf32:
+;CHECK-LABEL: vacgtf32:
;CHECK: vacgt.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <4 x i32> @vacgtQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vacgtQf32:
+;CHECK-LABEL: vacgtQf32:
;CHECK: vacgt.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
; rdar://7923010
define <4 x i32> @vcgt_zext(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vcgt_zext:
+;CHECK-LABEL: vcgt_zext:
;CHECK: vmov.i32 [[Q0:q[0-9]+]], #0x1
;CHECK: vcgt.f32 [[Q1:q[0-9]+]]
;CHECK: vand [[Q2:q[0-9]+]], [[Q1]], [[Q0]]
declare <4 x i32> @llvm.arm.neon.vacgtq(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @vcgti8Z(<8 x i8>* %A) nounwind {
-;CHECK: vcgti8Z:
+;CHECK-LABEL: vcgti8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vcgt.s8
}
define <8 x i8> @vclti8Z(<8 x i8>* %A) nounwind {
-;CHECK: vclti8Z:
+;CHECK-LABEL: vclti8Z:
;CHECK-NOT: vmov
;CHECK-NOT: vmvn
;CHECK: vclt.s8
; NB: this tests vcnt, vclz, and vcls
define <8 x i8> @vcnt8(<8 x i8>* %A) nounwind {
-;CHECK: vcnt8:
+;CHECK-LABEL: vcnt8:
;CHECK: vcnt.8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctpop.v8i8(<8 x i8> %tmp1)
}
define <16 x i8> @vcntQ8(<16 x i8>* %A) nounwind {
-;CHECK: vcntQ8:
+;CHECK-LABEL: vcntQ8:
;CHECK: vcnt.8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %tmp1)
declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8>) nounwind readnone
define <8 x i8> @vclz8(<8 x i8>* %A) nounwind {
-;CHECK: vclz8:
+;CHECK-LABEL: vclz8:
;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %tmp1, i1 0)
}
define <4 x i16> @vclz16(<4 x i16>* %A) nounwind {
-;CHECK: vclz16:
+;CHECK-LABEL: vclz16:
;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.ctlz.v4i16(<4 x i16> %tmp1, i1 0)
}
define <2 x i32> @vclz32(<2 x i32>* %A) nounwind {
-;CHECK: vclz32:
+;CHECK-LABEL: vclz32:
;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %tmp1, i1 0)
}
define <16 x i8> @vclzQ8(<16 x i8>* %A) nounwind {
-;CHECK: vclzQ8:
+;CHECK-LABEL: vclzQ8:
;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %tmp1, i1 0)
}
define <8 x i16> @vclzQ16(<8 x i16>* %A) nounwind {
-;CHECK: vclzQ16:
+;CHECK-LABEL: vclzQ16:
;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %tmp1, i1 0)
}
define <4 x i32> @vclzQ32(<4 x i32>* %A) nounwind {
-;CHECK: vclzQ32:
+;CHECK-LABEL: vclzQ32:
;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %tmp1, i1 0)
declare <4 x i32> @llvm.ctlz.v4i32(<4 x i32>, i1) nounwind readnone
define <8 x i8> @vclss8(<8 x i8>* %A) nounwind {
-;CHECK: vclss8:
+;CHECK-LABEL: vclss8:
;CHECK: vcls.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
}
define <4 x i16> @vclss16(<4 x i16>* %A) nounwind {
-;CHECK: vclss16:
+;CHECK-LABEL: vclss16:
;CHECK: vcls.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
}
define <2 x i32> @vclss32(<2 x i32>* %A) nounwind {
-;CHECK: vclss32:
+;CHECK-LABEL: vclss32:
;CHECK: vcls.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
}
define <16 x i8> @vclsQs8(<16 x i8>* %A) nounwind {
-;CHECK: vclsQs8:
+;CHECK-LABEL: vclsQs8:
;CHECK: vcls.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
}
define <8 x i16> @vclsQs16(<8 x i16>* %A) nounwind {
-;CHECK: vclsQs16:
+;CHECK-LABEL: vclsQs16:
;CHECK: vcls.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
}
define <4 x i32> @vclsQs32(<4 x i32>* %A) nounwind {
-;CHECK: vclsQs32:
+;CHECK-LABEL: vclsQs32:
;CHECK: vcls.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcls.v4i32(<4 x i32> %tmp1)
; RUN: opt < %s -cost-model -analyze -mtriple=thumbv7-apple-ios6.0.0 -march=arm -mcpu=cortex-a8 | FileCheck %s --check-prefix=COST
%T0_5 = type <8 x i8>
%T1_5 = type <8 x i32>
-; CHECK: func_cvt5:
+; CHECK-LABEL: func_cvt5:
define void @func_cvt5(%T0_5* %loadaddr, %T1_5* %storeaddr) {
; CHECK: vmovl.s8
; CHECK: vmovl.s16
;; is improved the cost needs to change.
%TA0_5 = type <8 x i8>
%TA1_5 = type <8 x i32>
-; CHECK: func_cvt1:
+; CHECK-LABEL: func_cvt1:
define void @func_cvt1(%TA0_5* %loadaddr, %TA1_5* %storeaddr) {
; CHECK: vmovl.u8
; CHECK: vmovl.u16
%T0_51 = type <8 x i32>
%T1_51 = type <8 x i8>
-; CHECK: func_cvt51:
+; CHECK-LABEL: func_cvt51:
define void @func_cvt51(%T0_51* %loadaddr, %T1_51* %storeaddr) {
; CHECK: vmovn.i32
; CHECK: vmovn.i32
%TT0_5 = type <16 x i8>
%TT1_5 = type <16 x i32>
-; CHECK: func_cvt52:
+; CHECK-LABEL: func_cvt52:
define void @func_cvt52(%TT0_5* %loadaddr, %TT1_5* %storeaddr) {
; CHECK: vmovl.s16
; CHECK: vmovl.s16
;; is improved the cost needs to change.
%TTA0_5 = type <16 x i8>
%TTA1_5 = type <16 x i32>
-; CHECK: func_cvt12:
+; CHECK-LABEL: func_cvt12:
define void @func_cvt12(%TTA0_5* %loadaddr, %TTA1_5* %storeaddr) {
; CHECK: vmovl.u16
; CHECK: vmovl.u16
%TT0_51 = type <16 x i32>
%TT1_51 = type <16 x i8>
-; CHECK: func_cvt512:
+; CHECK-LABEL: func_cvt512:
define void @func_cvt512(%TT0_51* %loadaddr, %TT1_51* %storeaddr) {
; CHECK: vmovn.i32
; CHECK: vmovn.i32
ret void
}
-; CHECK: sext_v4i16_v4i64:
+; CHECK-LABEL: sext_v4i16_v4i64:
define void @sext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
; CHECK: vmovl.s32
; CHECK: vmovl.s32
ret void
}
-; CHECK: zext_v4i16_v4i64:
+; CHECK-LABEL: zext_v4i16_v4i64:
define void @zext_v4i16_v4i64(<4 x i16>* %loadaddr, <4 x i64>* %storeaddr) {
; CHECK: vmovl.u32
; CHECK: vmovl.u32
ret void
}
-; CHECK: sext_v8i16_v8i64:
+; CHECK-LABEL: sext_v8i16_v8i64:
define void @sext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
; CHECK: vmovl.s32
; CHECK: vmovl.s32
ret void
}
-; CHECK: zext_v8i16_v8i64:
+; CHECK-LABEL: zext_v8i16_v8i64:
define void @zext_v8i16_v8i64(<8 x i16>* %loadaddr, <8 x i64>* %storeaddr) {
; CHECK: vmovl.u32
; CHECK: vmovl.u32
; RUN: llc < %s -march=arm -mattr=+neon,+fp16 | FileCheck %s
define <2 x i32> @vcvt_f32tos32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_f32tos32:
+;CHECK-LABEL: vcvt_f32tos32:
;CHECK: vcvt.s32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = fptosi <2 x float> %tmp1 to <2 x i32>
}
define <2 x i32> @vcvt_f32tou32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_f32tou32:
+;CHECK-LABEL: vcvt_f32tou32:
;CHECK: vcvt.u32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = fptoui <2 x float> %tmp1 to <2 x i32>
}
define <2 x float> @vcvt_s32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_s32tof32:
+;CHECK-LABEL: vcvt_s32tof32:
;CHECK: vcvt.f32.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = sitofp <2 x i32> %tmp1 to <2 x float>
}
define <2 x float> @vcvt_u32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_u32tof32:
+;CHECK-LABEL: vcvt_u32tof32:
;CHECK: vcvt.f32.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = uitofp <2 x i32> %tmp1 to <2 x float>
}
define <4 x i32> @vcvtQ_f32tos32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_f32tos32:
+;CHECK-LABEL: vcvtQ_f32tos32:
;CHECK: vcvt.s32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = fptosi <4 x float> %tmp1 to <4 x i32>
}
define <4 x i32> @vcvtQ_f32tou32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_f32tou32:
+;CHECK-LABEL: vcvtQ_f32tou32:
;CHECK: vcvt.u32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = fptoui <4 x float> %tmp1 to <4 x i32>
}
define <4 x float> @vcvtQ_s32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_s32tof32:
+;CHECK-LABEL: vcvtQ_s32tof32:
;CHECK: vcvt.f32.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = sitofp <4 x i32> %tmp1 to <4 x float>
}
define <4 x float> @vcvtQ_u32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_u32tof32:
+;CHECK-LABEL: vcvtQ_u32tof32:
;CHECK: vcvt.f32.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = uitofp <4 x i32> %tmp1 to <4 x float>
}
define <2 x i32> @vcvt_n_f32tos32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_n_f32tos32:
+;CHECK-LABEL: vcvt_n_f32tos32:
;CHECK: vcvt.s32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32(<2 x float> %tmp1, i32 1)
}
define <2 x i32> @vcvt_n_f32tou32(<2 x float>* %A) nounwind {
-;CHECK: vcvt_n_f32tou32:
+;CHECK-LABEL: vcvt_n_f32tou32:
;CHECK: vcvt.u32.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32(<2 x float> %tmp1, i32 1)
}
define <2 x float> @vcvt_n_s32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_n_s32tof32:
+;CHECK-LABEL: vcvt_n_s32tof32:
;CHECK: vcvt.f32.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
}
define <2 x float> @vcvt_n_u32tof32(<2 x i32>* %A) nounwind {
-;CHECK: vcvt_n_u32tof32:
+;CHECK-LABEL: vcvt_n_u32tof32:
;CHECK: vcvt.f32.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %tmp1, i32 1)
declare <2 x float> @llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
define <4 x i32> @vcvtQ_n_f32tos32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_n_f32tos32:
+;CHECK-LABEL: vcvtQ_n_f32tos32:
;CHECK: vcvt.s32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32(<4 x float> %tmp1, i32 1)
}
define <4 x i32> @vcvtQ_n_f32tou32(<4 x float>* %A) nounwind {
-;CHECK: vcvtQ_n_f32tou32:
+;CHECK-LABEL: vcvtQ_n_f32tou32:
;CHECK: vcvt.u32.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32(<4 x float> %tmp1, i32 1)
}
define <4 x float> @vcvtQ_n_s32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_n_s32tof32:
+;CHECK-LABEL: vcvtQ_n_s32tof32:
;CHECK: vcvt.f32.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
}
define <4 x float> @vcvtQ_n_u32tof32(<4 x i32>* %A) nounwind {
-;CHECK: vcvtQ_n_u32tof32:
+;CHECK-LABEL: vcvtQ_n_u32tof32:
;CHECK: vcvt.f32.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %tmp1, i32 1)
declare <4 x float> @llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
define <4 x float> @vcvt_f16tof32(<4 x i16>* %A) nounwind {
-;CHECK: vcvt_f16tof32:
+;CHECK-LABEL: vcvt_f16tof32:
;CHECK: vcvt.f32.f16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vcvthf2fp(<4 x i16> %tmp1)
}
define <4 x i16> @vcvt_f32tof16(<4 x float>* %A) nounwind {
-;CHECK: vcvt_f32tof16:
+;CHECK-LABEL: vcvt_f32tof16:
;CHECK: vcvt.f16.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vcvtfp2hf(<4 x float> %tmp1)
define <4 x i16> @fix_float_to_i16(<4 x float> %in) {
-; CHECK: fix_float_to_i16:
+; CHECK-LABEL: fix_float_to_i16:
; CHECK: vcvt.u32.f32 [[TMP:q[0-9]+]], {{q[0-9]+}}, #1
; CHECK: vmovn.i32 {{d[0-9]+}}, [[TMP]]
}
define <2 x i64> @fix_float_to_i64(<2 x float> %in) {
-; CHECK: fix_float_to_i64:
+; CHECK-LABEL: fix_float_to_i64:
; CHECK: bl
; CHECK: bl
}
define <4 x i16> @fix_double_to_i16(<4 x double> %in) {
-; CHECK: fix_double_to_i16:
+; CHECK-LABEL: fix_double_to_i16:
; CHECK: vcvt.s32.f64
; CHECK: vcvt.s32.f64
}
define <2 x i64> @fix_double_to_i64(<2 x double> %in) {
-; CHECK: fix_double_to_i64:
+; CHECK-LABEL: fix_double_to_i64:
; CHECK: bl
; CHECK: bl
%scale = fmul <2 x double> %in, <double 2.0, double 2.0>
declare void @foo_float32x4_t(<4 x float>)
define <4 x float> @fix_unsigned_i16_to_float(<4 x i16> %in) {
-; CHECK: fix_unsigned_i16_to_float:
+; CHECK-LABEL: fix_unsigned_i16_to_float:
; CHECK: vmovl.u16 [[TMP:q[0-9]+]], {{d[0-9]+}}
; CHECK: vcvt.f32.u32 {{q[0-9]+}}, [[TMP]], #1
}
define <4 x float> @fix_signed_i16_to_float(<4 x i16> %in) {
-; CHECK: fix_signed_i16_to_float:
+; CHECK-LABEL: fix_signed_i16_to_float:
; CHECK: vmovl.s16 [[TMP:q[0-9]+]], {{d[0-9]+}}
; CHECK: vcvt.f32.s32 {{q[0-9]+}}, [[TMP]], #1
}
define <2 x float> @fix_i64_to_float(<2 x i64> %in) {
-; CHECK: fix_i64_to_float:
+; CHECK-LABEL: fix_i64_to_float:
; CHECK: bl
; CHECK: bl
}
define <2 x double> @fix_i64_to_double(<2 x i64> %in) {
-; CHECK: fix_i64_to_double:
+; CHECK-LABEL: fix_i64_to_double:
; CHECK: bl
; CHECK: bl
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_dup8(i8 %A) nounwind {
-;CHECK: v_dup8:
+;CHECK-LABEL: v_dup8:
;CHECK: vdup.8
%tmp1 = insertelement <8 x i8> zeroinitializer, i8 %A, i32 0
%tmp2 = insertelement <8 x i8> %tmp1, i8 %A, i32 1
}
define <4 x i16> @v_dup16(i16 %A) nounwind {
-;CHECK: v_dup16:
+;CHECK-LABEL: v_dup16:
;CHECK: vdup.16
%tmp1 = insertelement <4 x i16> zeroinitializer, i16 %A, i32 0
%tmp2 = insertelement <4 x i16> %tmp1, i16 %A, i32 1
}
define <2 x i32> @v_dup32(i32 %A) nounwind {
-;CHECK: v_dup32:
+;CHECK-LABEL: v_dup32:
;CHECK: vdup.32
%tmp1 = insertelement <2 x i32> zeroinitializer, i32 %A, i32 0
%tmp2 = insertelement <2 x i32> %tmp1, i32 %A, i32 1
}
define <2 x float> @v_dupfloat(float %A) nounwind {
-;CHECK: v_dupfloat:
+;CHECK-LABEL: v_dupfloat:
;CHECK: vdup.32
%tmp1 = insertelement <2 x float> zeroinitializer, float %A, i32 0
%tmp2 = insertelement <2 x float> %tmp1, float %A, i32 1
}
define <16 x i8> @v_dupQ8(i8 %A) nounwind {
-;CHECK: v_dupQ8:
+;CHECK-LABEL: v_dupQ8:
;CHECK: vdup.8
%tmp1 = insertelement <16 x i8> zeroinitializer, i8 %A, i32 0
%tmp2 = insertelement <16 x i8> %tmp1, i8 %A, i32 1
}
define <8 x i16> @v_dupQ16(i16 %A) nounwind {
-;CHECK: v_dupQ16:
+;CHECK-LABEL: v_dupQ16:
;CHECK: vdup.16
%tmp1 = insertelement <8 x i16> zeroinitializer, i16 %A, i32 0
%tmp2 = insertelement <8 x i16> %tmp1, i16 %A, i32 1
}
define <4 x i32> @v_dupQ32(i32 %A) nounwind {
-;CHECK: v_dupQ32:
+;CHECK-LABEL: v_dupQ32:
;CHECK: vdup.32
%tmp1 = insertelement <4 x i32> zeroinitializer, i32 %A, i32 0
%tmp2 = insertelement <4 x i32> %tmp1, i32 %A, i32 1
}
define <4 x float> @v_dupQfloat(float %A) nounwind {
-;CHECK: v_dupQfloat:
+;CHECK-LABEL: v_dupQfloat:
;CHECK: vdup.32
%tmp1 = insertelement <4 x float> zeroinitializer, float %A, i32 0
%tmp2 = insertelement <4 x float> %tmp1, float %A, i32 1
; Check to make sure it works with shuffles, too.
define <8 x i8> @v_shuffledup8(i8 %A) nounwind {
-;CHECK: v_shuffledup8:
+;CHECK-LABEL: v_shuffledup8:
;CHECK: vdup.8
%tmp1 = insertelement <8 x i8> undef, i8 %A, i32 0
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> zeroinitializer
}
define <4 x i16> @v_shuffledup16(i16 %A) nounwind {
-;CHECK: v_shuffledup16:
+;CHECK-LABEL: v_shuffledup16:
;CHECK: vdup.16
%tmp1 = insertelement <4 x i16> undef, i16 %A, i32 0
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> zeroinitializer
}
define <2 x i32> @v_shuffledup32(i32 %A) nounwind {
-;CHECK: v_shuffledup32:
+;CHECK-LABEL: v_shuffledup32:
;CHECK: vdup.32
%tmp1 = insertelement <2 x i32> undef, i32 %A, i32 0
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> zeroinitializer
}
define <2 x float> @v_shuffledupfloat(float %A) nounwind {
-;CHECK: v_shuffledupfloat:
+;CHECK-LABEL: v_shuffledupfloat:
;CHECK: vdup.32
%tmp1 = insertelement <2 x float> undef, float %A, i32 0
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> zeroinitializer
}
define <16 x i8> @v_shuffledupQ8(i8 %A) nounwind {
-;CHECK: v_shuffledupQ8:
+;CHECK-LABEL: v_shuffledupQ8:
;CHECK: vdup.8
%tmp1 = insertelement <16 x i8> undef, i8 %A, i32 0
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> zeroinitializer
}
define <8 x i16> @v_shuffledupQ16(i16 %A) nounwind {
-;CHECK: v_shuffledupQ16:
+;CHECK-LABEL: v_shuffledupQ16:
;CHECK: vdup.16
%tmp1 = insertelement <8 x i16> undef, i16 %A, i32 0
%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> zeroinitializer
}
define <4 x i32> @v_shuffledupQ32(i32 %A) nounwind {
-;CHECK: v_shuffledupQ32:
+;CHECK-LABEL: v_shuffledupQ32:
;CHECK: vdup.32
%tmp1 = insertelement <4 x i32> undef, i32 %A, i32 0
%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> zeroinitializer
}
define <4 x float> @v_shuffledupQfloat(float %A) nounwind {
-;CHECK: v_shuffledupQfloat:
+;CHECK-LABEL: v_shuffledupQfloat:
;CHECK: vdup.32
%tmp1 = insertelement <4 x float> undef, float %A, i32 0
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> zeroinitializer
}
define <8 x i8> @vduplane8(<8 x i8>* %A) nounwind {
-;CHECK: vduplane8:
+;CHECK-LABEL: vduplane8:
;CHECK: vdup.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
}
define <4 x i16> @vduplane16(<4 x i16>* %A) nounwind {
-;CHECK: vduplane16:
+;CHECK-LABEL: vduplane16:
;CHECK: vdup.16
%tmp1 = load <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
}
define <2 x i32> @vduplane32(<2 x i32>* %A) nounwind {
-;CHECK: vduplane32:
+;CHECK-LABEL: vduplane32:
;CHECK: vdup.32
%tmp1 = load <2 x i32>* %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> < i32 1, i32 1 >
}
define <2 x float> @vduplanefloat(<2 x float>* %A) nounwind {
-;CHECK: vduplanefloat:
+;CHECK-LABEL: vduplanefloat:
;CHECK: vdup.32
%tmp1 = load <2 x float>* %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> < i32 1, i32 1 >
}
define <16 x i8> @vduplaneQ8(<8 x i8>* %A) nounwind {
-;CHECK: vduplaneQ8:
+;CHECK-LABEL: vduplaneQ8:
;CHECK: vdup.8
%tmp1 = load <8 x i8>* %A
%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <16 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
}
define <8 x i16> @vduplaneQ16(<4 x i16>* %A) nounwind {
-;CHECK: vduplaneQ16:
+;CHECK-LABEL: vduplaneQ16:
;CHECK: vdup.16
%tmp1 = load <4 x i16>* %A
%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <8 x i32> < i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1 >
}
define <4 x i32> @vduplaneQ32(<2 x i32>* %A) nounwind {
-;CHECK: vduplaneQ32:
+;CHECK-LABEL: vduplaneQ32:
;CHECK: vdup.32
%tmp1 = load <2 x i32>* %A
%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
}
define <4 x float> @vduplaneQfloat(<2 x float>* %A) nounwind {
-;CHECK: vduplaneQfloat:
+;CHECK-LABEL: vduplaneQfloat:
;CHECK: vdup.32
%tmp1 = load <2 x float>* %A
%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <4 x i32> < i32 1, i32 1, i32 1, i32 1 >
}
; Radar 7373643
-;CHECK: redundantVdup:
+;CHECK-LABEL: redundantVdup:
;CHECK: vmov.i8
;CHECK-NOT: vdup.8
;CHECK: vstr
}
define <2 x float> @check_f32(<4 x float> %v) nounwind {
-;CHECK: check_f32:
+;CHECK-LABEL: check_f32:
;CHECK: vdup.32 {{.*}}, d{{..}}[1]
%x = extractelement <4 x float> %v, i32 3
%1 = insertelement <2 x float> undef, float %x, i32 0
}
define <2 x i32> @check_i32(<4 x i32> %v) nounwind {
-;CHECK: check_i32:
+;CHECK-LABEL: check_i32:
;CHECK: vdup.32 {{.*}}, d{{..}}[1]
%x = extractelement <4 x i32> %v, i32 3
%1 = insertelement <2 x i32> undef, i32 %x, i32 0
}
define <4 x i16> @check_i16(<8 x i16> %v) nounwind {
-;CHECK: check_i16:
+;CHECK-LABEL: check_i16:
;CHECK: vdup.16 {{.*}}, d{{..}}[3]
%x = extractelement <8 x i16> %v, i32 3
%1 = insertelement <4 x i16> undef, i16 %x, i32 0
}
define <8 x i8> @check_i8(<16 x i8> %v) nounwind {
-;CHECK: check_i8:
+;CHECK-LABEL: check_i8:
;CHECK: vdup.8 {{.*}}, d{{..}}[3]
%x = extractelement <16 x i8> %v, i32 3
%1 = insertelement <8 x i8> undef, i8 %x, i32 0
; RUN: llc -mtriple armv7 %s -o - | FileCheck %s
-; CHECK: f:
+; CHECK-LABEL: f:
define float @f(<4 x i16>* nocapture %in) {
; CHECK: vldr
; CHECK: vmovl.u16
ret float %7
}
-; CHECK: g:
+; CHECK-LABEL: g:
define float @g(<4 x i8>* nocapture %in) {
; Note: vld1 here is reasonably important. Mixing VFP and NEON
; instructions is bad on some cores
ret float %7
}
-; CHECK: h:
+; CHECK-LABEL: h:
define <4 x i8> @h(<4 x float> %v) {
; CHECK: vcvt.{{[us]}}32.f32
; CHECK: vmovn.i32
ret <4 x i8> %1
}
-; CHECK: i:
+; CHECK-LABEL: i:
define <4 x i8> @i(<4 x i8>* %x) {
; Note: vld1 here is reasonably important. Mixing VFP and NEON
; instructions is bad on some cores
%2 = sdiv <4 x i8> zeroinitializer, %1
ret <4 x i8> %2
}
-; CHECK: j:
+; CHECK-LABEL: j:
define <4 x i32> @j(<4 x i8>* %in) nounwind {
; CHECK: vld1
; CHECK: vmovl.u8
; une is implemented with VCEQ/VMVN
define <2 x i32> @vcunef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcunef32:
+;CHECK-LABEL: vcunef32:
;CHECK: vceq.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
; olt is implemented with VCGT
define <2 x i32> @vcoltf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcoltf32:
+;CHECK-LABEL: vcoltf32:
;CHECK: vcgt.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
; ole is implemented with VCGE
define <2 x i32> @vcolef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcolef32:
+;CHECK-LABEL: vcolef32:
;CHECK: vcge.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
; uge is implemented with VCGT/VMVN
define <2 x i32> @vcugef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcugef32:
+;CHECK-LABEL: vcugef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
; ule is implemented with VCGT/VMVN
define <2 x i32> @vculef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vculef32:
+;CHECK-LABEL: vculef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
; ugt is implemented with VCGE/VMVN
define <2 x i32> @vcugtf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcugtf32:
+;CHECK-LABEL: vcugtf32:
;CHECK: vcge.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
; ult is implemented with VCGE/VMVN
define <2 x i32> @vcultf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcultf32:
+;CHECK-LABEL: vcultf32:
;CHECK: vcge.f32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x float>* %A
; ueq is implemented with VCGT/VCGT/VORR/VMVN
define <2 x i32> @vcueqf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcueqf32:
+;CHECK-LABEL: vcueqf32:
;CHECK: vcgt.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
; one is implemented with VCGT/VCGT/VORR
define <2 x i32> @vconef32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vconef32:
+;CHECK-LABEL: vconef32:
;CHECK: vcgt.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
; uno is implemented with VCGT/VCGE/VORR/VMVN
define <2 x i32> @vcunof32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcunof32:
+;CHECK-LABEL: vcunof32:
;CHECK: vcge.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
; ord is implemented with VCGT/VCGE/VORR
define <2 x i32> @vcordf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vcordf32:
+;CHECK-LABEL: vcordf32:
;CHECK: vcge.f32
;CHECK-NEXT: vcgt.f32
;CHECK-NEXT: vorr
target triple = "thumbv7-elf"
define i32 @vget_lanes8(<8 x i8>* %A) nounwind {
-;CHECK: vget_lanes8:
+;CHECK-LABEL: vget_lanes8:
;CHECK: vmov.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 1
}
define i32 @vget_lanes16(<4 x i16>* %A) nounwind {
-;CHECK: vget_lanes16:
+;CHECK-LABEL: vget_lanes16:
;CHECK: vmov.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = extractelement <4 x i16> %tmp1, i32 1
}
define i32 @vget_laneu8(<8 x i8>* %A) nounwind {
-;CHECK: vget_laneu8:
+;CHECK-LABEL: vget_laneu8:
;CHECK: vmov.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = extractelement <8 x i8> %tmp1, i32 1
}
define i32 @vget_laneu16(<4 x i16>* %A) nounwind {
-;CHECK: vget_laneu16:
+;CHECK-LABEL: vget_laneu16:
;CHECK: vmov.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = extractelement <4 x i16> %tmp1, i32 1
; Do a vector add to keep the extraction from being done directly from memory.
define i32 @vget_lanei32(<2 x i32>* %A) nounwind {
-;CHECK: vget_lanei32:
+;CHECK-LABEL: vget_lanei32:
;CHECK: vmov.32
%tmp1 = load <2 x i32>* %A
%tmp2 = add <2 x i32> %tmp1, %tmp1
}
define i32 @vgetQ_lanes8(<16 x i8>* %A) nounwind {
-;CHECK: vgetQ_lanes8:
+;CHECK-LABEL: vgetQ_lanes8:
;CHECK: vmov.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = extractelement <16 x i8> %tmp1, i32 1
}
define i32 @vgetQ_lanes16(<8 x i16>* %A) nounwind {
-;CHECK: vgetQ_lanes16:
+;CHECK-LABEL: vgetQ_lanes16:
;CHECK: vmov.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = extractelement <8 x i16> %tmp1, i32 1
}
define i32 @vgetQ_laneu8(<16 x i8>* %A) nounwind {
-;CHECK: vgetQ_laneu8:
+;CHECK-LABEL: vgetQ_laneu8:
;CHECK: vmov.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = extractelement <16 x i8> %tmp1, i32 1
}
define i32 @vgetQ_laneu16(<8 x i16>* %A) nounwind {
-;CHECK: vgetQ_laneu16:
+;CHECK-LABEL: vgetQ_laneu16:
;CHECK: vmov.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = extractelement <8 x i16> %tmp1, i32 1
; Do a vector add to keep the extraction from being done directly from memory.
define i32 @vgetQ_lanei32(<4 x i32>* %A) nounwind {
-;CHECK: vgetQ_lanei32:
+;CHECK-LABEL: vgetQ_lanei32:
;CHECK: vmov.32
%tmp1 = load <4 x i32>* %A
%tmp2 = add <4 x i32> %tmp1, %tmp1
}
define <8 x i8> @vset_lane8(<8 x i8>* %A, i8 %B) nounwind {
-;CHECK: vset_lane8:
+;CHECK-LABEL: vset_lane8:
;CHECK: vmov.8
%tmp1 = load <8 x i8>* %A
%tmp2 = insertelement <8 x i8> %tmp1, i8 %B, i32 1
}
define <4 x i16> @vset_lane16(<4 x i16>* %A, i16 %B) nounwind {
-;CHECK: vset_lane16:
+;CHECK-LABEL: vset_lane16:
;CHECK: vmov.16
%tmp1 = load <4 x i16>* %A
%tmp2 = insertelement <4 x i16> %tmp1, i16 %B, i32 1
}
define <2 x i32> @vset_lane32(<2 x i32>* %A, i32 %B) nounwind {
-;CHECK: vset_lane32:
+;CHECK-LABEL: vset_lane32:
;CHECK: vmov.32
%tmp1 = load <2 x i32>* %A
%tmp2 = insertelement <2 x i32> %tmp1, i32 %B, i32 1
}
define <16 x i8> @vsetQ_lane8(<16 x i8>* %A, i8 %B) nounwind {
-;CHECK: vsetQ_lane8:
+;CHECK-LABEL: vsetQ_lane8:
;CHECK: vmov.8
%tmp1 = load <16 x i8>* %A
%tmp2 = insertelement <16 x i8> %tmp1, i8 %B, i32 1
}
define <8 x i16> @vsetQ_lane16(<8 x i16>* %A, i16 %B) nounwind {
-;CHECK: vsetQ_lane16:
+;CHECK-LABEL: vsetQ_lane16:
;CHECK: vmov.16
%tmp1 = load <8 x i16>* %A
%tmp2 = insertelement <8 x i16> %tmp1, i16 %B, i32 1
}
define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
-;CHECK: vsetQ_lane32:
+;CHECK-LABEL: vsetQ_lane32:
;CHECK: vmov.32 d{{.*}}[1], r1
%tmp1 = load <4 x i32>* %A
%tmp2 = insertelement <4 x i32> %tmp1, i32 %B, i32 1
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhadds8:
+;CHECK-LABEL: vhadds8:
;CHECK: vhadd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhadds16:
+;CHECK-LABEL: vhadds16:
;CHECK: vhadd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhadds32:
+;CHECK-LABEL: vhadds32:
;CHECK: vhadd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhaddu8:
+;CHECK-LABEL: vhaddu8:
;CHECK: vhadd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhaddu16:
+;CHECK-LABEL: vhaddu16:
;CHECK: vhadd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhaddu32:
+;CHECK-LABEL: vhaddu32:
;CHECK: vhadd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <16 x i8> @vhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhaddQs8:
+;CHECK-LABEL: vhaddQs8:
;CHECK: vhadd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhaddQs16:
+;CHECK-LABEL: vhaddQs16:
;CHECK: vhadd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhaddQs32:
+;CHECK-LABEL: vhaddQs32:
;CHECK: vhadd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhaddQu8:
+;CHECK-LABEL: vhaddQu8:
;CHECK: vhadd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhaddQu16:
+;CHECK-LABEL: vhaddQu16:
;CHECK: vhadd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhaddQu32:
+;CHECK-LABEL: vhaddQu32:
;CHECK: vhadd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
declare <4 x i32> @llvm.arm.neon.vhaddu.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <8 x i8> @vrhadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrhadds8:
+;CHECK-LABEL: vrhadds8:
;CHECK: vrhadd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vrhadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrhadds16:
+;CHECK-LABEL: vrhadds16:
;CHECK: vrhadd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vrhadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrhadds32:
+;CHECK-LABEL: vrhadds32:
;CHECK: vrhadd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vrhaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrhaddu8:
+;CHECK-LABEL: vrhaddu8:
;CHECK: vrhadd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vrhaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrhaddu16:
+;CHECK-LABEL: vrhaddu16:
;CHECK: vrhadd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vrhaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrhaddu32:
+;CHECK-LABEL: vrhaddu32:
;CHECK: vrhadd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <16 x i8> @vrhaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrhaddQs8:
+;CHECK-LABEL: vrhaddQs8:
;CHECK: vrhadd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vrhaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrhaddQs16:
+;CHECK-LABEL: vrhaddQs16:
;CHECK: vrhadd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vrhaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrhaddQs32:
+;CHECK-LABEL: vrhaddQs32:
;CHECK: vrhadd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vrhaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrhaddQu8:
+;CHECK-LABEL: vrhaddQu8:
;CHECK: vrhadd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vrhaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrhaddQu16:
+;CHECK-LABEL: vrhaddQu16:
;CHECK: vrhadd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vrhaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrhaddQu32:
+;CHECK-LABEL: vrhaddQu32:
;CHECK: vrhadd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vhsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhsubs8:
+;CHECK-LABEL: vhsubs8:
;CHECK: vhsub.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vhsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhsubs16:
+;CHECK-LABEL: vhsubs16:
;CHECK: vhsub.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vhsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhsubs32:
+;CHECK-LABEL: vhsubs32:
;CHECK: vhsub.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vhsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vhsubu8:
+;CHECK-LABEL: vhsubu8:
;CHECK: vhsub.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vhsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vhsubu16:
+;CHECK-LABEL: vhsubu16:
;CHECK: vhsub.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vhsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vhsubu32:
+;CHECK-LABEL: vhsubu32:
;CHECK: vhsub.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <16 x i8> @vhsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhsubQs8:
+;CHECK-LABEL: vhsubQs8:
;CHECK: vhsub.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vhsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhsubQs16:
+;CHECK-LABEL: vhsubQs16:
;CHECK: vhsub.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vhsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhsubQs32:
+;CHECK-LABEL: vhsubQs32:
;CHECK: vhsub.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vhsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vhsubQu8:
+;CHECK-LABEL: vhsubQu8:
;CHECK: vhsub.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vhsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vhsubQu16:
+;CHECK-LABEL: vhsubQu16:
;CHECK: vhsub.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vhsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vhsubQu32:
+;CHECK-LABEL: vhsubQu32:
;CHECK: vhsub.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
; the other operations.
define <8 x i8> @vcnei8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vcnei8:
+;CHECK-LABEL: vcnei8:
;CHECK: vceq.i8
;CHECK-NEXT: vmvn
%tmp1 = load <8 x i8>* %A
}
define <4 x i16> @vcnei16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcnei16:
+;CHECK-LABEL: vcnei16:
;CHECK: vceq.i16
;CHECK-NEXT: vmvn
%tmp1 = load <4 x i16>* %A
}
define <2 x i32> @vcnei32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vcnei32:
+;CHECK-LABEL: vcnei32:
;CHECK: vceq.i32
;CHECK-NEXT: vmvn
%tmp1 = load <2 x i32>* %A
}
define <16 x i8> @vcneQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcneQi8:
+;CHECK-LABEL: vcneQi8:
;CHECK: vceq.i8
;CHECK-NEXT: vmvn
%tmp1 = load <16 x i8>* %A
}
define <8 x i16> @vcneQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vcneQi16:
+;CHECK-LABEL: vcneQi16:
;CHECK: vceq.i16
;CHECK-NEXT: vmvn
%tmp1 = load <8 x i16>* %A
}
define <4 x i32> @vcneQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcneQi32:
+;CHECK-LABEL: vcneQi32:
;CHECK: vceq.i32
;CHECK-NEXT: vmvn
%tmp1 = load <4 x i32>* %A
}
define <16 x i8> @vcltQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vcltQs8:
+;CHECK-LABEL: vcltQs8:
;CHECK: vcgt.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <4 x i16> @vcles16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcles16:
+;CHECK-LABEL: vcles16:
;CHECK: vcge.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <4 x i16> @vcltu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vcltu16:
+;CHECK-LABEL: vcltu16:
;CHECK: vcgt.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <4 x i32> @vcleQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vcleQu32:
+;CHECK-LABEL: vcleQu32:
;CHECK: vcge.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
define <8 x i8> @vld1i8(i8* %A) nounwind {
-;CHECK: vld1i8:
+;CHECK-LABEL: vld1i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld1.8 {d16}, [r0:64]
%tmp1 = call <8 x i8> @llvm.arm.neon.vld1.v8i8(i8* %A, i32 16)
}
define <4 x i16> @vld1i16(i16* %A) nounwind {
-;CHECK: vld1i16:
+;CHECK-LABEL: vld1i16:
;CHECK: vld1.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call <4 x i16> @llvm.arm.neon.vld1.v4i16(i8* %tmp0, i32 1)
;Check for a post-increment updating load.
define <4 x i16> @vld1i16_update(i16** %ptr) nounwind {
-;CHECK: vld1i16_update:
+;CHECK-LABEL: vld1i16_update:
;CHECK: vld1.16 {d16}, [{{r[0-9]+}}]!
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
}
define <2 x i32> @vld1i32(i32* %A) nounwind {
-;CHECK: vld1i32:
+;CHECK-LABEL: vld1i32:
;CHECK: vld1.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call <2 x i32> @llvm.arm.neon.vld1.v2i32(i8* %tmp0, i32 1)
;Check for a post-increment updating load with register increment.
define <2 x i32> @vld1i32_update(i32** %ptr, i32 %inc) nounwind {
-;CHECK: vld1i32_update:
+;CHECK-LABEL: vld1i32_update:
;CHECK: vld1.32 {d16}, [{{r[0-9]+}}], {{r[0-9]+}}
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
}
define <2 x float> @vld1f(float* %A) nounwind {
-;CHECK: vld1f:
+;CHECK-LABEL: vld1f:
;CHECK: vld1.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call <2 x float> @llvm.arm.neon.vld1.v2f32(i8* %tmp0, i32 1)
}
define <1 x i64> @vld1i64(i64* %A) nounwind {
-;CHECK: vld1i64:
+;CHECK-LABEL: vld1i64:
;CHECK: vld1.64
%tmp0 = bitcast i64* %A to i8*
%tmp1 = call <1 x i64> @llvm.arm.neon.vld1.v1i64(i8* %tmp0, i32 1)
}
define <16 x i8> @vld1Qi8(i8* %A) nounwind {
-;CHECK: vld1Qi8:
+;CHECK-LABEL: vld1Qi8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.8 {d16, d17}, [r0:64]
%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
;Check for a post-increment updating load.
define <16 x i8> @vld1Qi8_update(i8** %ptr) nounwind {
-;CHECK: vld1Qi8_update:
+;CHECK-LABEL: vld1Qi8_update:
;CHECK: vld1.8 {d16, d17}, [{{r[0-9]+}}:64]!
%A = load i8** %ptr
%tmp1 = call <16 x i8> @llvm.arm.neon.vld1.v16i8(i8* %A, i32 8)
}
define <8 x i16> @vld1Qi16(i16* %A) nounwind {
-;CHECK: vld1Qi16:
+;CHECK-LABEL: vld1Qi16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
}
define <4 x i32> @vld1Qi32(i32* %A) nounwind {
-;CHECK: vld1Qi32:
+;CHECK-LABEL: vld1Qi32:
;CHECK: vld1.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call <4 x i32> @llvm.arm.neon.vld1.v4i32(i8* %tmp0, i32 1)
}
define <4 x float> @vld1Qf(float* %A) nounwind {
-;CHECK: vld1Qf:
+;CHECK-LABEL: vld1Qf:
;CHECK: vld1.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %tmp0, i32 1)
}
define <2 x i64> @vld1Qi64(i64* %A) nounwind {
-;CHECK: vld1Qi64:
+;CHECK-LABEL: vld1Qi64:
;CHECK: vld1.64
%tmp0 = bitcast i64* %A to i8*
%tmp1 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %tmp0, i32 1)
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
define <8 x i8> @vld2i8(i8* %A) nounwind {
-;CHECK: vld2i8:
+;CHECK-LABEL: vld2i8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld2.8 {d16, d17}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
}
define <4 x i16> @vld2i16(i16* %A) nounwind {
-;CHECK: vld2i16:
+;CHECK-LABEL: vld2i16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld2.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
}
define <2 x i32> @vld2i32(i32* %A) nounwind {
-;CHECK: vld2i32:
+;CHECK-LABEL: vld2i32:
;CHECK: vld2.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0, i32 1)
}
define <2 x float> @vld2f(float* %A) nounwind {
-;CHECK: vld2f:
+;CHECK-LABEL: vld2f:
;CHECK: vld2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1)
;Check for a post-increment updating load.
define <2 x float> @vld2f_update(float** %ptr) nounwind {
-;CHECK: vld2f_update:
+;CHECK-LABEL: vld2f_update:
;CHECK: vld2.32 {d16, d17}, [r1]!
%A = load float** %ptr
%tmp0 = bitcast float* %A to i8*
}
define <1 x i64> @vld2i64(i64* %A) nounwind {
-;CHECK: vld2i64:
+;CHECK-LABEL: vld2i64:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vld1.64 {d16, d17}, [r0:128]
%tmp0 = bitcast i64* %A to i8*
}
define <16 x i8> @vld2Qi8(i8* %A) nounwind {
-;CHECK: vld2Qi8:
+;CHECK-LABEL: vld2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 8)
;Check for a post-increment updating load with register increment.
define <16 x i8> @vld2Qi8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld2Qi8_update:
+;CHECK-LABEL: vld2Qi8_update:
;CHECK: vld2.8 {d16, d17, d18, d19}, [r2:128], r1
%A = load i8** %ptr
%tmp1 = call %struct.__neon_int8x16x2_t @llvm.arm.neon.vld2.v16i8(i8* %A, i32 16)
}
define <8 x i16> @vld2Qi16(i16* %A) nounwind {
-;CHECK: vld2Qi16:
+;CHECK-LABEL: vld2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
}
define <4 x i32> @vld2Qi32(i32* %A) nounwind {
-;CHECK: vld2Qi32:
+;CHECK-LABEL: vld2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
}
define <4 x float> @vld2Qf(float* %A) nounwind {
-;CHECK: vld2Qf:
+;CHECK-LABEL: vld2Qf:
;CHECK: vld2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call %struct.__neon_float32x4x2_t @llvm.arm.neon.vld2.v4f32(i8* %tmp0, i32 1)
%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld3i8(i8* %A) nounwind {
-;CHECK: vld3i8:
+;CHECK-LABEL: vld3i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
}
define <4 x i16> @vld3i16(i16* %A) nounwind {
-;CHECK: vld3i16:
+;CHECK-LABEL: vld3i16:
;CHECK: vld3.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
;Check for a post-increment updating load with register increment.
define <4 x i16> @vld3i16_update(i16** %ptr, i32 %inc) nounwind {
-;CHECK: vld3i16_update:
+;CHECK-LABEL: vld3i16_update:
;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
}
define <2 x i32> @vld3i32(i32* %A) nounwind {
-;CHECK: vld3i32:
+;CHECK-LABEL: vld3i32:
;CHECK: vld3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1)
}
define <2 x float> @vld3f(float* %A) nounwind {
-;CHECK: vld3f:
+;CHECK-LABEL: vld3f:
;CHECK: vld3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1)
}
define <1 x i64> @vld3i64(i64* %A) nounwind {
-;CHECK: vld3i64:
+;CHECK-LABEL: vld3i64:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld1.64 {d16, d17, d18}, [r0:64]
%tmp0 = bitcast i64* %A to i8*
}
define <16 x i8> @vld3Qi8(i8* %A) nounwind {
-;CHECK: vld3Qi8:
+;CHECK-LABEL: vld3Qi8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld3.8 {d16, d18, d20}, [r0:64]!
;CHECK: vld3.8 {d17, d19, d21}, [r0:64]
}
define <8 x i16> @vld3Qi16(i16* %A) nounwind {
-;CHECK: vld3Qi16:
+;CHECK-LABEL: vld3Qi16:
;CHECK: vld3.16
;CHECK: vld3.16
%tmp0 = bitcast i16* %A to i8*
}
define <4 x i32> @vld3Qi32(i32* %A) nounwind {
-;CHECK: vld3Qi32:
+;CHECK-LABEL: vld3Qi32:
;CHECK: vld3.32
;CHECK: vld3.32
%tmp0 = bitcast i32* %A to i8*
;Check for a post-increment updating load.
define <4 x i32> @vld3Qi32_update(i32** %ptr) nounwind {
-;CHECK: vld3Qi32_update:
+;CHECK-LABEL: vld3Qi32_update:
;CHECK: vld3.32 {d16, d18, d20}, [r[[R:[0-9]+]]]!
;CHECK: vld3.32 {d17, d19, d21}, [r[[R]]]!
%A = load i32** %ptr
}
define <4 x float> @vld3Qf(float* %A) nounwind {
-;CHECK: vld3Qf:
+;CHECK-LABEL: vld3Qf:
;CHECK: vld3.32
;CHECK: vld3.32
%tmp0 = bitcast float* %A to i8*
%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld4i8(i8* %A) nounwind {
-;CHECK: vld4i8:
+;CHECK-LABEL: vld4i8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 8)
;Check for a post-increment updating load with register increment.
define <8 x i8> @vld4i8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld4i8_update:
+;CHECK-LABEL: vld4i8_update:
;CHECK: vld4.8 {d16, d17, d18, d19}, [r2:128], r1
%A = load i8** %ptr
%tmp1 = call %struct.__neon_int8x8x4_t @llvm.arm.neon.vld4.v8i8(i8* %A, i32 16)
}
define <4 x i16> @vld4i16(i16* %A) nounwind {
-;CHECK: vld4i16:
+;CHECK-LABEL: vld4i16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
}
define <2 x i32> @vld4i32(i32* %A) nounwind {
-;CHECK: vld4i32:
+;CHECK-LABEL: vld4i32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
}
define <2 x float> @vld4f(float* %A) nounwind {
-;CHECK: vld4f:
+;CHECK-LABEL: vld4f:
;CHECK: vld4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = call %struct.__neon_float32x2x4_t @llvm.arm.neon.vld4.v2f32(i8* %tmp0, i32 1)
}
define <1 x i64> @vld4i64(i64* %A) nounwind {
-;CHECK: vld4i64:
+;CHECK-LABEL: vld4i64:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld1.64 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i64* %A to i8*
}
define <16 x i8> @vld4Qi8(i8* %A) nounwind {
-;CHECK: vld4Qi8:
+;CHECK-LABEL: vld4Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vld4.8 {d16, d18, d20, d22}, [r0:256]!
;CHECK: vld4.8 {d17, d19, d21, d23}, [r0:256]
}
define <8 x i16> @vld4Qi16(i16* %A) nounwind {
-;CHECK: vld4Qi16:
+;CHECK-LABEL: vld4Qi16:
;Check for no alignment specifier.
;CHECK: vld4.16 {d16, d18, d20, d22}, [r0]!
;CHECK: vld4.16 {d17, d19, d21, d23}, [r0]
;Check for a post-increment updating load.
define <8 x i16> @vld4Qi16_update(i16** %ptr) nounwind {
-;CHECK: vld4Qi16_update:
+;CHECK-LABEL: vld4Qi16_update:
;CHECK: vld4.16 {d16, d18, d20, d22}, [r1:64]!
;CHECK: vld4.16 {d17, d19, d21, d23}, [r1:64]!
%A = load i16** %ptr
}
define <4 x i32> @vld4Qi32(i32* %A) nounwind {
-;CHECK: vld4Qi32:
+;CHECK-LABEL: vld4Qi32:
;CHECK: vld4.32
;CHECK: vld4.32
%tmp0 = bitcast i32* %A to i8*
}
define <4 x float> @vld4Qf(float* %A) nounwind {
-;CHECK: vld4Qf:
+;CHECK-LABEL: vld4Qf:
;CHECK: vld4.32
;CHECK: vld4.32
%tmp0 = bitcast float* %A to i8*
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vld1dupi8(i8* %A) nounwind {
-;CHECK: vld1dupi8:
+;CHECK-LABEL: vld1dupi8:
;Check the (default) alignment value.
;CHECK: vld1.8 {d16[]}, [r0]
%tmp1 = load i8* %A, align 8
}
define <4 x i16> @vld1dupi16(i16* %A) nounwind {
-;CHECK: vld1dupi16:
+;CHECK-LABEL: vld1dupi16:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vld1.16 {d16[]}, [r0:16]
%tmp1 = load i16* %A, align 8
}
define <2 x i32> @vld1dupi32(i32* %A) nounwind {
-;CHECK: vld1dupi32:
+;CHECK-LABEL: vld1dupi32:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld1.32 {d16[]}, [r0:32]
%tmp1 = load i32* %A, align 8
}
define <2 x float> @vld1dupf(float* %A) nounwind {
-;CHECK: vld1dupf:
+;CHECK-LABEL: vld1dupf:
;CHECK: vld1.32 {d16[]}, [r0:32]
%tmp0 = load float* %A
%tmp1 = insertelement <2 x float> undef, float %tmp0, i32 0
}
define <16 x i8> @vld1dupQi8(i8* %A) nounwind {
-;CHECK: vld1dupQi8:
+;CHECK-LABEL: vld1dupQi8:
;Check the (default) alignment value.
;CHECK: vld1.8 {d16[], d17[]}, [r0]
%tmp1 = load i8* %A, align 8
}
define <4 x float> @vld1dupQf(float* %A) nounwind {
-;CHECK: vld1dupQf:
+;CHECK-LABEL: vld1dupQf:
;CHECK: vld1.32 {d16[], d17[]}, [r0:32]
%tmp0 = load float* %A
%tmp1 = insertelement <4 x float> undef, float %tmp0, i32 0
%struct.__neon_int2x32x2_t = type { <2 x i32>, <2 x i32> }
define <8 x i8> @vld2dupi8(i8* %A) nounwind {
-;CHECK: vld2dupi8:
+;CHECK-LABEL: vld2dupi8:
;Check the (default) alignment value.
;CHECK: vld2.8 {d16[], d17[]}, [r0]
%tmp0 = tail call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, i32 0, i32 1)
}
define <4 x i16> @vld2dupi16(i8* %A) nounwind {
-;CHECK: vld2dupi16:
+;CHECK-LABEL: vld2dupi16:
;Check that a power-of-two alignment smaller than the total size of the memory
;being loaded is ignored.
;CHECK: vld2.16 {d16[], d17[]}, [r0]
;Check for a post-increment updating load.
define <4 x i16> @vld2dupi16_update(i16** %ptr) nounwind {
-;CHECK: vld2dupi16_update:
+;CHECK-LABEL: vld2dupi16_update:
;CHECK: vld2.16 {d16[], d17[]}, [r1]!
%A = load i16** %ptr
%A2 = bitcast i16* %A to i8*
}
define <2 x i32> @vld2dupi32(i8* %A) nounwind {
-;CHECK: vld2dupi32:
+;CHECK-LABEL: vld2dupi32:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld2.32 {d16[], d17[]}, [r0:64]
%tmp0 = tail call %struct.__neon_int2x32x2_t @llvm.arm.neon.vld2lane.v2i32(i8* %A, <2 x i32> undef, <2 x i32> undef, i32 0, i32 16)
;Check for a post-increment updating load with register increment.
define <8 x i8> @vld3dupi8_update(i8** %ptr, i32 %inc) nounwind {
-;CHECK: vld3dupi8_update:
+;CHECK-LABEL: vld3dupi8_update:
;CHECK: vld3.8 {d16[], d17[], d18[]}, [r2], r1
%A = load i8** %ptr
%tmp0 = tail call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> undef, <8 x i8> undef, <8 x i8> undef, i32 0, i32 8)
}
define <4 x i16> @vld3dupi16(i8* %A) nounwind {
-;CHECK: vld3dupi16:
+;CHECK-LABEL: vld3dupi16:
;Check the (default) alignment value. VLD3 does not support alignment.
;CHECK: vld3.16 {d16[], d17[], d18[]}, [r0]
%tmp0 = tail call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3lane.v4i16(i8* %A, <4 x i16> undef, <4 x i16> undef, <4 x i16> undef, i32 0, i32 8)
;Check for a post-increment updating load.
define <4 x i16> @vld4dupi16_update(i16** %ptr) nounwind {
-;CHECK: vld4dupi16_update:
+;CHECK-LABEL: vld4dupi16_update:
;CHECK: vld4.16 {d16[], d17[], d18[], d19[]}, [r1]!
%A = load i16** %ptr
%A2 = bitcast i16* %A to i8*
}
define <2 x i32> @vld4dupi32(i8* %A) nounwind {
-;CHECK: vld4dupi32:
+;CHECK-LABEL: vld4dupi32:
;Check the alignment value. An 8-byte alignment is allowed here even though
;it is smaller than the total size of the memory being loaded.
;CHECK: vld4.32 {d16[], d17[], d18[], d19[]}, [r0:64]
; RUN: llc < %s -march=arm -mattr=+neon -regalloc=basic | FileCheck %s
define <8 x i8> @vld1lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld1lanei8:
+;CHECK-LABEL: vld1lanei8:
;Check the (default) alignment value.
;CHECK: vld1.8 {d16[3]}, [r0]
%tmp1 = load <8 x i8>* %B
}
define <4 x i16> @vld1lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld1lanei16:
+;CHECK-LABEL: vld1lanei16:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vld1.16 {d16[2]}, [r0:16]
%tmp1 = load <4 x i16>* %B
}
define <2 x i32> @vld1lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld1lanei32:
+;CHECK-LABEL: vld1lanei32:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x i32>* %B
}
define <2 x i32> @vld1lanei32a32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld1lanei32a32:
+;CHECK-LABEL: vld1lanei32a32:
;Check the alignment value. Legal values are none or :32.
;CHECK: vld1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x i32>* %B
}
define <2 x float> @vld1lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld1lanef:
+;CHECK-LABEL: vld1lanef:
;CHECK: vld1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x float>* %B
%tmp2 = load float* %A, align 4
}
define <16 x i8> @vld1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vld1laneQi8:
+;CHECK-LABEL: vld1laneQi8:
;CHECK: vld1.8 {d17[1]}, [r0]
%tmp1 = load <16 x i8>* %B
%tmp2 = load i8* %A, align 8
}
define <8 x i16> @vld1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld1laneQi16:
+;CHECK-LABEL: vld1laneQi16:
;CHECK: vld1.16 {d17[1]}, [r0:16]
%tmp1 = load <8 x i16>* %B
%tmp2 = load i16* %A, align 8
}
define <4 x i32> @vld1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld1laneQi32:
+;CHECK-LABEL: vld1laneQi32:
;CHECK: vld1.32 {d17[1]}, [r0:32]
%tmp1 = load <4 x i32>* %B
%tmp2 = load i32* %A, align 8
}
define <4 x float> @vld1laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld1laneQf:
+;CHECK-LABEL: vld1laneQf:
;CHECK: vld1.32 {d16[0]}, [r0:32]
%tmp1 = load <4 x float>* %B
%tmp2 = load float* %A
%struct.__neon_float32x4x2_t = type { <4 x float>, <4 x float> }
define <8 x i8> @vld2lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld2lanei8:
+;CHECK-LABEL: vld2lanei8:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
%tmp1 = load <8 x i8>* %B
}
define <4 x i16> @vld2lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld2lanei16:
+;CHECK-LABEL: vld2lanei16:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
%tmp0 = bitcast i16* %A to i8*
}
define <2 x i32> @vld2lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld2lanei32:
+;CHECK-LABEL: vld2lanei32:
;CHECK: vld2.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
;Check for a post-increment updating load.
define <2 x i32> @vld2lanei32_update(i32** %ptr, <2 x i32>* %B) nounwind {
-;CHECK: vld2lanei32_update:
+;CHECK-LABEL: vld2lanei32_update:
;CHECK: vld2.32 {d16[1], d17[1]}, [{{r[0-9]+}}]!
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
}
define <2 x float> @vld2lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld2lanef:
+;CHECK-LABEL: vld2lanef:
;CHECK: vld2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define <8 x i16> @vld2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld2laneQi16:
+;CHECK-LABEL: vld2laneQi16:
;Check the (default) alignment.
;CHECK: vld2.16 {d17[1], d19[1]}, [{{r[0-9]+}}]
%tmp0 = bitcast i16* %A to i8*
}
define <4 x i32> @vld2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld2laneQi32:
+;CHECK-LABEL: vld2laneQi32:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld2.32 {d17[0], d19[0]}, [{{r[0-9]+}}:64]
%tmp0 = bitcast i32* %A to i8*
}
define <4 x float> @vld2laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld2laneQf:
+;CHECK-LABEL: vld2laneQf:
;CHECK: vld2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
%struct.__neon_float32x4x3_t = type { <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld3lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld3lanei8:
+;CHECK-LABEL: vld3lanei8:
;CHECK: vld3.8
%tmp1 = load <8 x i8>* %B
%tmp2 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
}
define <4 x i16> @vld3lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld3lanei16:
+;CHECK-LABEL: vld3lanei16:
;Check the (default) alignment value. VLD3 does not support alignment.
;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
%tmp0 = bitcast i16* %A to i8*
}
define <2 x i32> @vld3lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld3lanei32:
+;CHECK-LABEL: vld3lanei32:
;CHECK: vld3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
}
define <2 x float> @vld3lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld3lanef:
+;CHECK-LABEL: vld3lanef:
;CHECK: vld3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define <8 x i16> @vld3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld3laneQi16:
+;CHECK-LABEL: vld3laneQi16:
;Check the (default) alignment value. VLD3 does not support alignment.
;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}]
%tmp0 = bitcast i16* %A to i8*
;Check for a post-increment updating load with register increment.
define <8 x i16> @vld3laneQi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vld3laneQi16_update:
+;CHECK-LABEL: vld3laneQi16_update:
;CHECK: vld3.16 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}], {{r[0-9]+}}
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
}
define <4 x i32> @vld3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld3laneQi32:
+;CHECK-LABEL: vld3laneQi32:
;CHECK: vld3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <4 x i32>* %B
}
define <4 x float> @vld3laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld3laneQf:
+;CHECK-LABEL: vld3laneQf:
;CHECK: vld3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
%struct.__neon_float32x4x4_t = type { <4 x float>, <4 x float>, <4 x float>, <4 x float> }
define <8 x i8> @vld4lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vld4lanei8:
+;CHECK-LABEL: vld4lanei8:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vld4.8 {d{{.*}}[1], d{{.*}}[1], d{{.*}}[1], d{{.*}}[1]}, [{{r[0-9]+}}:32]
%tmp1 = load <8 x i8>* %B
;Check for a post-increment updating load.
define <8 x i8> @vld4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vld4lanei8_update:
+;CHECK-LABEL: vld4lanei8_update:
;CHECK: vld4.8 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:32]!
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
}
define <4 x i16> @vld4lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vld4lanei16:
+;CHECK-LABEL: vld4lanei16:
;Check that a power-of-two alignment smaller than the total size of the memory
;being loaded is ignored.
;CHECK: vld4.16 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}]
}
define <2 x i32> @vld4lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vld4lanei32:
+;CHECK-LABEL: vld4lanei32:
;Check the alignment value. An 8-byte alignment is allowed here even though
;it is smaller than the total size of the memory being loaded.
;CHECK: vld4.32 {d16[1], d17[1], d18[1], d19[1]}, [{{r[0-9]+}}:64]
}
define <2 x float> @vld4lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vld4lanef:
+;CHECK-LABEL: vld4lanef:
;CHECK: vld4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define <8 x i16> @vld4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vld4laneQi16:
+;CHECK-LABEL: vld4laneQi16:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vld4.16 {d16[1], d18[1], d20[1], d22[1]}, [{{r[0-9]+}}:64]
%tmp0 = bitcast i16* %A to i8*
}
define <4 x i32> @vld4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vld4laneQi32:
+;CHECK-LABEL: vld4laneQi32:
;Check the (default) alignment.
;CHECK: vld4.32 {d17[0], d19[0], d21[0], d23[0]}, [{{r[0-9]+}}]
%tmp0 = bitcast i32* %A to i8*
}
define <4 x float> @vld4laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vld4laneQf:
+;CHECK-LABEL: vld4laneQf:
;CHECK: vld4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmins8:
+;CHECK-LABEL: vmins8:
;CHECK: vmin.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmins16:
+;CHECK-LABEL: vmins16:
;CHECK: vmin.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmins32:
+;CHECK-LABEL: vmins32:
;CHECK: vmin.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vminu8:
+;CHECK-LABEL: vminu8:
;CHECK: vmin.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vminu16:
+;CHECK-LABEL: vminu16:
;CHECK: vmin.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vminu32:
+;CHECK-LABEL: vminu32:
;CHECK: vmin.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vminf32:
+;CHECK-LABEL: vminf32:
;CHECK: vmin.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vminQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vminQs8:
+;CHECK-LABEL: vminQs8:
;CHECK: vmin.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vminQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vminQs16:
+;CHECK-LABEL: vminQs16:
;CHECK: vmin.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vminQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vminQs32:
+;CHECK-LABEL: vminQs32:
;CHECK: vmin.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vminQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vminQu8:
+;CHECK-LABEL: vminQu8:
;CHECK: vmin.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vminQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vminQu16:
+;CHECK-LABEL: vminQu16:
;CHECK: vmin.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vminQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vminQu32:
+;CHECK-LABEL: vminQu32:
;CHECK: vmin.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x float> @vminQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vminQf32:
+;CHECK-LABEL: vminQf32:
;CHECK: vmin.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
declare <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float>, <4 x float>) nounwind readnone
define <8 x i8> @vmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmaxs8:
+;CHECK-LABEL: vmaxs8:
;CHECK: vmax.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmaxs16:
+;CHECK-LABEL: vmaxs16:
;CHECK: vmax.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmaxs32:
+;CHECK-LABEL: vmaxs32:
;CHECK: vmax.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmaxu8:
+;CHECK-LABEL: vmaxu8:
;CHECK: vmax.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmaxu16:
+;CHECK-LABEL: vmaxu16:
;CHECK: vmax.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmaxu32:
+;CHECK-LABEL: vmaxu32:
;CHECK: vmax.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vmaxf32:
+;CHECK-LABEL: vmaxf32:
;CHECK: vmax.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vmaxQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmaxQs8:
+;CHECK-LABEL: vmaxQs8:
;CHECK: vmax.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vmaxQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmaxQs16:
+;CHECK-LABEL: vmaxQs16:
;CHECK: vmax.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vmaxQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmaxQs32:
+;CHECK-LABEL: vmaxQs32:
;CHECK: vmax.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <16 x i8> @vmaxQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmaxQu8:
+;CHECK-LABEL: vmaxQu8:
;CHECK: vmax.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vmaxQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmaxQu16:
+;CHECK-LABEL: vmaxQu16:
;CHECK: vmax.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vmaxQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmaxQu32:
+;CHECK-LABEL: vmaxQu32:
;CHECK: vmax.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x float> @vmaxQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vmaxQf32:
+;CHECK-LABEL: vmaxQf32:
;CHECK: vmax.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vmlai8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK: vmlai8:
+;CHECK-LABEL: vmlai8:
;CHECK: vmla.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vmlai16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlai16:
+;CHECK-LABEL: vmlai16:
;CHECK: vmla.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vmlai32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlai32:
+;CHECK-LABEL: vmlai32:
;CHECK: vmla.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vmlaf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK: vmlaf32:
+;CHECK-LABEL: vmlaf32:
;CHECK: vmla.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vmlaQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK: vmlaQi8:
+;CHECK-LABEL: vmlaQi8:
;CHECK: vmla.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vmlaQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vmlaQi16:
+;CHECK-LABEL: vmlaQi16:
;CHECK: vmla.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vmlaQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vmlaQi32:
+;CHECK-LABEL: vmlaQi32:
;CHECK: vmla.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x float> @vmlaQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK: vmlaQf32:
+;CHECK-LABEL: vmlaQf32:
;CHECK: vmla.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
}
define <8 x i16> @vmlals8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlals8:
+;CHECK-LABEL: vmlals8:
;CHECK: vmlal.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlals16:
+;CHECK-LABEL: vmlals16:
;CHECK: vmlal.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlals32:
+;CHECK-LABEL: vmlals32:
;CHECK: vmlal.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vmlalu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlalu8:
+;CHECK-LABEL: vmlalu8:
;CHECK: vmlal.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vmlalu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlalu16:
+;CHECK-LABEL: vmlalu16:
;CHECK: vmlal.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vmlalu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlalu32:
+;CHECK-LABEL: vmlalu32:
;CHECK: vmlal.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vmlsi8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8> * %C) nounwind {
-;CHECK: vmlsi8:
+;CHECK-LABEL: vmlsi8:
;CHECK: vmls.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vmlsi16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlsi16:
+;CHECK-LABEL: vmlsi16:
;CHECK: vmls.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vmlsi32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlsi32:
+;CHECK-LABEL: vmlsi32:
;CHECK: vmls.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vmlsf32(<2 x float>* %A, <2 x float>* %B, <2 x float>* %C) nounwind {
-;CHECK: vmlsf32:
+;CHECK-LABEL: vmlsf32:
;CHECK: vmls.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vmlsQi8(<16 x i8>* %A, <16 x i8>* %B, <16 x i8> * %C) nounwind {
-;CHECK: vmlsQi8:
+;CHECK-LABEL: vmlsQi8:
;CHECK: vmls.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vmlsQi16(<8 x i16>* %A, <8 x i16>* %B, <8 x i16>* %C) nounwind {
-;CHECK: vmlsQi16:
+;CHECK-LABEL: vmlsQi16:
;CHECK: vmls.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vmlsQi32(<4 x i32>* %A, <4 x i32>* %B, <4 x i32>* %C) nounwind {
-;CHECK: vmlsQi32:
+;CHECK-LABEL: vmlsQi32:
;CHECK: vmls.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x float> @vmlsQf32(<4 x float>* %A, <4 x float>* %B, <4 x float>* %C) nounwind {
-;CHECK: vmlsQf32:
+;CHECK-LABEL: vmlsQf32:
;CHECK: vmls.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
}
define <8 x i16> @vmlsls8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlsls8:
+;CHECK-LABEL: vmlsls8:
;CHECK: vmlsl.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlsls16:
+;CHECK-LABEL: vmlsls16:
;CHECK: vmlsl.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlsls32:
+;CHECK-LABEL: vmlsls32:
;CHECK: vmlsl.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vmlslu8(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vmlslu8:
+;CHECK-LABEL: vmlslu8:
;CHECK: vmlsl.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vmlslu16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vmlslu16:
+;CHECK-LABEL: vmlslu16:
;CHECK: vmlsl.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vmlslu32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vmlslu32:
+;CHECK-LABEL: vmlslu32:
;CHECK: vmlsl.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @v_movi8() nounwind {
-;CHECK: v_movi8:
+;CHECK-LABEL: v_movi8:
;CHECK: vmov.i8 d{{.*}}, #0x8
ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <4 x i16> @v_movi16a() nounwind {
-;CHECK: v_movi16a:
+;CHECK-LABEL: v_movi16a:
;CHECK: vmov.i16 d{{.*}}, #0x10
ret <4 x i16> < i16 16, i16 16, i16 16, i16 16 >
}
define <4 x i16> @v_movi16b() nounwind {
-;CHECK: v_movi16b:
+;CHECK-LABEL: v_movi16b:
;CHECK: vmov.i16 d{{.*}}, #0x1000
ret <4 x i16> < i16 4096, i16 4096, i16 4096, i16 4096 >
}
define <4 x i16> @v_mvni16a() nounwind {
-;CHECK: v_mvni16a:
+;CHECK-LABEL: v_mvni16a:
;CHECK: vmvn.i16 d{{.*}}, #0x10
ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
}
define <4 x i16> @v_mvni16b() nounwind {
-;CHECK: v_mvni16b:
+;CHECK-LABEL: v_mvni16b:
;CHECK: vmvn.i16 d{{.*}}, #0x1000
ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
}
define <2 x i32> @v_movi32a() nounwind {
-;CHECK: v_movi32a:
+;CHECK-LABEL: v_movi32a:
;CHECK: vmov.i32 d{{.*}}, #0x20
ret <2 x i32> < i32 32, i32 32 >
}
define <2 x i32> @v_movi32b() nounwind {
-;CHECK: v_movi32b:
+;CHECK-LABEL: v_movi32b:
;CHECK: vmov.i32 d{{.*}}, #0x2000
ret <2 x i32> < i32 8192, i32 8192 >
}
define <2 x i32> @v_movi32c() nounwind {
-;CHECK: v_movi32c:
+;CHECK-LABEL: v_movi32c:
;CHECK: vmov.i32 d{{.*}}, #0x200000
ret <2 x i32> < i32 2097152, i32 2097152 >
}
define <2 x i32> @v_movi32d() nounwind {
-;CHECK: v_movi32d:
+;CHECK-LABEL: v_movi32d:
;CHECK: vmov.i32 d{{.*}}, #0x20000000
ret <2 x i32> < i32 536870912, i32 536870912 >
}
define <2 x i32> @v_movi32e() nounwind {
-;CHECK: v_movi32e:
+;CHECK-LABEL: v_movi32e:
;CHECK: vmov.i32 d{{.*}}, #0x20ff
ret <2 x i32> < i32 8447, i32 8447 >
}
define <2 x i32> @v_movi32f() nounwind {
-;CHECK: v_movi32f:
+;CHECK-LABEL: v_movi32f:
;CHECK: vmov.i32 d{{.*}}, #0x20ffff
ret <2 x i32> < i32 2162687, i32 2162687 >
}
define <2 x i32> @v_mvni32a() nounwind {
-;CHECK: v_mvni32a:
+;CHECK-LABEL: v_mvni32a:
;CHECK: vmvn.i32 d{{.*}}, #0x20
ret <2 x i32> < i32 4294967263, i32 4294967263 >
}
define <2 x i32> @v_mvni32b() nounwind {
-;CHECK: v_mvni32b:
+;CHECK-LABEL: v_mvni32b:
;CHECK: vmvn.i32 d{{.*}}, #0x2000
ret <2 x i32> < i32 4294959103, i32 4294959103 >
}
define <2 x i32> @v_mvni32c() nounwind {
-;CHECK: v_mvni32c:
+;CHECK-LABEL: v_mvni32c:
;CHECK: vmvn.i32 d{{.*}}, #0x200000
ret <2 x i32> < i32 4292870143, i32 4292870143 >
}
define <2 x i32> @v_mvni32d() nounwind {
-;CHECK: v_mvni32d:
+;CHECK-LABEL: v_mvni32d:
;CHECK: vmvn.i32 d{{.*}}, #0x20000000
ret <2 x i32> < i32 3758096383, i32 3758096383 >
}
define <2 x i32> @v_mvni32e() nounwind {
-;CHECK: v_mvni32e:
+;CHECK-LABEL: v_mvni32e:
;CHECK: vmvn.i32 d{{.*}}, #0x20ff
ret <2 x i32> < i32 4294958848, i32 4294958848 >
}
define <2 x i32> @v_mvni32f() nounwind {
-;CHECK: v_mvni32f:
+;CHECK-LABEL: v_mvni32f:
;CHECK: vmvn.i32 d{{.*}}, #0x20ffff
ret <2 x i32> < i32 4292804608, i32 4292804608 >
}
define <1 x i64> @v_movi64() nounwind {
-;CHECK: v_movi64:
+;CHECK-LABEL: v_movi64:
;CHECK: vmov.i64 d{{.*}}, #0xff0000ff0000ffff
ret <1 x i64> < i64 18374687574888349695 >
}
define <16 x i8> @v_movQi8() nounwind {
-;CHECK: v_movQi8:
+;CHECK-LABEL: v_movQi8:
;CHECK: vmov.i8 q{{.*}}, #0x8
ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <8 x i16> @v_movQi16a() nounwind {
-;CHECK: v_movQi16a:
+;CHECK-LABEL: v_movQi16a:
;CHECK: vmov.i16 q{{.*}}, #0x10
ret <8 x i16> < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
}
define <8 x i16> @v_movQi16b() nounwind {
-;CHECK: v_movQi16b:
+;CHECK-LABEL: v_movQi16b:
;CHECK: vmov.i16 q{{.*}}, #0x1000
ret <8 x i16> < i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096, i16 4096 >
}
define <4 x i32> @v_movQi32a() nounwind {
-;CHECK: v_movQi32a:
+;CHECK-LABEL: v_movQi32a:
;CHECK: vmov.i32 q{{.*}}, #0x20
ret <4 x i32> < i32 32, i32 32, i32 32, i32 32 >
}
define <4 x i32> @v_movQi32b() nounwind {
-;CHECK: v_movQi32b:
+;CHECK-LABEL: v_movQi32b:
;CHECK: vmov.i32 q{{.*}}, #0x2000
ret <4 x i32> < i32 8192, i32 8192, i32 8192, i32 8192 >
}
define <4 x i32> @v_movQi32c() nounwind {
-;CHECK: v_movQi32c:
+;CHECK-LABEL: v_movQi32c:
;CHECK: vmov.i32 q{{.*}}, #0x200000
ret <4 x i32> < i32 2097152, i32 2097152, i32 2097152, i32 2097152 >
}
define <4 x i32> @v_movQi32d() nounwind {
-;CHECK: v_movQi32d:
+;CHECK-LABEL: v_movQi32d:
;CHECK: vmov.i32 q{{.*}}, #0x20000000
ret <4 x i32> < i32 536870912, i32 536870912, i32 536870912, i32 536870912 >
}
define <4 x i32> @v_movQi32e() nounwind {
-;CHECK: v_movQi32e:
+;CHECK-LABEL: v_movQi32e:
;CHECK: vmov.i32 q{{.*}}, #0x20ff
ret <4 x i32> < i32 8447, i32 8447, i32 8447, i32 8447 >
}
define <4 x i32> @v_movQi32f() nounwind {
-;CHECK: v_movQi32f:
+;CHECK-LABEL: v_movQi32f:
;CHECK: vmov.i32 q{{.*}}, #0x20ffff
ret <4 x i32> < i32 2162687, i32 2162687, i32 2162687, i32 2162687 >
}
define <2 x i64> @v_movQi64() nounwind {
-;CHECK: v_movQi64:
+;CHECK-LABEL: v_movQi64:
;CHECK: vmov.i64 q{{.*}}, #0xff0000ff0000ffff
ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
}
%struct.int8x8_t = type { <8 x i8> }
define void @vdupn128(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
entry:
-;CHECK: vdupn128:
+;CHECK-LABEL: vdupn128:
;CHECK: vmov.i8 d{{.*}}, #0x80
%0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
store <8 x i8> <i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128, i8 -128>, <8 x i8>* %0, align 8
define void @vdupnneg75(%struct.int8x8_t* noalias nocapture sret %agg.result) nounwind {
entry:
-;CHECK: vdupnneg75:
+;CHECK-LABEL: vdupnneg75:
;CHECK: vmov.i8 d{{.*}}, #0xb5
%0 = getelementptr inbounds %struct.int8x8_t* %agg.result, i32 0, i32 0 ; <<8 x i8>*> [#uses=1]
store <8 x i8> <i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75, i8 -75>, <8 x i8>* %0, align 8
}
define <8 x i16> @vmovls8(<8 x i8>* %A) nounwind {
-;CHECK: vmovls8:
+;CHECK-LABEL: vmovls8:
;CHECK: vmovl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = sext <8 x i8> %tmp1 to <8 x i16>
}
define <4 x i32> @vmovls16(<4 x i16>* %A) nounwind {
-;CHECK: vmovls16:
+;CHECK-LABEL: vmovls16:
;CHECK: vmovl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = sext <4 x i16> %tmp1 to <4 x i32>
}
define <2 x i64> @vmovls32(<2 x i32>* %A) nounwind {
-;CHECK: vmovls32:
+;CHECK-LABEL: vmovls32:
;CHECK: vmovl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = sext <2 x i32> %tmp1 to <2 x i64>
}
define <8 x i16> @vmovlu8(<8 x i8>* %A) nounwind {
-;CHECK: vmovlu8:
+;CHECK-LABEL: vmovlu8:
;CHECK: vmovl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = zext <8 x i8> %tmp1 to <8 x i16>
}
define <4 x i32> @vmovlu16(<4 x i16>* %A) nounwind {
-;CHECK: vmovlu16:
+;CHECK-LABEL: vmovlu16:
;CHECK: vmovl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = zext <4 x i16> %tmp1 to <4 x i32>
}
define <2 x i64> @vmovlu32(<2 x i32>* %A) nounwind {
-;CHECK: vmovlu32:
+;CHECK-LABEL: vmovlu32:
;CHECK: vmovl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = zext <2 x i32> %tmp1 to <2 x i64>
}
define <8 x i8> @vmovni16(<8 x i16>* %A) nounwind {
-;CHECK: vmovni16:
+;CHECK-LABEL: vmovni16:
;CHECK: vmovn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = trunc <8 x i16> %tmp1 to <8 x i8>
}
define <4 x i16> @vmovni32(<4 x i32>* %A) nounwind {
-;CHECK: vmovni32:
+;CHECK-LABEL: vmovni32:
;CHECK: vmovn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = trunc <4 x i32> %tmp1 to <4 x i16>
}
define <2 x i32> @vmovni64(<2 x i64>* %A) nounwind {
-;CHECK: vmovni64:
+;CHECK-LABEL: vmovni64:
;CHECK: vmovn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = trunc <2 x i64> %tmp1 to <2 x i32>
}
define <8 x i8> @vqmovns16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovns16:
+;CHECK-LABEL: vqmovns16:
;CHECK: vqmovn.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovns.v8i8(<8 x i16> %tmp1)
}
define <4 x i16> @vqmovns32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovns32:
+;CHECK-LABEL: vqmovns32:
;CHECK: vqmovn.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovns.v4i16(<4 x i32> %tmp1)
}
define <2 x i32> @vqmovns64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovns64:
+;CHECK-LABEL: vqmovns64:
;CHECK: vqmovn.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovns.v2i32(<2 x i64> %tmp1)
}
define <8 x i8> @vqmovnu16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovnu16:
+;CHECK-LABEL: vqmovnu16:
;CHECK: vqmovn.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnu.v8i8(<8 x i16> %tmp1)
}
define <4 x i16> @vqmovnu32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovnu32:
+;CHECK-LABEL: vqmovnu32:
;CHECK: vqmovn.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnu.v4i16(<4 x i32> %tmp1)
}
define <2 x i32> @vqmovnu64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovnu64:
+;CHECK-LABEL: vqmovnu64:
;CHECK: vqmovn.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnu.v2i32(<2 x i64> %tmp1)
}
define <8 x i8> @vqmovuns16(<8 x i16>* %A) nounwind {
-;CHECK: vqmovuns16:
+;CHECK-LABEL: vqmovuns16:
;CHECK: vqmovun.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqmovnsu.v8i8(<8 x i16> %tmp1)
}
define <4 x i16> @vqmovuns32(<4 x i32>* %A) nounwind {
-;CHECK: vqmovuns32:
+;CHECK-LABEL: vqmovuns32:
;CHECK: vqmovun.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqmovnsu.v4i16(<4 x i32> %tmp1)
}
define <2 x i32> @vqmovuns64(<2 x i64>* %A) nounwind {
-;CHECK: vqmovuns64:
+;CHECK-LABEL: vqmovuns64:
;CHECK: vqmovun.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqmovnsu.v2i32(<2 x i64> %tmp1)
; rdar://10437054
define void @v_mov_v2f32(<2 x float>* nocapture %p) nounwind {
entry:
-;CHECK: v_mov_v2f32:
+;CHECK-LABEL: v_mov_v2f32:
;CHECK: vmov.f32 d{{.*}}, #-1.600000e+01
store <2 x float> <float -1.600000e+01, float -1.600000e+01>, <2 x float>* %p, align 4
ret void
define void @v_mov_v4f32(<4 x float>* nocapture %p) nounwind {
entry:
-;CHECK: v_mov_v4f32:
+;CHECK-LABEL: v_mov_v4f32:
;CHECK: vmov.f32 q{{.*}}, #3.100000e+01
store <4 x float> <float 3.100000e+01, float 3.100000e+01, float 3.100000e+01, float 3.100000e+01>, <4 x float>* %p, align 4
ret void
define void @v_mov_v4f32_undef(<4 x float> * nocapture %p) nounwind {
entry:
-;CHECK: v_mov_v4f32_undef:
+;CHECK-LABEL: v_mov_v4f32_undef:
;CHECK: vmov.f32 q{{.*}}, #1.000000e+00
%a = load <4 x float> *%p
%b = fadd <4 x float> %a, <float undef, float 1.0, float 1.0, float 1.0>
; RUN: llc < %s -march=arm -mcpu=cortex-a8 | FileCheck %s
define <8 x i8> @vmuli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmuli8:
+;CHECK-LABEL: vmuli8:
;CHECK: vmul.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vmuli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmuli16:
+;CHECK-LABEL: vmuli16:
;CHECK: vmul.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vmuli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmuli32:
+;CHECK-LABEL: vmuli32:
;CHECK: vmul.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vmulf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vmulf32:
+;CHECK-LABEL: vmulf32:
;CHECK: vmul.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <8 x i8> @vmulp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulp8:
+;CHECK-LABEL: vmulp8:
;CHECK: vmul.p8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <16 x i8> @vmulQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmulQi8:
+;CHECK-LABEL: vmulQi8:
;CHECK: vmul.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vmulQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vmulQi16:
+;CHECK-LABEL: vmulQi16:
;CHECK: vmul.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vmulQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vmulQi32:
+;CHECK-LABEL: vmulQi32:
;CHECK: vmul.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <4 x float> @vmulQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vmulQf32:
+;CHECK-LABEL: vmulQf32:
;CHECK: vmul.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
}
define <16 x i8> @vmulQp8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vmulQp8:
+;CHECK-LABEL: vmulQp8:
;CHECK: vmul.p8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vmulls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulls8:
+;CHECK-LABEL: vmulls8:
;CHECK: vmull.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <8 x i16> @vmulls8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmulls8_int:
+;CHECK-LABEL: vmulls8_int:
;CHECK: vmull.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmulls16:
+;CHECK-LABEL: vmulls16:
;CHECK: vmull.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <4 x i32> @vmulls16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmulls16_int:
+;CHECK-LABEL: vmulls16_int:
;CHECK: vmull.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmulls32:
+;CHECK-LABEL: vmulls32:
;CHECK: vmull.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x i64> @vmulls32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmulls32_int:
+;CHECK-LABEL: vmulls32_int:
;CHECK: vmull.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vmullu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullu8:
+;CHECK-LABEL: vmullu8:
;CHECK: vmull.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <8 x i16> @vmullu8_int(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullu8_int:
+;CHECK-LABEL: vmullu8_int:
;CHECK: vmull.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vmullu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmullu16:
+;CHECK-LABEL: vmullu16:
;CHECK: vmull.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <4 x i32> @vmullu16_int(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vmullu16_int:
+;CHECK-LABEL: vmullu16_int:
;CHECK: vmull.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vmullu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmullu32:
+;CHECK-LABEL: vmullu32:
;CHECK: vmull.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x i64> @vmullu32_int(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vmullu32_int:
+;CHECK-LABEL: vmullu32_int:
;CHECK: vmull.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vmullp8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vmullp8:
+;CHECK-LABEL: vmullp8:
;CHECK: vmull.p8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
; rdar://9197392
define void @distribute(i16* %dst, i8* %src, i32 %mul) nounwind {
entry:
-; CHECK: distribute:
+; CHECK-LABEL: distribute:
; CHECK: vmull.u8 [[REG1:(q[0-9]+)]], d{{.*}}, [[REG2:(d[0-9]+)]]
; CHECK: vmlal.u8 [[REG1]], d{{.*}}, [[REG2]]
%0 = trunc i32 %mul to i8
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vnegs8(<8 x i8>* %A) nounwind {
-;CHECK: vnegs8:
+;CHECK-LABEL: vnegs8:
;CHECK: vneg.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = sub <8 x i8> zeroinitializer, %tmp1
}
define <4 x i16> @vnegs16(<4 x i16>* %A) nounwind {
-;CHECK: vnegs16:
+;CHECK-LABEL: vnegs16:
;CHECK: vneg.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = sub <4 x i16> zeroinitializer, %tmp1
}
define <2 x i32> @vnegs32(<2 x i32>* %A) nounwind {
-;CHECK: vnegs32:
+;CHECK-LABEL: vnegs32:
;CHECK: vneg.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = sub <2 x i32> zeroinitializer, %tmp1
}
define <2 x float> @vnegf32(<2 x float>* %A) nounwind {
-;CHECK: vnegf32:
+;CHECK-LABEL: vnegf32:
;CHECK: vneg.f32
%tmp1 = load <2 x float>* %A
%tmp2 = fsub <2 x float> < float -0.000000e+00, float -0.000000e+00 >, %tmp1
}
define <16 x i8> @vnegQs8(<16 x i8>* %A) nounwind {
-;CHECK: vnegQs8:
+;CHECK-LABEL: vnegQs8:
;CHECK: vneg.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = sub <16 x i8> zeroinitializer, %tmp1
}
define <8 x i16> @vnegQs16(<8 x i16>* %A) nounwind {
-;CHECK: vnegQs16:
+;CHECK-LABEL: vnegQs16:
;CHECK: vneg.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = sub <8 x i16> zeroinitializer, %tmp1
}
define <4 x i32> @vnegQs32(<4 x i32>* %A) nounwind {
-;CHECK: vnegQs32:
+;CHECK-LABEL: vnegQs32:
;CHECK: vneg.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = sub <4 x i32> zeroinitializer, %tmp1
}
define <4 x float> @vnegQf32(<4 x float>* %A) nounwind {
-;CHECK: vnegQf32:
+;CHECK-LABEL: vnegQf32:
;CHECK: vneg.f32
%tmp1 = load <4 x float>* %A
%tmp2 = fsub <4 x float> < float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.000000e+00 >, %tmp1
}
define <8 x i8> @vqnegs8(<8 x i8>* %A) nounwind {
-;CHECK: vqnegs8:
+;CHECK-LABEL: vqnegs8:
;CHECK: vqneg.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqneg.v8i8(<8 x i8> %tmp1)
}
define <4 x i16> @vqnegs16(<4 x i16>* %A) nounwind {
-;CHECK: vqnegs16:
+;CHECK-LABEL: vqnegs16:
;CHECK: vqneg.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqneg.v4i16(<4 x i16> %tmp1)
}
define <2 x i32> @vqnegs32(<2 x i32>* %A) nounwind {
-;CHECK: vqnegs32:
+;CHECK-LABEL: vqnegs32:
;CHECK: vqneg.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqneg.v2i32(<2 x i32> %tmp1)
}
define <16 x i8> @vqnegQs8(<16 x i8>* %A) nounwind {
-;CHECK: vqnegQs8:
+;CHECK-LABEL: vqnegQs8:
;CHECK: vqneg.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqneg.v16i8(<16 x i8> %tmp1)
}
define <8 x i16> @vqnegQs16(<8 x i16>* %A) nounwind {
-;CHECK: vqnegQs16:
+;CHECK-LABEL: vqnegQs16:
;CHECK: vqneg.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqneg.v8i16(<8 x i16> %tmp1)
}
define <4 x i32> @vqnegQs32(<4 x i32>* %A) nounwind {
-;CHECK: vqnegQs32:
+;CHECK-LABEL: vqnegQs32:
;CHECK: vqneg.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqneg.v4i32(<4 x i32> %tmp1)
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <4 x i16> @vpadals8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpadals8:
+;CHECK-LABEL: vpadals8:
;CHECK: vpadal.s8
%tmp1 = load <4 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <2 x i32> @vpadals16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpadals16:
+;CHECK-LABEL: vpadals16:
;CHECK: vpadal.s16
%tmp1 = load <2 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <1 x i64> @vpadals32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpadals32:
+;CHECK-LABEL: vpadals32:
;CHECK: vpadal.s32
%tmp1 = load <1 x i64>* %A
%tmp2 = load <2 x i32>* %B
}
define <4 x i16> @vpadalu8(<4 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpadalu8:
+;CHECK-LABEL: vpadalu8:
;CHECK: vpadal.u8
%tmp1 = load <4 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <2 x i32> @vpadalu16(<2 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpadalu16:
+;CHECK-LABEL: vpadalu16:
;CHECK: vpadal.u16
%tmp1 = load <2 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <1 x i64> @vpadalu32(<1 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpadalu32:
+;CHECK-LABEL: vpadalu32:
;CHECK: vpadal.u32
%tmp1 = load <1 x i64>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vpadalQs8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vpadalQs8:
+;CHECK-LABEL: vpadalQs8:
;CHECK: vpadal.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <16 x i8>* %B
}
define <4 x i32> @vpadalQs16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vpadalQs16:
+;CHECK-LABEL: vpadalQs16:
;CHECK: vpadal.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <8 x i16>* %B
}
define <2 x i64> @vpadalQs32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vpadalQs32:
+;CHECK-LABEL: vpadalQs32:
;CHECK: vpadal.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <4 x i32>* %B
}
define <8 x i16> @vpadalQu8(<8 x i16>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vpadalQu8:
+;CHECK-LABEL: vpadalQu8:
;CHECK: vpadal.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <16 x i8>* %B
}
define <4 x i32> @vpadalQu16(<4 x i32>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vpadalQu16:
+;CHECK-LABEL: vpadalQu16:
;CHECK: vpadal.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <8 x i16>* %B
}
define <2 x i64> @vpadalQu32(<2 x i64>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vpadalQu32:
+;CHECK-LABEL: vpadalQu32:
;CHECK: vpadal.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <4 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vpaddi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpaddi8:
+;CHECK-LABEL: vpaddi8:
;CHECK: vpadd.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vpaddi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpaddi16:
+;CHECK-LABEL: vpaddi16:
;CHECK: vpadd.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vpaddi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpaddi32:
+;CHECK-LABEL: vpaddi32:
;CHECK: vpadd.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vpaddf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpaddf32:
+;CHECK-LABEL: vpaddf32:
;CHECK: vpadd.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
declare <2 x float> @llvm.arm.neon.vpadd.v2f32(<2 x float>, <2 x float>) nounwind readnone
define <4 x i16> @vpaddls8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddls8:
+;CHECK-LABEL: vpaddls8:
;CHECK: vpaddl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddls.v4i16.v8i8(<8 x i8> %tmp1)
}
define <2 x i32> @vpaddls16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddls16:
+;CHECK-LABEL: vpaddls16:
;CHECK: vpaddl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddls.v2i32.v4i16(<4 x i16> %tmp1)
}
define <1 x i64> @vpaddls32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddls32:
+;CHECK-LABEL: vpaddls32:
;CHECK: vpaddl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddls.v1i64.v2i32(<2 x i32> %tmp1)
}
define <4 x i16> @vpaddlu8(<8 x i8>* %A) nounwind {
-;CHECK: vpaddlu8:
+;CHECK-LABEL: vpaddlu8:
;CHECK: vpaddl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vpaddlu.v4i16.v8i8(<8 x i8> %tmp1)
}
define <2 x i32> @vpaddlu16(<4 x i16>* %A) nounwind {
-;CHECK: vpaddlu16:
+;CHECK-LABEL: vpaddlu16:
;CHECK: vpaddl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vpaddlu.v2i32.v4i16(<4 x i16> %tmp1)
}
define <1 x i64> @vpaddlu32(<2 x i32>* %A) nounwind {
-;CHECK: vpaddlu32:
+;CHECK-LABEL: vpaddlu32:
;CHECK: vpaddl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vpaddlu.v1i64.v2i32(<2 x i32> %tmp1)
}
define <8 x i16> @vpaddlQs8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQs8:
+;CHECK-LABEL: vpaddlQs8:
;CHECK: vpaddl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddls.v8i16.v16i8(<16 x i8> %tmp1)
}
define <4 x i32> @vpaddlQs16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQs16:
+;CHECK-LABEL: vpaddlQs16:
;CHECK: vpaddl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddls.v4i32.v8i16(<8 x i16> %tmp1)
}
define <2 x i64> @vpaddlQs32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQs32:
+;CHECK-LABEL: vpaddlQs32:
;CHECK: vpaddl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddls.v2i64.v4i32(<4 x i32> %tmp1)
}
define <8 x i16> @vpaddlQu8(<16 x i8>* %A) nounwind {
-;CHECK: vpaddlQu8:
+;CHECK-LABEL: vpaddlQu8:
;CHECK: vpaddl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vpaddlu.v8i16.v16i8(<16 x i8> %tmp1)
}
define <4 x i32> @vpaddlQu16(<8 x i16>* %A) nounwind {
-;CHECK: vpaddlQu16:
+;CHECK-LABEL: vpaddlQu16:
;CHECK: vpaddl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vpaddlu.v4i32.v8i16(<8 x i16> %tmp1)
}
define <2 x i64> @vpaddlQu32(<4 x i32>* %A) nounwind {
-;CHECK: vpaddlQu32:
+;CHECK-LABEL: vpaddlQu32:
;CHECK: vpaddl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vpaddlu.v2i64.v4i32(<4 x i32> %tmp1)
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vpmins8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmins8:
+;CHECK-LABEL: vpmins8:
;CHECK: vpmin.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vpmins16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmins16:
+;CHECK-LABEL: vpmins16:
;CHECK: vpmin.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vpmins32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmins32:
+;CHECK-LABEL: vpmins32:
;CHECK: vpmin.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vpminu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpminu8:
+;CHECK-LABEL: vpminu8:
;CHECK: vpmin.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vpminu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpminu16:
+;CHECK-LABEL: vpminu16:
;CHECK: vpmin.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vpminu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpminu32:
+;CHECK-LABEL: vpminu32:
;CHECK: vpmin.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vpminf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpminf32:
+;CHECK-LABEL: vpminf32:
;CHECK: vpmin.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
declare <2 x float> @llvm.arm.neon.vpmins.v2f32(<2 x float>, <2 x float>) nounwind readnone
define <8 x i8> @vpmaxs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmaxs8:
+;CHECK-LABEL: vpmaxs8:
;CHECK: vpmax.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vpmaxs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmaxs16:
+;CHECK-LABEL: vpmaxs16:
;CHECK: vpmax.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vpmaxs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmaxs32:
+;CHECK-LABEL: vpmaxs32:
;CHECK: vpmax.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i8> @vpmaxu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vpmaxu8:
+;CHECK-LABEL: vpmaxu8:
;CHECK: vpmax.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vpmaxu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vpmaxu16:
+;CHECK-LABEL: vpmaxu16:
;CHECK: vpmax.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vpmaxu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vpmaxu32:
+;CHECK-LABEL: vpmaxu32:
;CHECK: vpmax.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <2 x float> @vpmaxf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vpmaxf32:
+;CHECK-LABEL: vpmaxf32:
;CHECK: vpmax.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vqadds8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqadds8:
+;CHECK-LABEL: vqadds8:
;CHECK: vqadd.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vqadds16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqadds16:
+;CHECK-LABEL: vqadds16:
;CHECK: vqadd.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqadds32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqadds32:
+;CHECK-LABEL: vqadds32:
;CHECK: vqadd.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vqadds64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqadds64:
+;CHECK-LABEL: vqadds64:
;CHECK: vqadd.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <8 x i8> @vqaddu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqaddu8:
+;CHECK-LABEL: vqaddu8:
;CHECK: vqadd.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vqaddu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqaddu16:
+;CHECK-LABEL: vqaddu16:
;CHECK: vqadd.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqaddu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqaddu32:
+;CHECK-LABEL: vqaddu32:
;CHECK: vqadd.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vqaddu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqaddu64:
+;CHECK-LABEL: vqaddu64:
;CHECK: vqadd.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vqaddQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqaddQs8:
+;CHECK-LABEL: vqaddQs8:
;CHECK: vqadd.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vqaddQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqaddQs16:
+;CHECK-LABEL: vqaddQs16:
;CHECK: vqadd.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqaddQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqaddQs32:
+;CHECK-LABEL: vqaddQs32:
;CHECK: vqadd.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vqaddQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqaddQs64:
+;CHECK-LABEL: vqaddQs64:
;CHECK: vqadd.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <16 x i8> @vqaddQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqaddQu8:
+;CHECK-LABEL: vqaddQu8:
;CHECK: vqadd.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vqaddQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqaddQu16:
+;CHECK-LABEL: vqaddQu16:
;CHECK: vqadd.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqaddQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqaddQu32:
+;CHECK-LABEL: vqaddQu32:
;CHECK: vqadd.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vqaddQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqaddQu64:
+;CHECK-LABEL: vqaddQu64:
;CHECK: vqadd.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
target triple = "thumbv7-elf"
define <4 x i16> @vqdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqdmulhs16:
+;CHECK-LABEL: vqdmulhs16:
;CHECK: vqdmulh.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqdmulhs32:
+;CHECK-LABEL: vqdmulhs32:
;CHECK: vqdmulh.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vqdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqdmulhQs16:
+;CHECK-LABEL: vqdmulhQs16:
;CHECK: vqdmulh.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqdmulhQs32:
+;CHECK-LABEL: vqdmulhQs32:
;CHECK: vqdmulh.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
declare <4 x i32> @llvm.arm.neon.vqdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i16> @vqrdmulhs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrdmulhs16:
+;CHECK-LABEL: vqrdmulhs16:
;CHECK: vqrdmulh.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqrdmulhs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrdmulhs32:
+;CHECK-LABEL: vqrdmulhs32:
;CHECK: vqrdmulh.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vqrdmulhQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrdmulhQs16:
+;CHECK-LABEL: vqrdmulhQs16:
;CHECK: vqrdmulh.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqrdmulhQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrdmulhQs32:
+;CHECK-LABEL: vqrdmulhQs32:
;CHECK: vqrdmulh.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
define <4 x i32> @vqdmulls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqdmulls16:
+;CHECK-LABEL: vqdmulls16:
;CHECK: vqdmull.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vqdmulls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqdmulls32:
+;CHECK-LABEL: vqdmulls32:
;CHECK: vqdmull.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
declare <2 x i64> @llvm.arm.neon.vqdmull.v2i64(<2 x i32>, <2 x i32>) nounwind readnone
define <4 x i32> @vqdmlals16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vqdmlals16:
+;CHECK-LABEL: vqdmlals16:
;CHECK: vqdmlal.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vqdmlals32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vqdmlals32:
+;CHECK-LABEL: vqdmlals32:
;CHECK: vqdmlal.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
declare <2 x i64> @llvm.arm.neon.vqdmlal.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
define <4 x i32> @vqdmlsls16(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
-;CHECK: vqdmlsls16:
+;CHECK-LABEL: vqdmlsls16:
;CHECK: vqdmlsl.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vqdmlsls32(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
-;CHECK: vqdmlsls32:
+;CHECK-LABEL: vqdmlsls32:
;CHECK: vqdmlsl.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vqshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqshls8:
+;CHECK-LABEL: vqshls8:
;CHECK: vqshl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vqshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqshls16:
+;CHECK-LABEL: vqshls16:
;CHECK: vqshl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqshls32:
+;CHECK-LABEL: vqshls32:
;CHECK: vqshl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vqshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqshls64:
+;CHECK-LABEL: vqshls64:
;CHECK: vqshl.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <8 x i8> @vqshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqshlu8:
+;CHECK-LABEL: vqshlu8:
;CHECK: vqshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vqshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqshlu16:
+;CHECK-LABEL: vqshlu16:
;CHECK: vqshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqshlu32:
+;CHECK-LABEL: vqshlu32:
;CHECK: vqshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vqshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqshlu64:
+;CHECK-LABEL: vqshlu64:
;CHECK: vqshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vqshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqshlQs8:
+;CHECK-LABEL: vqshlQs8:
;CHECK: vqshl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vqshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqshlQs16:
+;CHECK-LABEL: vqshlQs16:
;CHECK: vqshl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqshlQs32:
+;CHECK-LABEL: vqshlQs32:
;CHECK: vqshl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vqshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqshlQs64:
+;CHECK-LABEL: vqshlQs64:
;CHECK: vqshl.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <16 x i8> @vqshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqshlQu8:
+;CHECK-LABEL: vqshlQu8:
;CHECK: vqshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vqshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqshlQu16:
+;CHECK-LABEL: vqshlQu16:
;CHECK: vqshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqshlQu32:
+;CHECK-LABEL: vqshlQu32:
;CHECK: vqshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vqshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqshlQu64:
+;CHECK-LABEL: vqshlQu64:
;CHECK: vqshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @vqshls_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshls_n8:
+;CHECK-LABEL: vqshls_n8:
;CHECK: vqshl.s8{{.*#7}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <4 x i16> @vqshls_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshls_n16:
+;CHECK-LABEL: vqshls_n16:
;CHECK: vqshl.s16{{.*#15}}
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
}
define <2 x i32> @vqshls_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshls_n32:
+;CHECK-LABEL: vqshls_n32:
;CHECK: vqshl.s32{{.*#31}}
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
}
define <1 x i64> @vqshls_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshls_n64:
+;CHECK-LABEL: vqshls_n64:
;CHECK: vqshl.s64{{.*#63}}
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
}
define <8 x i8> @vqshlu_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshlu_n8:
+;CHECK-LABEL: vqshlu_n8:
;CHECK: vqshl.u8{{.*#7}}
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <4 x i16> @vqshlu_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshlu_n16:
+;CHECK-LABEL: vqshlu_n16:
;CHECK: vqshl.u16{{.*#15}}
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
}
define <2 x i32> @vqshlu_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshlu_n32:
+;CHECK-LABEL: vqshlu_n32:
;CHECK: vqshl.u32{{.*#31}}
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
}
define <1 x i64> @vqshlu_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshlu_n64:
+;CHECK-LABEL: vqshlu_n64:
;CHECK: vqshl.u64{{.*#63}}
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
}
define <8 x i8> @vqshlsu_n8(<8 x i8>* %A) nounwind {
-;CHECK: vqshlsu_n8:
+;CHECK-LABEL: vqshlsu_n8:
;CHECK: vqshlu.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftsu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <4 x i16> @vqshlsu_n16(<4 x i16>* %A) nounwind {
-;CHECK: vqshlsu_n16:
+;CHECK-LABEL: vqshlsu_n16:
;CHECK: vqshlu.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftsu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
}
define <2 x i32> @vqshlsu_n32(<2 x i32>* %A) nounwind {
-;CHECK: vqshlsu_n32:
+;CHECK-LABEL: vqshlsu_n32:
;CHECK: vqshlu.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftsu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
}
define <1 x i64> @vqshlsu_n64(<1 x i64>* %A) nounwind {
-;CHECK: vqshlsu_n64:
+;CHECK-LABEL: vqshlsu_n64:
;CHECK: vqshlu.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vqshiftsu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
}
define <16 x i8> @vqshlQs_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQs_n8:
+;CHECK-LABEL: vqshlQs_n8:
;CHECK: vqshl.s8{{.*#7}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <8 x i16> @vqshlQs_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQs_n16:
+;CHECK-LABEL: vqshlQs_n16:
;CHECK: vqshl.s16{{.*#15}}
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
}
define <4 x i32> @vqshlQs_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQs_n32:
+;CHECK-LABEL: vqshlQs_n32:
;CHECK: vqshl.s32{{.*#31}}
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
}
define <2 x i64> @vqshlQs_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQs_n64:
+;CHECK-LABEL: vqshlQs_n64:
;CHECK: vqshl.s64{{.*#63}}
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
}
define <16 x i8> @vqshlQu_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQu_n8:
+;CHECK-LABEL: vqshlQu_n8:
;CHECK: vqshl.u8{{.*#7}}
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <8 x i16> @vqshlQu_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQu_n16:
+;CHECK-LABEL: vqshlQu_n16:
;CHECK: vqshl.u16{{.*#15}}
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
}
define <4 x i32> @vqshlQu_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQu_n32:
+;CHECK-LABEL: vqshlQu_n32:
;CHECK: vqshl.u32{{.*#31}}
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
}
define <2 x i64> @vqshlQu_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQu_n64:
+;CHECK-LABEL: vqshlQu_n64:
;CHECK: vqshl.u64{{.*#63}}
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
}
define <16 x i8> @vqshlQsu_n8(<16 x i8>* %A) nounwind {
-;CHECK: vqshlQsu_n8:
+;CHECK-LABEL: vqshlQsu_n8:
;CHECK: vqshlu.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vqshiftsu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <8 x i16> @vqshlQsu_n16(<8 x i16>* %A) nounwind {
-;CHECK: vqshlQsu_n16:
+;CHECK-LABEL: vqshlQsu_n16:
;CHECK: vqshlu.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vqshiftsu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
}
define <4 x i32> @vqshlQsu_n32(<4 x i32>* %A) nounwind {
-;CHECK: vqshlQsu_n32:
+;CHECK-LABEL: vqshlQsu_n32:
;CHECK: vqshlu.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vqshiftsu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
}
define <2 x i64> @vqshlQsu_n64(<2 x i64>* %A) nounwind {
-;CHECK: vqshlQsu_n64:
+;CHECK-LABEL: vqshlQsu_n64:
;CHECK: vqshlu.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
declare <2 x i64> @llvm.arm.neon.vqshiftsu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vqrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqrshls8:
+;CHECK-LABEL: vqrshls8:
;CHECK: vqrshl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vqrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrshls16:
+;CHECK-LABEL: vqrshls16:
;CHECK: vqrshl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrshls32:
+;CHECK-LABEL: vqrshls32:
;CHECK: vqrshl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vqrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqrshls64:
+;CHECK-LABEL: vqrshls64:
;CHECK: vqrshl.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <8 x i8> @vqrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqrshlu8:
+;CHECK-LABEL: vqrshlu8:
;CHECK: vqrshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vqrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqrshlu16:
+;CHECK-LABEL: vqrshlu16:
;CHECK: vqrshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqrshlu32:
+;CHECK-LABEL: vqrshlu32:
;CHECK: vqrshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vqrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqrshlu64:
+;CHECK-LABEL: vqrshlu64:
;CHECK: vqrshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vqrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqrshlQs8:
+;CHECK-LABEL: vqrshlQs8:
;CHECK: vqrshl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vqrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrshlQs16:
+;CHECK-LABEL: vqrshlQs16:
;CHECK: vqrshl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrshlQs32:
+;CHECK-LABEL: vqrshlQs32:
;CHECK: vqrshl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vqrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqrshlQs64:
+;CHECK-LABEL: vqrshlQs64:
;CHECK: vqrshl.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <16 x i8> @vqrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqrshlQu8:
+;CHECK-LABEL: vqrshlQu8:
;CHECK: vqrshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vqrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqrshlQu16:
+;CHECK-LABEL: vqrshlQu16:
;CHECK: vqrshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqrshlQu32:
+;CHECK-LABEL: vqrshlQu32:
;CHECK: vqrshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vqrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqrshlQu64:
+;CHECK-LABEL: vqrshlQu64:
;CHECK: vqrshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vqshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrns8:
+;CHECK-LABEL: vqshrns8:
;CHECK: vqshrn.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
}
define <4 x i16> @vqshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrns16:
+;CHECK-LABEL: vqshrns16:
;CHECK: vqshrn.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
}
define <2 x i32> @vqshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrns32:
+;CHECK-LABEL: vqshrns32:
;CHECK: vqshrn.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
}
define <8 x i8> @vqshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqshrnu8:
+;CHECK-LABEL: vqshrnu8:
;CHECK: vqshrn.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
}
define <4 x i16> @vqshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqshrnu16:
+;CHECK-LABEL: vqshrnu16:
;CHECK: vqshrn.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
}
define <2 x i32> @vqshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqshrnu32:
+;CHECK-LABEL: vqshrnu32:
;CHECK: vqshrn.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
}
define <8 x i8> @vqshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqshruns8:
+;CHECK-LABEL: vqshruns8:
;CHECK: vqshrun.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
}
define <4 x i16> @vqshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqshruns16:
+;CHECK-LABEL: vqshruns16:
;CHECK: vqshrun.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
}
define <2 x i32> @vqshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqshruns32:
+;CHECK-LABEL: vqshruns32:
;CHECK: vqshrun.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
declare <2 x i32> @llvm.arm.neon.vqshiftnsu.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vqrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrns8:
+;CHECK-LABEL: vqrshrns8:
;CHECK: vqrshrn.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftns.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
}
define <4 x i16> @vqrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrns16:
+;CHECK-LABEL: vqrshrns16:
;CHECK: vqrshrn.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftns.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
}
define <2 x i32> @vqrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrns32:
+;CHECK-LABEL: vqrshrns32:
;CHECK: vqrshrn.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftns.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
}
define <8 x i8> @vqrshrnu8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshrnu8:
+;CHECK-LABEL: vqrshrnu8:
;CHECK: vqrshrn.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
}
define <4 x i16> @vqrshrnu16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshrnu16:
+;CHECK-LABEL: vqrshrnu16:
;CHECK: vqrshrn.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
}
define <2 x i32> @vqrshrnu32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshrnu32:
+;CHECK-LABEL: vqrshrnu32:
;CHECK: vqrshrn.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
}
define <8 x i8> @vqrshruns8(<8 x i16>* %A) nounwind {
-;CHECK: vqrshruns8:
+;CHECK-LABEL: vqrshruns8:
;CHECK: vqrshrun.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vqrshiftnsu.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
}
define <4 x i16> @vqrshruns16(<4 x i32>* %A) nounwind {
-;CHECK: vqrshruns16:
+;CHECK-LABEL: vqrshruns16:
;CHECK: vqrshrun.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vqrshiftnsu.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
}
define <2 x i32> @vqrshruns32(<2 x i64>* %A) nounwind {
-;CHECK: vqrshruns32:
+;CHECK-LABEL: vqrshruns32:
;CHECK: vqrshrun.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vqrshiftnsu.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vqsubs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqsubs8:
+;CHECK-LABEL: vqsubs8:
;CHECK: vqsub.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vqsubs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqsubs16:
+;CHECK-LABEL: vqsubs16:
;CHECK: vqsub.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqsubs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqsubs32:
+;CHECK-LABEL: vqsubs32:
;CHECK: vqsub.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vqsubs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqsubs64:
+;CHECK-LABEL: vqsubs64:
;CHECK: vqsub.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <8 x i8> @vqsubu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vqsubu8:
+;CHECK-LABEL: vqsubu8:
;CHECK: vqsub.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vqsubu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vqsubu16:
+;CHECK-LABEL: vqsubu16:
;CHECK: vqsub.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vqsubu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vqsubu32:
+;CHECK-LABEL: vqsubu32:
;CHECK: vqsub.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vqsubu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vqsubu64:
+;CHECK-LABEL: vqsubu64:
;CHECK: vqsub.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vqsubQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqsubQs8:
+;CHECK-LABEL: vqsubQs8:
;CHECK: vqsub.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vqsubQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqsubQs16:
+;CHECK-LABEL: vqsubQs16:
;CHECK: vqsub.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqsubQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqsubQs32:
+;CHECK-LABEL: vqsubQs32:
;CHECK: vqsub.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vqsubQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqsubQs64:
+;CHECK-LABEL: vqsubQs64:
;CHECK: vqsub.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <16 x i8> @vqsubQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vqsubQu8:
+;CHECK-LABEL: vqsubQu8:
;CHECK: vqsub.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vqsubQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vqsubQu16:
+;CHECK-LABEL: vqsubQu16:
;CHECK: vqsub.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vqsubQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vqsubQu32:
+;CHECK-LABEL: vqsubQu32:
;CHECK: vqsub.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vqsubQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vqsubQu64:
+;CHECK-LABEL: vqsubQu64:
;CHECK: vqsub.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <2 x i32> @vrecpei32(<2 x i32>* %A) nounwind {
-;CHECK: vrecpei32:
+;CHECK-LABEL: vrecpei32:
;CHECK: vrecpe.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrecpe.v2i32(<2 x i32> %tmp1)
}
define <4 x i32> @vrecpeQi32(<4 x i32>* %A) nounwind {
-;CHECK: vrecpeQi32:
+;CHECK-LABEL: vrecpeQi32:
;CHECK: vrecpe.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrecpe.v4i32(<4 x i32> %tmp1)
}
define <2 x float> @vrecpef32(<2 x float>* %A) nounwind {
-;CHECK: vrecpef32:
+;CHECK-LABEL: vrecpef32:
;CHECK: vrecpe.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vrecpe.v2f32(<2 x float> %tmp1)
}
define <4 x float> @vrecpeQf32(<4 x float>* %A) nounwind {
-;CHECK: vrecpeQf32:
+;CHECK-LABEL: vrecpeQf32:
;CHECK: vrecpe.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float> %tmp1)
declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
define <2 x float> @vrecpsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vrecpsf32:
+;CHECK-LABEL: vrecpsf32:
;CHECK: vrecps.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <4 x float> @vrecpsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vrecpsQf32:
+;CHECK-LABEL: vrecpsQf32:
;CHECK: vrecps.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
define <2 x i32> @vrsqrtei32(<2 x i32>* %A) nounwind {
-;CHECK: vrsqrtei32:
+;CHECK-LABEL: vrsqrtei32:
;CHECK: vrsqrte.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrsqrte.v2i32(<2 x i32> %tmp1)
}
define <4 x i32> @vrsqrteQi32(<4 x i32>* %A) nounwind {
-;CHECK: vrsqrteQi32:
+;CHECK-LABEL: vrsqrteQi32:
;CHECK: vrsqrte.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrsqrte.v4i32(<4 x i32> %tmp1)
}
define <2 x float> @vrsqrtef32(<2 x float>* %A) nounwind {
-;CHECK: vrsqrtef32:
+;CHECK-LABEL: vrsqrtef32:
;CHECK: vrsqrte.f32
%tmp1 = load <2 x float>* %A
%tmp2 = call <2 x float> @llvm.arm.neon.vrsqrte.v2f32(<2 x float> %tmp1)
}
define <4 x float> @vrsqrteQf32(<4 x float>* %A) nounwind {
-;CHECK: vrsqrteQf32:
+;CHECK-LABEL: vrsqrteQf32:
;CHECK: vrsqrte.f32
%tmp1 = load <4 x float>* %A
%tmp2 = call <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float> %tmp1)
declare <4 x float> @llvm.arm.neon.vrsqrte.v4f32(<4 x float>) nounwind readnone
define <2 x float> @vrsqrtsf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vrsqrtsf32:
+;CHECK-LABEL: vrsqrtsf32:
;CHECK: vrsqrts.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <4 x float> @vrsqrtsQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vrsqrtsQf32:
+;CHECK-LABEL: vrsqrtsQf32:
;CHECK: vrsqrts.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
; lowering we also need to adjust the cost.
%T0_10 = type <16 x i16>
%T1_10 = type <16 x i1>
-; CHECK: func_blend10:
+; CHECK-LABEL: func_blend10:
define void @func_blend10(%T0_10* %loadaddr, %T0_10* %loadaddr2,
%T1_10* %blend, %T0_10* %storeaddr) {
%v0 = load %T0_10* %loadaddr
}
%T0_14 = type <8 x i32>
%T1_14 = type <8 x i1>
-; CHECK: func_blend14:
+; CHECK-LABEL: func_blend14:
define void @func_blend14(%T0_14* %loadaddr, %T0_14* %loadaddr2,
%T1_14* %blend, %T0_14* %storeaddr) {
%v0 = load %T0_14* %loadaddr
}
%T0_15 = type <16 x i32>
%T1_15 = type <16 x i1>
-; CHECK: func_blend15:
+; CHECK-LABEL: func_blend15:
define void @func_blend15(%T0_15* %loadaddr, %T0_15* %loadaddr2,
%T1_15* %blend, %T0_15* %storeaddr) {
; CHECK: vbsl
}
%T0_18 = type <4 x i64>
%T1_18 = type <4 x i1>
-; CHECK: func_blend18:
+; CHECK-LABEL: func_blend18:
define void @func_blend18(%T0_18* %loadaddr, %T0_18* %loadaddr2,
%T1_18* %blend, %T0_18* %storeaddr) {
; CHECK: vbsl
}
%T0_19 = type <8 x i64>
%T1_19 = type <8 x i1>
-; CHECK: func_blend19:
+; CHECK-LABEL: func_blend19:
define void @func_blend19(%T0_19* %loadaddr, %T0_19* %loadaddr2,
%T1_19* %blend, %T0_19* %storeaddr) {
; CHECK: vbsl
}
%T0_20 = type <16 x i64>
%T1_20 = type <16 x i1>
-; CHECK: func_blend20:
+; CHECK-LABEL: func_blend20:
define void @func_blend20(%T0_20* %loadaddr, %T0_20* %loadaddr2,
%T1_20* %blend, %T0_20* %storeaddr) {
; CHECK: vbsl
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshls8:
+;CHECK-LABEL: vshls8:
;CHECK: vshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshls16:
+;CHECK-LABEL: vshls16:
;CHECK: vshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshls32:
+;CHECK-LABEL: vshls32:
;CHECK: vshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshls64:
+;CHECK-LABEL: vshls64:
;CHECK: vshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
-;CHECK: vshli8:
+;CHECK-LABEL: vshli8:
;CHECK: vshl.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = shl <8 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
}
define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
-;CHECK: vshli16:
+;CHECK-LABEL: vshli16:
;CHECK: vshl.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = shl <4 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15 >
}
define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
-;CHECK: vshli32:
+;CHECK-LABEL: vshli32:
;CHECK: vshl.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = shl <2 x i32> %tmp1, < i32 31, i32 31 >
}
define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
-;CHECK: vshli64:
+;CHECK-LABEL: vshli64:
;CHECK: vshl.i64
%tmp1 = load <1 x i64>* %A
%tmp2 = shl <1 x i64> %tmp1, < i64 63 >
}
define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQs8:
+;CHECK-LABEL: vshlQs8:
;CHECK: vshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQs16:
+;CHECK-LABEL: vshlQs16:
;CHECK: vshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQs32:
+;CHECK-LABEL: vshlQs32:
;CHECK: vshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQs64:
+;CHECK-LABEL: vshlQs64:
;CHECK: vshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
-;CHECK: vshlQi8:
+;CHECK-LABEL: vshlQi8:
;CHECK: vshl.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = shl <16 x i8> %tmp1, < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >
}
define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
-;CHECK: vshlQi16:
+;CHECK-LABEL: vshlQi16:
;CHECK: vshl.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = shl <8 x i16> %tmp1, < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >
}
define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
-;CHECK: vshlQi32:
+;CHECK-LABEL: vshlQi32:
;CHECK: vshl.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = shl <4 x i32> %tmp1, < i32 31, i32 31, i32 31, i32 31 >
}
define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
-;CHECK: vshlQi64:
+;CHECK-LABEL: vshlQi64:
;CHECK: vshl.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = shl <2 x i64> %tmp1, < i64 63, i64 63 >
}
define <8 x i8> @vlshru8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vlshru8:
+;CHECK-LABEL: vlshru8:
;CHECK: vneg.s8
;CHECK: vshl.u8
%tmp1 = load <8 x i8>* %A
}
define <4 x i16> @vlshru16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vlshru16:
+;CHECK-LABEL: vlshru16:
;CHECK: vneg.s16
;CHECK: vshl.u16
%tmp1 = load <4 x i16>* %A
}
define <2 x i32> @vlshru32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vlshru32:
+;CHECK-LABEL: vlshru32:
;CHECK: vneg.s32
;CHECK: vshl.u32
%tmp1 = load <2 x i32>* %A
}
define <1 x i64> @vlshru64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vlshru64:
+;CHECK-LABEL: vlshru64:
;CHECK: vsub.i64
;CHECK: vshl.u64
%tmp1 = load <1 x i64>* %A
}
define <8 x i8> @vlshri8(<8 x i8>* %A) nounwind {
-;CHECK: vlshri8:
+;CHECK-LABEL: vlshri8:
;CHECK: vshr.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = lshr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <4 x i16> @vlshri16(<4 x i16>* %A) nounwind {
-;CHECK: vlshri16:
+;CHECK-LABEL: vlshri16:
;CHECK: vshr.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = lshr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
}
define <2 x i32> @vlshri32(<2 x i32>* %A) nounwind {
-;CHECK: vlshri32:
+;CHECK-LABEL: vlshri32:
;CHECK: vshr.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = lshr <2 x i32> %tmp1, < i32 32, i32 32 >
}
define <1 x i64> @vlshri64(<1 x i64>* %A) nounwind {
-;CHECK: vlshri64:
+;CHECK-LABEL: vlshri64:
;CHECK: vshr.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = lshr <1 x i64> %tmp1, < i64 64 >
}
define <16 x i8> @vlshrQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vlshrQu8:
+;CHECK-LABEL: vlshrQu8:
;CHECK: vneg.s8
;CHECK: vshl.u8
%tmp1 = load <16 x i8>* %A
}
define <8 x i16> @vlshrQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vlshrQu16:
+;CHECK-LABEL: vlshrQu16:
;CHECK: vneg.s16
;CHECK: vshl.u16
%tmp1 = load <8 x i16>* %A
}
define <4 x i32> @vlshrQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vlshrQu32:
+;CHECK-LABEL: vlshrQu32:
;CHECK: vneg.s32
;CHECK: vshl.u32
%tmp1 = load <4 x i32>* %A
}
define <2 x i64> @vlshrQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vlshrQu64:
+;CHECK-LABEL: vlshrQu64:
;CHECK: vsub.i64
;CHECK: vshl.u64
%tmp1 = load <2 x i64>* %A
}
define <16 x i8> @vlshrQi8(<16 x i8>* %A) nounwind {
-;CHECK: vlshrQi8:
+;CHECK-LABEL: vlshrQi8:
;CHECK: vshr.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = lshr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <8 x i16> @vlshrQi16(<8 x i16>* %A) nounwind {
-;CHECK: vlshrQi16:
+;CHECK-LABEL: vlshrQi16:
;CHECK: vshr.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = lshr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
}
define <4 x i32> @vlshrQi32(<4 x i32>* %A) nounwind {
-;CHECK: vlshrQi32:
+;CHECK-LABEL: vlshrQi32:
;CHECK: vshr.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = lshr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
}
define <2 x i64> @vlshrQi64(<2 x i64>* %A) nounwind {
-;CHECK: vlshrQi64:
+;CHECK-LABEL: vlshrQi64:
;CHECK: vshr.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = lshr <2 x i64> %tmp1, < i64 64, i64 64 >
}
define <8 x i8> @vashrs8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vashrs8:
+;CHECK-LABEL: vashrs8:
;CHECK: vneg.s8
;CHECK: vshl.s8
%tmp1 = load <8 x i8>* %A
}
define <4 x i16> @vashrs16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vashrs16:
+;CHECK-LABEL: vashrs16:
;CHECK: vneg.s16
;CHECK: vshl.s16
%tmp1 = load <4 x i16>* %A
}
define <2 x i32> @vashrs32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vashrs32:
+;CHECK-LABEL: vashrs32:
;CHECK: vneg.s32
;CHECK: vshl.s32
%tmp1 = load <2 x i32>* %A
}
define <1 x i64> @vashrs64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vashrs64:
+;CHECK-LABEL: vashrs64:
;CHECK: vsub.i64
;CHECK: vshl.s64
%tmp1 = load <1 x i64>* %A
}
define <8 x i8> @vashri8(<8 x i8>* %A) nounwind {
-;CHECK: vashri8:
+;CHECK-LABEL: vashri8:
;CHECK: vshr.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = ashr <8 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <4 x i16> @vashri16(<4 x i16>* %A) nounwind {
-;CHECK: vashri16:
+;CHECK-LABEL: vashri16:
;CHECK: vshr.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = ashr <4 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16 >
}
define <2 x i32> @vashri32(<2 x i32>* %A) nounwind {
-;CHECK: vashri32:
+;CHECK-LABEL: vashri32:
;CHECK: vshr.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = ashr <2 x i32> %tmp1, < i32 32, i32 32 >
}
define <1 x i64> @vashri64(<1 x i64>* %A) nounwind {
-;CHECK: vashri64:
+;CHECK-LABEL: vashri64:
;CHECK: vshr.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = ashr <1 x i64> %tmp1, < i64 64 >
}
define <16 x i8> @vashrQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vashrQs8:
+;CHECK-LABEL: vashrQs8:
;CHECK: vneg.s8
;CHECK: vshl.s8
%tmp1 = load <16 x i8>* %A
}
define <8 x i16> @vashrQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vashrQs16:
+;CHECK-LABEL: vashrQs16:
;CHECK: vneg.s16
;CHECK: vshl.s16
%tmp1 = load <8 x i16>* %A
}
define <4 x i32> @vashrQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vashrQs32:
+;CHECK-LABEL: vashrQs32:
;CHECK: vneg.s32
;CHECK: vshl.s32
%tmp1 = load <4 x i32>* %A
}
define <2 x i64> @vashrQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vashrQs64:
+;CHECK-LABEL: vashrQs64:
;CHECK: vsub.i64
;CHECK: vshl.s64
%tmp1 = load <2 x i64>* %A
}
define <16 x i8> @vashrQi8(<16 x i8>* %A) nounwind {
-;CHECK: vashrQi8:
+;CHECK-LABEL: vashrQi8:
;CHECK: vshr.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = ashr <16 x i8> %tmp1, < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
}
define <8 x i16> @vashrQi16(<8 x i16>* %A) nounwind {
-;CHECK: vashrQi16:
+;CHECK-LABEL: vashrQi16:
;CHECK: vshr.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = ashr <8 x i16> %tmp1, < i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16, i16 16 >
}
define <4 x i32> @vashrQi32(<4 x i32>* %A) nounwind {
-;CHECK: vashrQi32:
+;CHECK-LABEL: vashrQi32:
;CHECK: vshr.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = ashr <4 x i32> %tmp1, < i32 32, i32 32, i32 32, i32 32 >
}
define <2 x i64> @vashrQi64(<2 x i64>* %A) nounwind {
-;CHECK: vashrQi64:
+;CHECK-LABEL: vashrQi64:
;CHECK: vshr.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = ashr <2 x i64> %tmp1, < i64 64, i64 64 >
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vsli8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsli8:
+;CHECK-LABEL: vsli8:
;CHECK: vsli.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vsli16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsli16:
+;CHECK-LABEL: vsli16:
;CHECK: vsli.16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vsli32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsli32:
+;CHECK-LABEL: vsli32:
;CHECK: vsli.32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vsli64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsli64:
+;CHECK-LABEL: vsli64:
;CHECK: vsli.64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vsliQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsliQ8:
+;CHECK-LABEL: vsliQ8:
;CHECK: vsli.8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vsliQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsliQ16:
+;CHECK-LABEL: vsliQ16:
;CHECK: vsli.16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vsliQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsliQ32:
+;CHECK-LABEL: vsliQ32:
;CHECK: vsli.32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vsliQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsliQ64:
+;CHECK-LABEL: vsliQ64:
;CHECK: vsli.64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @vsri8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsri8:
+;CHECK-LABEL: vsri8:
;CHECK: vsri.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vsri16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsri16:
+;CHECK-LABEL: vsri16:
;CHECK: vsri.16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vsri32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsri32:
+;CHECK-LABEL: vsri32:
;CHECK: vsri.32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vsri64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsri64:
+;CHECK-LABEL: vsri64:
;CHECK: vsri.64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vsriQ8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsriQ8:
+;CHECK-LABEL: vsriQ8:
;CHECK: vsri.8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vsriQ16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsriQ16:
+;CHECK-LABEL: vsriQ16:
;CHECK: vsri.16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vsriQ32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsriQ32:
+;CHECK-LABEL: vsriQ32:
;CHECK: vsri.32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vsriQ64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsriQ64:
+;CHECK-LABEL: vsriQ64:
;CHECK: vsri.64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshls8:
+;CHECK-LABEL: vshls8:
;CHECK: vshl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshls16:
+;CHECK-LABEL: vshls16:
;CHECK: vshl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshls32:
+;CHECK-LABEL: vshls32:
;CHECK: vshl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshls64:
+;CHECK-LABEL: vshls64:
;CHECK: vshl.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <8 x i8> @vshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vshlu8:
+;CHECK-LABEL: vshlu8:
;CHECK: vshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vshlu16:
+;CHECK-LABEL: vshlu16:
;CHECK: vshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vshlu32:
+;CHECK-LABEL: vshlu32:
;CHECK: vshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vshlu64:
+;CHECK-LABEL: vshlu64:
;CHECK: vshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQs8:
+;CHECK-LABEL: vshlQs8:
;CHECK: vshl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQs16:
+;CHECK-LABEL: vshlQs16:
;CHECK: vshl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQs32:
+;CHECK-LABEL: vshlQs32:
;CHECK: vshl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQs64:
+;CHECK-LABEL: vshlQs64:
;CHECK: vshl.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <16 x i8> @vshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vshlQu8:
+;CHECK-LABEL: vshlQu8:
;CHECK: vshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vshlQu16:
+;CHECK-LABEL: vshlQu16:
;CHECK: vshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vshlQu32:
+;CHECK-LABEL: vshlQu32:
;CHECK: vshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vshlQu64:
+;CHECK-LABEL: vshlQu64:
;CHECK: vshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
; Test a mix of both signed and unsigned intrinsics.
define <8 x i8> @vshli8(<8 x i8>* %A) nounwind {
-;CHECK: vshli8:
+;CHECK-LABEL: vshli8:
;CHECK: vshl.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <4 x i16> @vshli16(<4 x i16>* %A) nounwind {
-;CHECK: vshli16:
+;CHECK-LABEL: vshli16:
;CHECK: vshl.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
}
define <2 x i32> @vshli32(<2 x i32>* %A) nounwind {
-;CHECK: vshli32:
+;CHECK-LABEL: vshli32:
;CHECK: vshl.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
}
define <1 x i64> @vshli64(<1 x i64>* %A) nounwind {
-;CHECK: vshli64:
+;CHECK-LABEL: vshli64:
;CHECK: vshl.i64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 63 >)
}
define <16 x i8> @vshlQi8(<16 x i8>* %A) nounwind {
-;CHECK: vshlQi8:
+;CHECK-LABEL: vshlQi8:
;CHECK: vshl.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <8 x i16> @vshlQi16(<8 x i16>* %A) nounwind {
-;CHECK: vshlQi16:
+;CHECK-LABEL: vshlQi16:
;CHECK: vshl.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15, i16 15 >)
}
define <4 x i32> @vshlQi32(<4 x i32>* %A) nounwind {
-;CHECK: vshlQi32:
+;CHECK-LABEL: vshlQi32:
;CHECK: vshl.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 31, i32 31, i32 31, i32 31 >)
}
define <2 x i64> @vshlQi64(<2 x i64>* %A) nounwind {
-;CHECK: vshlQi64:
+;CHECK-LABEL: vshlQi64:
;CHECK: vshl.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 63, i64 63 >)
; Right shift by immediate:
define <8 x i8> @vshrs8(<8 x i8>* %A) nounwind {
-;CHECK: vshrs8:
+;CHECK-LABEL: vshrs8:
;CHECK: vshr.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
}
define <4 x i16> @vshrs16(<4 x i16>* %A) nounwind {
-;CHECK: vshrs16:
+;CHECK-LABEL: vshrs16:
;CHECK: vshr.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
}
define <2 x i32> @vshrs32(<2 x i32>* %A) nounwind {
-;CHECK: vshrs32:
+;CHECK-LABEL: vshrs32:
;CHECK: vshr.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
}
define <1 x i64> @vshrs64(<1 x i64>* %A) nounwind {
-;CHECK: vshrs64:
+;CHECK-LABEL: vshrs64:
;CHECK: vshr.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
}
define <8 x i8> @vshru8(<8 x i8>* %A) nounwind {
-;CHECK: vshru8:
+;CHECK-LABEL: vshru8:
;CHECK: vshr.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
}
define <4 x i16> @vshru16(<4 x i16>* %A) nounwind {
-;CHECK: vshru16:
+;CHECK-LABEL: vshru16:
;CHECK: vshr.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
}
define <2 x i32> @vshru32(<2 x i32>* %A) nounwind {
-;CHECK: vshru32:
+;CHECK-LABEL: vshru32:
;CHECK: vshr.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
}
define <1 x i64> @vshru64(<1 x i64>* %A) nounwind {
-;CHECK: vshru64:
+;CHECK-LABEL: vshru64:
;CHECK: vshr.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
}
define <16 x i8> @vshrQs8(<16 x i8>* %A) nounwind {
-;CHECK: vshrQs8:
+;CHECK-LABEL: vshrQs8:
;CHECK: vshr.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
}
define <8 x i16> @vshrQs16(<8 x i16>* %A) nounwind {
-;CHECK: vshrQs16:
+;CHECK-LABEL: vshrQs16:
;CHECK: vshr.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
}
define <4 x i32> @vshrQs32(<4 x i32>* %A) nounwind {
-;CHECK: vshrQs32:
+;CHECK-LABEL: vshrQs32:
;CHECK: vshr.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
}
define <2 x i64> @vshrQs64(<2 x i64>* %A) nounwind {
-;CHECK: vshrQs64:
+;CHECK-LABEL: vshrQs64:
;CHECK: vshr.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
}
define <16 x i8> @vshrQu8(<16 x i8>* %A) nounwind {
-;CHECK: vshrQu8:
+;CHECK-LABEL: vshrQu8:
;CHECK: vshr.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
}
define <8 x i16> @vshrQu16(<8 x i16>* %A) nounwind {
-;CHECK: vshrQu16:
+;CHECK-LABEL: vshrQu16:
;CHECK: vshr.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
}
define <4 x i32> @vshrQu32(<4 x i32>* %A) nounwind {
-;CHECK: vshrQu32:
+;CHECK-LABEL: vshrQu32:
;CHECK: vshr.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
}
define <2 x i64> @vshrQu64(<2 x i64>* %A) nounwind {
-;CHECK: vshrQu64:
+;CHECK-LABEL: vshrQu64:
;CHECK: vshr.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vrshls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrshls8:
+;CHECK-LABEL: vrshls8:
;CHECK: vrshl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vrshls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrshls16:
+;CHECK-LABEL: vrshls16:
;CHECK: vrshl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vrshls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrshls32:
+;CHECK-LABEL: vrshls32:
;CHECK: vrshl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vrshls64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrshls64:
+;CHECK-LABEL: vrshls64:
;CHECK: vrshl.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <8 x i8> @vrshlu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrshlu8:
+;CHECK-LABEL: vrshlu8:
;CHECK: vrshl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vrshlu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrshlu16:
+;CHECK-LABEL: vrshlu16:
;CHECK: vrshl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vrshlu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrshlu32:
+;CHECK-LABEL: vrshlu32:
;CHECK: vrshl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vrshlu64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrshlu64:
+;CHECK-LABEL: vrshlu64:
;CHECK: vrshl.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vrshlQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrshlQs8:
+;CHECK-LABEL: vrshlQs8:
;CHECK: vrshl.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vrshlQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrshlQs16:
+;CHECK-LABEL: vrshlQs16:
;CHECK: vrshl.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vrshlQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrshlQs32:
+;CHECK-LABEL: vrshlQs32:
;CHECK: vrshl.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vrshlQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrshlQs64:
+;CHECK-LABEL: vrshlQs64:
;CHECK: vrshl.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <16 x i8> @vrshlQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrshlQu8:
+;CHECK-LABEL: vrshlQu8:
;CHECK: vrshl.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vrshlQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrshlQu16:
+;CHECK-LABEL: vrshlQu16:
;CHECK: vrshl.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vrshlQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrshlQu32:
+;CHECK-LABEL: vrshlQu32:
;CHECK: vrshl.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vrshlQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrshlQu64:
+;CHECK-LABEL: vrshlQu64:
;CHECK: vrshl.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @vrshrs8(<8 x i8>* %A) nounwind {
-;CHECK: vrshrs8:
+;CHECK-LABEL: vrshrs8:
;CHECK: vrshr.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshifts.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
}
define <4 x i16> @vrshrs16(<4 x i16>* %A) nounwind {
-;CHECK: vrshrs16:
+;CHECK-LABEL: vrshrs16:
;CHECK: vrshr.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshifts.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
}
define <2 x i32> @vrshrs32(<2 x i32>* %A) nounwind {
-;CHECK: vrshrs32:
+;CHECK-LABEL: vrshrs32:
;CHECK: vrshr.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshifts.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
}
define <1 x i64> @vrshrs64(<1 x i64>* %A) nounwind {
-;CHECK: vrshrs64:
+;CHECK-LABEL: vrshrs64:
;CHECK: vrshr.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vrshifts.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
}
define <8 x i8> @vrshru8(<8 x i8>* %A) nounwind {
-;CHECK: vrshru8:
+;CHECK-LABEL: vrshru8:
;CHECK: vrshr.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftu.v8i8(<8 x i8> %tmp1, <8 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
}
define <4 x i16> @vrshru16(<4 x i16>* %A) nounwind {
-;CHECK: vrshru16:
+;CHECK-LABEL: vrshru16:
;CHECK: vrshr.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftu.v4i16(<4 x i16> %tmp1, <4 x i16> < i16 -16, i16 -16, i16 -16, i16 -16 >)
}
define <2 x i32> @vrshru32(<2 x i32>* %A) nounwind {
-;CHECK: vrshru32:
+;CHECK-LABEL: vrshru32:
;CHECK: vrshr.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftu.v2i32(<2 x i32> %tmp1, <2 x i32> < i32 -32, i32 -32 >)
}
define <1 x i64> @vrshru64(<1 x i64>* %A) nounwind {
-;CHECK: vrshru64:
+;CHECK-LABEL: vrshru64:
;CHECK: vrshr.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = call <1 x i64> @llvm.arm.neon.vrshiftu.v1i64(<1 x i64> %tmp1, <1 x i64> < i64 -64 >)
}
define <16 x i8> @vrshrQs8(<16 x i8>* %A) nounwind {
-;CHECK: vrshrQs8:
+;CHECK-LABEL: vrshrQs8:
;CHECK: vrshr.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vrshifts.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
}
define <8 x i16> @vrshrQs16(<8 x i16>* %A) nounwind {
-;CHECK: vrshrQs16:
+;CHECK-LABEL: vrshrQs16:
;CHECK: vrshr.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vrshifts.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
}
define <4 x i32> @vrshrQs32(<4 x i32>* %A) nounwind {
-;CHECK: vrshrQs32:
+;CHECK-LABEL: vrshrQs32:
;CHECK: vrshr.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrshifts.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
}
define <2 x i64> @vrshrQs64(<2 x i64>* %A) nounwind {
-;CHECK: vrshrQs64:
+;CHECK-LABEL: vrshrQs64:
;CHECK: vrshr.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vrshifts.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
}
define <16 x i8> @vrshrQu8(<16 x i8>* %A) nounwind {
-;CHECK: vrshrQu8:
+;CHECK-LABEL: vrshrQu8:
;CHECK: vrshr.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = call <16 x i8> @llvm.arm.neon.vrshiftu.v16i8(<16 x i8> %tmp1, <16 x i8> < i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8, i8 -8 >)
}
define <8 x i16> @vrshrQu16(<8 x i16>* %A) nounwind {
-;CHECK: vrshrQu16:
+;CHECK-LABEL: vrshrQu16:
;CHECK: vrshr.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vrshiftu.v8i16(<8 x i16> %tmp1, <8 x i16> < i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16, i16 -16 >)
}
define <4 x i32> @vrshrQu32(<4 x i32>* %A) nounwind {
-;CHECK: vrshrQu32:
+;CHECK-LABEL: vrshrQu32:
;CHECK: vrshr.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vrshiftu.v4i32(<4 x i32> %tmp1, <4 x i32> < i32 -32, i32 -32, i32 -32, i32 -32 >)
}
define <2 x i64> @vrshrQu64(<2 x i64>* %A) nounwind {
-;CHECK: vrshrQu64:
+;CHECK-LABEL: vrshrQu64:
;CHECK: vrshr.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vrshiftu.v2i64(<2 x i64> %tmp1, <2 x i64> < i64 -64, i64 -64 >)
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i16> @vshlls8(<8 x i8>* %A) nounwind {
-;CHECK: vshlls8:
+;CHECK-LABEL: vshlls8:
;CHECK: vshll.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <4 x i32> @vshlls16(<4 x i16>* %A) nounwind {
-;CHECK: vshlls16:
+;CHECK-LABEL: vshlls16:
;CHECK: vshll.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftls.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
}
define <2 x i64> @vshlls32(<2 x i32>* %A) nounwind {
-;CHECK: vshlls32:
+;CHECK-LABEL: vshlls32:
;CHECK: vshll.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
}
define <8 x i16> @vshllu8(<8 x i8>* %A) nounwind {
-;CHECK: vshllu8:
+;CHECK-LABEL: vshllu8:
;CHECK: vshll.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftlu.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7 >)
}
define <4 x i32> @vshllu16(<4 x i16>* %A) nounwind {
-;CHECK: vshllu16:
+;CHECK-LABEL: vshllu16:
;CHECK: vshll.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 15, i16 15, i16 15, i16 15 >)
}
define <2 x i64> @vshllu32(<2 x i32>* %A) nounwind {
-;CHECK: vshllu32:
+;CHECK-LABEL: vshllu32:
;CHECK: vshll.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftlu.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 31, i32 31 >)
; The following tests use the maximum shift count, so the signedness is
; irrelevant. Test both signed and unsigned versions.
define <8 x i16> @vshlli8(<8 x i8>* %A) nounwind {
-;CHECK: vshlli8:
+;CHECK-LABEL: vshlli8:
;CHECK: vshll.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = call <8 x i16> @llvm.arm.neon.vshiftls.v8i16(<8 x i8> %tmp1, <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >)
}
define <4 x i32> @vshlli16(<4 x i16>* %A) nounwind {
-;CHECK: vshlli16:
+;CHECK-LABEL: vshlli16:
;CHECK: vshll.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = call <4 x i32> @llvm.arm.neon.vshiftlu.v4i32(<4 x i16> %tmp1, <4 x i16> < i16 16, i16 16, i16 16, i16 16 >)
}
define <2 x i64> @vshlli32(<2 x i32>* %A) nounwind {
-;CHECK: vshlli32:
+;CHECK-LABEL: vshlli32:
;CHECK: vshll.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = call <2 x i64> @llvm.arm.neon.vshiftls.v2i64(<2 x i32> %tmp1, <2 x i32> < i32 32, i32 32 >)
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vshrns8:
+;CHECK-LABEL: vshrns8:
;CHECK: vshrn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
}
define <4 x i16> @vshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vshrns16:
+;CHECK-LABEL: vshrns16:
;CHECK: vshrn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
}
define <2 x i32> @vshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vshrns32:
+;CHECK-LABEL: vshrns32:
;CHECK: vshrn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
declare <2 x i32> @llvm.arm.neon.vshiftn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vrshrns8(<8 x i16>* %A) nounwind {
-;CHECK: vrshrns8:
+;CHECK-LABEL: vrshrns8:
;CHECK: vrshrn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = call <8 x i8> @llvm.arm.neon.vrshiftn.v8i8(<8 x i16> %tmp1, <8 x i16> < i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8, i16 -8 >)
}
define <4 x i16> @vrshrns16(<4 x i32>* %A) nounwind {
-;CHECK: vrshrns16:
+;CHECK-LABEL: vrshrns16:
;CHECK: vrshrn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = call <4 x i16> @llvm.arm.neon.vrshiftn.v4i16(<4 x i32> %tmp1, <4 x i32> < i32 -16, i32 -16, i32 -16, i32 -16 >)
}
define <2 x i32> @vrshrns32(<2 x i64>* %A) nounwind {
-;CHECK: vrshrns32:
+;CHECK-LABEL: vrshrns32:
;CHECK: vrshrn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = call <2 x i32> @llvm.arm.neon.vrshiftn.v2i32(<2 x i64> %tmp1, <2 x i64> < i64 -32, i64 -32 >)
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsras8:
+;CHECK-LABEL: vsras8:
;CHECK: vsra.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsras16:
+;CHECK-LABEL: vsras16:
;CHECK: vsra.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsras32:
+;CHECK-LABEL: vsras32:
;CHECK: vsra.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsras64:
+;CHECK-LABEL: vsras64:
;CHECK: vsra.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsraQs8:
+;CHECK-LABEL: vsraQs8:
;CHECK: vsra.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsraQs16:
+;CHECK-LABEL: vsraQs16:
;CHECK: vsra.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsraQs32:
+;CHECK-LABEL: vsraQs32:
;CHECK: vsra.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsraQs64:
+;CHECK-LABEL: vsraQs64:
;CHECK: vsra.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @vsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsrau8:
+;CHECK-LABEL: vsrau8:
;CHECK: vsra.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsrau16:
+;CHECK-LABEL: vsrau16:
;CHECK: vsra.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsrau32:
+;CHECK-LABEL: vsrau32:
;CHECK: vsra.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsrau64:
+;CHECK-LABEL: vsrau64:
;CHECK: vsra.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsraQu8:
+;CHECK-LABEL: vsraQu8:
;CHECK: vsra.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsraQu16:
+;CHECK-LABEL: vsraQu16:
;CHECK: vsra.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsraQu32:
+;CHECK-LABEL: vsraQu32:
;CHECK: vsra.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsraQu64:
+;CHECK-LABEL: vsraQu64:
;CHECK: vsra.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <8 x i8> @vrsras8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrsras8:
+;CHECK-LABEL: vrsras8:
;CHECK: vrsra.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vrsras16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrsras16:
+;CHECK-LABEL: vrsras16:
;CHECK: vrsra.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vrsras32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrsras32:
+;CHECK-LABEL: vrsras32:
;CHECK: vrsra.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vrsras64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrsras64:
+;CHECK-LABEL: vrsras64:
;CHECK: vrsra.s64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <8 x i8> @vrsrau8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vrsrau8:
+;CHECK-LABEL: vrsrau8:
;CHECK: vrsra.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vrsrau16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vrsrau16:
+;CHECK-LABEL: vrsrau16:
;CHECK: vrsra.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vrsrau32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vrsrau32:
+;CHECK-LABEL: vrsrau32:
;CHECK: vrsra.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vrsrau64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vrsrau64:
+;CHECK-LABEL: vrsrau64:
;CHECK: vrsra.u64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <16 x i8> @vrsraQs8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrsraQs8:
+;CHECK-LABEL: vrsraQs8:
;CHECK: vrsra.s8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vrsraQs16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsraQs16:
+;CHECK-LABEL: vrsraQs16:
;CHECK: vrsra.s16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vrsraQs32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsraQs32:
+;CHECK-LABEL: vrsraQs32:
;CHECK: vrsra.s32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vrsraQs64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsraQs64:
+;CHECK-LABEL: vrsraQs64:
;CHECK: vrsra.s64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <16 x i8> @vrsraQu8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vrsraQu8:
+;CHECK-LABEL: vrsraQu8:
;CHECK: vrsra.u8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vrsraQu16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsraQu16:
+;CHECK-LABEL: vrsraQu16:
;CHECK: vrsra.u16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vrsraQu32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsraQu32:
+;CHECK-LABEL: vrsraQu32:
;CHECK: vrsra.u32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vrsraQu64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsraQu64:
+;CHECK-LABEL: vrsraQu64:
;CHECK: vrsra.u64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst1i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst1i8:
+;CHECK-LABEL: vst1i8:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vst1.8 {d16}, [r0:64]
%tmp1 = load <8 x i8>* %B
}
define void @vst1i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst1i16:
+;CHECK-LABEL: vst1i16:
;CHECK: vst1.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = load <4 x i16>* %B
}
define void @vst1i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst1i32:
+;CHECK-LABEL: vst1i32:
;CHECK: vst1.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
}
define void @vst1f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst1f:
+;CHECK-LABEL: vst1f:
;CHECK: vst1.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
;Check for a post-increment updating store.
define void @vst1f_update(float** %ptr, <2 x float>* %B) nounwind {
-;CHECK: vst1f_update:
+;CHECK-LABEL: vst1f_update:
;CHECK: vst1.32 {d16}, [r1]!
%A = load float** %ptr
%tmp0 = bitcast float* %A to i8*
}
define void @vst1i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst1i64:
+;CHECK-LABEL: vst1i64:
;CHECK: vst1.64
%tmp0 = bitcast i64* %A to i8*
%tmp1 = load <1 x i64>* %B
}
define void @vst1Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst1Qi8:
+;CHECK-LABEL: vst1Qi8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.8 {d16, d17}, [r0:64]
%tmp1 = load <16 x i8>* %B
}
define void @vst1Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst1Qi16:
+;CHECK-LABEL: vst1Qi16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
;Check for a post-increment updating store with register increment.
define void @vst1Qi16_update(i16** %ptr, <8 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vst1Qi16_update:
+;CHECK-LABEL: vst1Qi16_update:
;CHECK: vst1.16 {d16, d17}, [r1:64], r2
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
}
define void @vst1Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst1Qi32:
+;CHECK-LABEL: vst1Qi32:
;CHECK: vst1.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <4 x i32>* %B
}
define void @vst1Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst1Qf:
+;CHECK-LABEL: vst1Qf:
;CHECK: vst1.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
}
define void @vst1Qi64(i64* %A, <2 x i64>* %B) nounwind {
-;CHECK: vst1Qi64:
+;CHECK-LABEL: vst1Qi64:
;CHECK: vst1.64
%tmp0 = bitcast i64* %A to i8*
%tmp1 = load <2 x i64>* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst2i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst2i8:
+;CHECK-LABEL: vst2i8:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst2.8 {d16, d17}, [r0:64]
%tmp1 = load <8 x i8>* %B
;Check for a post-increment updating store with register increment.
define void @vst2i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
-;CHECK: vst2i8_update:
+;CHECK-LABEL: vst2i8_update:
;CHECK: vst2.8 {d16, d17}, [r1], r2
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
}
define void @vst2i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst2i16:
+;CHECK-LABEL: vst2i16:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst2.16 {d16, d17}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
}
define void @vst2i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst2i32:
+;CHECK-LABEL: vst2i32:
;CHECK: vst2.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
}
define void @vst2f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst2f:
+;CHECK-LABEL: vst2f:
;CHECK: vst2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define void @vst2i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst2i64:
+;CHECK-LABEL: vst2i64:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst1.64 {d16, d17}, [r0:128]
%tmp0 = bitcast i64* %A to i8*
;Check for a post-increment updating store.
define void @vst2i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
-;CHECK: vst2i64_update:
+;CHECK-LABEL: vst2i64_update:
;CHECK: vst1.64 {d16, d17}, [r1:64]!
%A = load i64** %ptr
%tmp0 = bitcast i64* %A to i8*
}
define void @vst2Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst2Qi8:
+;CHECK-LABEL: vst2Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = load <16 x i8>* %B
}
define void @vst2Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst2Qi16:
+;CHECK-LABEL: vst2Qi16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
}
define void @vst2Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst2Qi32:
+;CHECK-LABEL: vst2Qi32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst2.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
}
define void @vst2Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst2Qf:
+;CHECK-LABEL: vst2Qf:
;CHECK: vst2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
; RUN: llc < %s -march=arm -mattr=+neon -fast-isel=0 -O0 | FileCheck %s
define void @vst3i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst3i8:
+;CHECK-LABEL: vst3i8:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
}
define void @vst3i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst3i16:
+;CHECK-LABEL: vst3i16:
;CHECK: vst3.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = load <4 x i16>* %B
}
define void @vst3i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst3i32:
+;CHECK-LABEL: vst3i32:
;CHECK: vst3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
;Check for a post-increment updating store.
define void @vst3i32_update(i32** %ptr, <2 x i32>* %B) nounwind {
-;CHECK: vst3i32_update:
+;CHECK-LABEL: vst3i32_update:
;CHECK: vst3.32 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
}
define void @vst3f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst3f:
+;CHECK-LABEL: vst3f:
;CHECK: vst3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define void @vst3i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst3i64:
+;CHECK-LABEL: vst3i64:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst1.64 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]
}
define void @vst3Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst3Qi8:
+;CHECK-LABEL: vst3Qi8:
;Check the alignment value. Max for this instruction is 64 bits:
;This test runs at -O0 so do not check for specific register numbers.
;CHECK: vst3.8 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}:64]!
}
define void @vst3Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst3Qi16:
+;CHECK-LABEL: vst3Qi16:
;CHECK: vst3.16
;CHECK: vst3.16
%tmp0 = bitcast i16* %A to i8*
;Check for a post-increment updating store.
define void @vst3Qi16_update(i16** %ptr, <8 x i16>* %B) nounwind {
-;CHECK: vst3Qi16_update:
+;CHECK-LABEL: vst3Qi16_update:
;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
;CHECK: vst3.16 {d{{.*}}, d{{.*}}, d{{.*}}}, [r{{.*}}]!
%A = load i16** %ptr
}
define void @vst3Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst3Qi32:
+;CHECK-LABEL: vst3Qi32:
;CHECK: vst3.32
;CHECK: vst3.32
%tmp0 = bitcast i32* %A to i8*
}
define void @vst3Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst3Qf:
+;CHECK-LABEL: vst3Qf:
;CHECK: vst3.32
;CHECK: vst3.32
%tmp0 = bitcast float* %A to i8*
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst4i8:
+;CHECK-LABEL: vst4i8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
%tmp1 = load <8 x i8>* %B
;Check for a post-increment updating store with register increment.
define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
-;CHECK: vst4i8_update:
+;CHECK-LABEL: vst4i8_update:
;CHECK: vst4.8 {d16, d17, d18, d19}, [r1:128], r2
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
}
define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst4i16:
+;CHECK-LABEL: vst4i16:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
%tmp0 = bitcast i16* %A to i8*
}
define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst4i32:
+;CHECK-LABEL: vst4i32:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i32* %A to i8*
}
define void @vst4f(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst4f:
+;CHECK-LABEL: vst4f:
;CHECK: vst4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
-;CHECK: vst4i64:
+;CHECK-LABEL: vst4i64:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256]
%tmp0 = bitcast i64* %A to i8*
}
define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst4Qi8:
+;CHECK-LABEL: vst4Qi8:
;Check the alignment value. Max for this instruction is 256 bits:
;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]
}
define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst4Qi16:
+;CHECK-LABEL: vst4Qi16:
;Check for no alignment specifier.
;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
;CHECK: vst4.16 {d17, d19, d21, d23}, [r0]
}
define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst4Qi32:
+;CHECK-LABEL: vst4Qi32:
;CHECK: vst4.32
;CHECK: vst4.32
%tmp0 = bitcast i32* %A to i8*
}
define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst4Qf:
+;CHECK-LABEL: vst4Qf:
;CHECK: vst4.32
;CHECK: vst4.32
%tmp0 = bitcast float* %A to i8*
;Check for a post-increment updating store.
define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind {
-;CHECK: vst4Qf_update:
+;CHECK-LABEL: vst4Qf_update:
;CHECK: vst4.32 {d16, d18, d20, d22}, [r1]!
;CHECK: vst4.32 {d17, d19, d21, d23}, [r1]!
%A = load float** %ptr
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define void @vst1lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst1lanei8:
+;CHECK-LABEL: vst1lanei8:
;Check the (default) alignment.
;CHECK: vst1.8 {d16[3]}, [r0]
%tmp1 = load <8 x i8>* %B
;Check for a post-increment updating store.
define void @vst1lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vst1lanei8_update:
+;CHECK-LABEL: vst1lanei8_update:
;CHECK: vst1.8 {d16[3]}, [r2]!
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
}
define void @vst1lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst1lanei16:
+;CHECK-LABEL: vst1lanei16:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vst1.16 {d16[2]}, [r0:16]
%tmp1 = load <4 x i16>* %B
}
define void @vst1lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst1lanei32:
+;CHECK-LABEL: vst1lanei32:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vst1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x i32>* %B
}
define void @vst1lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst1lanef:
+;CHECK-LABEL: vst1lanef:
;CHECK: vst1.32 {d16[1]}, [r0:32]
%tmp1 = load <2 x float>* %B
%tmp2 = extractelement <2 x float> %tmp1, i32 1
}
define void @vst1laneQi8(i8* %A, <16 x i8>* %B) nounwind {
-;CHECK: vst1laneQi8:
+;CHECK-LABEL: vst1laneQi8:
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.8 {d17[1]}, [r0]
%tmp1 = load <16 x i8>* %B
}
define void @vst1laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst1laneQi16:
+;CHECK-LABEL: vst1laneQi16:
;CHECK: vst1.16 {d17[1]}, [r0:16]
%tmp1 = load <8 x i16>* %B
%tmp2 = extractelement <8 x i16> %tmp1, i32 5
}
define void @vst1laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst1laneQi32:
+;CHECK-LABEL: vst1laneQi32:
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r0:32]
%tmp1 = load <4 x i32>* %B
;Check for a post-increment updating store.
define void @vst1laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
-;CHECK: vst1laneQi32_update:
+;CHECK-LABEL: vst1laneQi32_update:
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r1:32]!
%A = load i32** %ptr
}
define void @vst1laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst1laneQf:
+;CHECK-LABEL: vst1laneQf:
; // Can use scalar load. No need to use vectors.
; // CHE-CK: vst1.32 {d17[1]}, [r0]
%tmp1 = load <4 x float>* %B
}
define void @vst2lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst2lanei8:
+;CHECK-LABEL: vst2lanei8:
;Check the alignment value. Max for this instruction is 16 bits:
;CHECK: vst2.8 {d16[1], d17[1]}, [r0:16]
%tmp1 = load <8 x i8>* %B
}
define void @vst2lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst2lanei16:
+;CHECK-LABEL: vst2lanei16:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vst2.16 {d16[1], d17[1]}, [r0:32]
%tmp0 = bitcast i16* %A to i8*
;Check for a post-increment updating store with register increment.
define void @vst2lanei16_update(i16** %ptr, <4 x i16>* %B, i32 %inc) nounwind {
-;CHECK: vst2lanei16_update:
+;CHECK-LABEL: vst2lanei16_update:
;CHECK: vst2.16 {d16[1], d17[1]}, [r1], r2
%A = load i16** %ptr
%tmp0 = bitcast i16* %A to i8*
}
define void @vst2lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst2lanei32:
+;CHECK-LABEL: vst2lanei32:
;CHECK: vst2.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
}
define void @vst2lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst2lanef:
+;CHECK-LABEL: vst2lanef:
;CHECK: vst2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define void @vst2laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst2laneQi16:
+;CHECK-LABEL: vst2laneQi16:
;Check the (default) alignment.
;CHECK: vst2.16 {d17[1], d19[1]}, [r0]
%tmp0 = bitcast i16* %A to i8*
}
define void @vst2laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst2laneQi32:
+;CHECK-LABEL: vst2laneQi32:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vst2.32 {d17[0], d19[0]}, [r0:64]
%tmp0 = bitcast i32* %A to i8*
}
define void @vst2laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst2laneQf:
+;CHECK-LABEL: vst2laneQf:
;CHECK: vst2.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
declare void @llvm.arm.neon.vst2lane.v4f32(i8*, <4 x float>, <4 x float>, i32, i32) nounwind
define void @vst3lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst3lanei8:
+;CHECK-LABEL: vst3lanei8:
;CHECK: vst3.8
%tmp1 = load <8 x i8>* %B
call void @llvm.arm.neon.vst3lane.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 1, i32 1)
}
define void @vst3lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst3lanei16:
+;CHECK-LABEL: vst3lanei16:
;Check the (default) alignment value. VST3 does not support alignment.
;CHECK: vst3.16 {d16[1], d17[1], d18[1]}, [r0]
%tmp0 = bitcast i16* %A to i8*
}
define void @vst3lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst3lanei32:
+;CHECK-LABEL: vst3lanei32:
;CHECK: vst3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <2 x i32>* %B
}
define void @vst3lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst3lanef:
+;CHECK-LABEL: vst3lanef:
;CHECK: vst3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define void @vst3laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst3laneQi16:
+;CHECK-LABEL: vst3laneQi16:
;Check the (default) alignment value. VST3 does not support alignment.
;CHECK: vst3.16 {d17[2], d19[2], d21[2]}, [r0]
%tmp0 = bitcast i16* %A to i8*
}
define void @vst3laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst3laneQi32:
+;CHECK-LABEL: vst3laneQi32:
;CHECK: vst3.32
%tmp0 = bitcast i32* %A to i8*
%tmp1 = load <4 x i32>* %B
;Check for a post-increment updating store.
define void @vst3laneQi32_update(i32** %ptr, <4 x i32>* %B) nounwind {
-;CHECK: vst3laneQi32_update:
+;CHECK-LABEL: vst3laneQi32_update:
;CHECK: vst3.32 {d16[0], d18[0], d20[0]}, [r1]!
%A = load i32** %ptr
%tmp0 = bitcast i32* %A to i8*
}
define void @vst3laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst3laneQf:
+;CHECK-LABEL: vst3laneQf:
;CHECK: vst3.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
define void @vst4lanei8(i8* %A, <8 x i8>* %B) nounwind {
-;CHECK: vst4lanei8:
+;CHECK-LABEL: vst4lanei8:
;Check the alignment value. Max for this instruction is 32 bits:
;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r0:32]
%tmp1 = load <8 x i8>* %B
;Check for a post-increment updating store.
define void @vst4lanei8_update(i8** %ptr, <8 x i8>* %B) nounwind {
-;CHECK: vst4lanei8_update:
+;CHECK-LABEL: vst4lanei8_update:
;CHECK: vst4.8 {d16[1], d17[1], d18[1], d19[1]}, [r1:32]!
%A = load i8** %ptr
%tmp1 = load <8 x i8>* %B
}
define void @vst4lanei16(i16* %A, <4 x i16>* %B) nounwind {
-;CHECK: vst4lanei16:
+;CHECK-LABEL: vst4lanei16:
;CHECK: vst4.16
%tmp0 = bitcast i16* %A to i8*
%tmp1 = load <4 x i16>* %B
}
define void @vst4lanei32(i32* %A, <2 x i32>* %B) nounwind {
-;CHECK: vst4lanei32:
+;CHECK-LABEL: vst4lanei32:
;Check the alignment value. Max for this instruction is 128 bits:
;CHECK: vst4.32 {d16[1], d17[1], d18[1], d19[1]}, [r0:128]
%tmp0 = bitcast i32* %A to i8*
}
define void @vst4lanef(float* %A, <2 x float>* %B) nounwind {
-;CHECK: vst4lanef:
+;CHECK-LABEL: vst4lanef:
;CHECK: vst4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <2 x float>* %B
}
define void @vst4laneQi16(i16* %A, <8 x i16>* %B) nounwind {
-;CHECK: vst4laneQi16:
+;CHECK-LABEL: vst4laneQi16:
;Check the alignment value. Max for this instruction is 64 bits:
;CHECK: vst4.16 {d17[3], d19[3], d21[3], d23[3]}, [r0:64]
%tmp0 = bitcast i16* %A to i8*
}
define void @vst4laneQi32(i32* %A, <4 x i32>* %B) nounwind {
-;CHECK: vst4laneQi32:
+;CHECK-LABEL: vst4laneQi32:
;Check the (default) alignment.
;CHECK: vst4.32 {d17[0], d19[0], d21[0], d23[0]}, [r0]
%tmp0 = bitcast i32* %A to i8*
}
define void @vst4laneQf(float* %A, <4 x float>* %B) nounwind {
-;CHECK: vst4laneQf:
+;CHECK-LABEL: vst4laneQf:
;CHECK: vst4.32
%tmp0 = bitcast float* %A to i8*
%tmp1 = load <4 x float>* %B
; Make sure this doesn't crash; PR10258
define <8 x i16> @variable_insertelement(<8 x i16> %a, i16 %b, i32 %c) nounwind readnone {
-;CHECK: variable_insertelement:
+;CHECK-LABEL: variable_insertelement:
%r = insertelement <8 x i16> %a, i16 %b, i32 %c
ret <8 x i16> %r
}
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vsubi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubi8:
+;CHECK-LABEL: vsubi8:
;CHECK: vsub.i8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i16> @vsubi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubi16:
+;CHECK-LABEL: vsubi16:
;CHECK: vsub.i16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i32> @vsubi32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubi32:
+;CHECK-LABEL: vsubi32:
;CHECK: vsub.i32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <1 x i64> @vsubi64(<1 x i64>* %A, <1 x i64>* %B) nounwind {
-;CHECK: vsubi64:
+;CHECK-LABEL: vsubi64:
;CHECK: vsub.i64
%tmp1 = load <1 x i64>* %A
%tmp2 = load <1 x i64>* %B
}
define <2 x float> @vsubf32(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vsubf32:
+;CHECK-LABEL: vsubf32:
;CHECK: vsub.f32
%tmp1 = load <2 x float>* %A
%tmp2 = load <2 x float>* %B
}
define <16 x i8> @vsubQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vsubQi8:
+;CHECK-LABEL: vsubQi8:
;CHECK: vsub.i8
%tmp1 = load <16 x i8>* %A
%tmp2 = load <16 x i8>* %B
}
define <8 x i16> @vsubQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsubQi16:
+;CHECK-LABEL: vsubQi16:
;CHECK: vsub.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i32> @vsubQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsubQi32:
+;CHECK-LABEL: vsubQi32:
;CHECK: vsub.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i64> @vsubQi64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsubQi64:
+;CHECK-LABEL: vsubQi64:
;CHECK: vsub.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
}
define <4 x float> @vsubQf32(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vsubQf32:
+;CHECK-LABEL: vsubQf32:
;CHECK: vsub.f32
%tmp1 = load <4 x float>* %A
%tmp2 = load <4 x float>* %B
}
define <8 x i8> @vsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vsubhni16:
+;CHECK-LABEL: vsubhni16:
;CHECK: vsubhn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i16> @vsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vsubhni32:
+;CHECK-LABEL: vsubhni32:
;CHECK: vsubhn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i32> @vsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vsubhni64:
+;CHECK-LABEL: vsubhni64:
;CHECK: vsubhn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
declare <2 x i32> @llvm.arm.neon.vsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i8> @vrsubhni16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vrsubhni16:
+;CHECK-LABEL: vrsubhni16:
;CHECK: vrsubhn.i16
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i16>* %B
}
define <4 x i16> @vrsubhni32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vrsubhni32:
+;CHECK-LABEL: vrsubhni32:
;CHECK: vrsubhn.i32
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i32>* %B
}
define <2 x i32> @vrsubhni64(<2 x i64>* %A, <2 x i64>* %B) nounwind {
-;CHECK: vrsubhni64:
+;CHECK-LABEL: vrsubhni64:
;CHECK: vrsubhn.i64
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i64>* %B
declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
define <8 x i16> @vsubls8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubls8:
+;CHECK-LABEL: vsubls8:
;CHECK: vsubl.s8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vsubls16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubls16:
+;CHECK-LABEL: vsubls16:
;CHECK: vsubl.s16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vsubls32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubls32:
+;CHECK-LABEL: vsubls32:
;CHECK: vsubl.s32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vsublu8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsublu8:
+;CHECK-LABEL: vsublu8:
;CHECK: vsubl.u8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vsublu16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsublu16:
+;CHECK-LABEL: vsublu16:
;CHECK: vsubl.u16
%tmp1 = load <4 x i16>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vsublu32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsublu32:
+;CHECK-LABEL: vsublu32:
;CHECK: vsubl.u32
%tmp1 = load <2 x i32>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vsubws8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubws8:
+;CHECK-LABEL: vsubws8:
;CHECK: vsubw.s8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vsubws16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubws16:
+;CHECK-LABEL: vsubws16:
;CHECK: vsubw.s16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vsubws32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubws32:
+;CHECK-LABEL: vsubws32:
;CHECK: vsubw.s32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
}
define <8 x i16> @vsubwu8(<8 x i16>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vsubwu8:
+;CHECK-LABEL: vsubwu8:
;CHECK: vsubw.u8
%tmp1 = load <8 x i16>* %A
%tmp2 = load <8 x i8>* %B
}
define <4 x i32> @vsubwu16(<4 x i32>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vsubwu16:
+;CHECK-LABEL: vsubwu16:
;CHECK: vsubw.u16
%tmp1 = load <4 x i32>* %A
%tmp2 = load <4 x i16>* %B
}
define <2 x i64> @vsubwu32(<2 x i64>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vsubwu32:
+;CHECK-LABEL: vsubwu32:
;CHECK: vsubw.u32
%tmp1 = load <2 x i64>* %A
%tmp2 = load <2 x i32>* %B
%struct.__neon_int8x8x4_t = type { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> }
define <8 x i8> @vtbl1(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtbl1:
+;CHECK-LABEL: vtbl1:
;CHECK: vtbl.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <8 x i8> @vtbl2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B) nounwind {
-;CHECK: vtbl2:
+;CHECK-LABEL: vtbl2:
;CHECK: vtbl.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x2_t* %B
}
define <8 x i8> @vtbl3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B) nounwind {
-;CHECK: vtbl3:
+;CHECK-LABEL: vtbl3:
;CHECK: vtbl.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x3_t* %B
}
define <8 x i8> @vtbl4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B) nounwind {
-;CHECK: vtbl4:
+;CHECK-LABEL: vtbl4:
;CHECK: vtbl.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x4_t* %B
}
define <8 x i8> @vtbx1(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx1:
+;CHECK-LABEL: vtbx1:
;CHECK: vtbx.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load <8 x i8>* %B
}
define <8 x i8> @vtbx2(<8 x i8>* %A, %struct.__neon_int8x8x2_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx2:
+;CHECK-LABEL: vtbx2:
;CHECK: vtbx.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x2_t* %B
}
define <8 x i8> @vtbx3(<8 x i8>* %A, %struct.__neon_int8x8x3_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx3:
+;CHECK-LABEL: vtbx3:
;CHECK: vtbx.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x3_t* %B
}
define <8 x i8> @vtbx4(<8 x i8>* %A, %struct.__neon_int8x8x4_t* %B, <8 x i8>* %C) nounwind {
-;CHECK: vtbx4:
+;CHECK-LABEL: vtbx4:
;CHECK: vtbx.8
%tmp1 = load <8 x i8>* %A
%tmp2 = load %struct.__neon_int8x8x4_t* %B
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vtrni8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8:
+;CHECK-LABEL: vtrni8:
;CHECK: vtrn.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
}
define <4 x i16> @vtrni16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vtrni16:
+;CHECK-LABEL: vtrni16:
;CHECK: vtrn.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <4 x i16>* %A
}
define <2 x i32> @vtrni32(<2 x i32>* %A, <2 x i32>* %B) nounwind {
-;CHECK: vtrni32:
+;CHECK-LABEL: vtrni32:
;CHECK: vtrn.32
;CHECK-NEXT: vadd.i32
%tmp1 = load <2 x i32>* %A
}
define <2 x float> @vtrnf(<2 x float>* %A, <2 x float>* %B) nounwind {
-;CHECK: vtrnf:
+;CHECK-LABEL: vtrnf:
;CHECK: vtrn.32
;CHECK-NEXT: vadd.f32
%tmp1 = load <2 x float>* %A
}
define <16 x i8> @vtrnQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vtrnQi8:
+;CHECK-LABEL: vtrnQi8:
;CHECK: vtrn.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
}
define <8 x i16> @vtrnQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16:
+;CHECK-LABEL: vtrnQi16:
;CHECK: vtrn.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
}
define <4 x i32> @vtrnQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vtrnQi32:
+;CHECK-LABEL: vtrnQi32:
;CHECK: vtrn.32
;CHECK-NEXT: vadd.i32
%tmp1 = load <4 x i32>* %A
}
define <4 x float> @vtrnQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vtrnQf:
+;CHECK-LABEL: vtrnQf:
;CHECK: vtrn.32
;CHECK-NEXT: vadd.f32
%tmp1 = load <4 x float>* %A
; Undef shuffle indices should not prevent matching to VTRN:
define <8 x i8> @vtrni8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vtrni8_undef:
+;CHECK-LABEL: vtrni8_undef:
;CHECK: vtrn.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
}
define <8 x i16> @vtrnQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vtrnQi16_undef:
+;CHECK-LABEL: vtrnQi16_undef:
;CHECK: vtrn.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vuzpi8:
+;CHECK-LABEL: vuzpi8:
;CHECK: vuzp.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
}
define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vuzpi16:
+;CHECK-LABEL: vuzpi16:
;CHECK: vuzp.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <4 x i16>* %A
; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vuzpQi8:
+;CHECK-LABEL: vuzpQi8:
;CHECK: vuzp.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
}
define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vuzpQi16:
+;CHECK-LABEL: vuzpQi16:
;CHECK: vuzp.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
}
define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vuzpQi32:
+;CHECK-LABEL: vuzpQi32:
;CHECK: vuzp.32
;CHECK-NEXT: vadd.i32
%tmp1 = load <4 x i32>* %A
}
define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vuzpQf:
+;CHECK-LABEL: vuzpQf:
;CHECK: vuzp.32
;CHECK-NEXT: vadd.f32
%tmp1 = load <4 x float>* %A
; Undef shuffle indices should not prevent matching to VUZP:
define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vuzpi8_undef:
+;CHECK-LABEL: vuzpi8_undef:
;CHECK: vuzp.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
}
define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vuzpQi16_undef:
+;CHECK-LABEL: vuzpQi16_undef:
;CHECK: vuzp.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
define <8 x i8> @vzipi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vzipi8:
+;CHECK-LABEL: vzipi8:
;CHECK: vzip.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
}
define <4 x i16> @vzipi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: vzipi16:
+;CHECK-LABEL: vzipi16:
;CHECK: vzip.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <4 x i16>* %A
; VZIP.32 is equivalent to VTRN.32 for 64-bit vectors.
define <16 x i8> @vzipQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vzipQi8:
+;CHECK-LABEL: vzipQi8:
;CHECK: vzip.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
}
define <8 x i16> @vzipQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: vzipQi16:
+;CHECK-LABEL: vzipQi16:
;CHECK: vzip.16
;CHECK-NEXT: vadd.i16
%tmp1 = load <8 x i16>* %A
}
define <4 x i32> @vzipQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: vzipQi32:
+;CHECK-LABEL: vzipQi32:
;CHECK: vzip.32
;CHECK-NEXT: vadd.i32
%tmp1 = load <4 x i32>* %A
}
define <4 x float> @vzipQf(<4 x float>* %A, <4 x float>* %B) nounwind {
-;CHECK: vzipQf:
+;CHECK-LABEL: vzipQf:
;CHECK: vzip.32
;CHECK-NEXT: vadd.f32
%tmp1 = load <4 x float>* %A
; Undef shuffle indices should not prevent matching to VZIP:
define <8 x i8> @vzipi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: vzipi8_undef:
+;CHECK-LABEL: vzipi8_undef:
;CHECK: vzip.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <8 x i8>* %A
}
define <16 x i8> @vzipQi8_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: vzipQi8_undef:
+;CHECK-LABEL: vzipQi8_undef:
;CHECK: vzip.8
;CHECK-NEXT: vadd.i8
%tmp1 = load <16 x i8>* %A
define i32 @brind(i32 %a, i32 %b)
{
- ; CHECK: brind:
+ ; CHECK-LABEL: brind:
entry:
br label %loop
define i32 @doadd(i32 %a, i32 %b)
{
- ; CHECK: doadd:
+ ; CHECK-LABEL: doadd:
%tmp.0 = add i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
define i32 @dosub(i32 %a, i32 %b)
{
- ; CHECK: dosub:
+ ; CHECK-LABEL: dosub:
%tmp.0 = sub i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
define i32 @domul(i32 %a, i32 %b)
{
- ; CHECK: domul:
+ ; CHECK-LABEL: domul:
%tmp.0 = mul i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
define i32 @dodiv(i32 %a, i32 %b)
{
- ; CHECK: dodiv:
+ ; CHECK-LABEL: dodiv:
%tmp.0 = sdiv i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
define i32 @dorem(i32 %a, i32 %b)
{
- ; CHECK: dorem:
+ ; CHECK-LABEL: dorem:
%tmp.0 = srem i32 %a, %b
ret i32 %tmp.0
; CHECK: rtsd
define i32 @callind(i32 %a, i32 %b)
{
- ; CHECK: callind:
+ ; CHECK-LABEL: callind:
entry:
br label %loop
@MSG = internal constant [13 x i8] c"Message: %d\0A\00"
define void @params0_noret() {
- ; CHECK: params0_noret:
+ ; CHECK-LABEL: params0_noret:
ret void
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
}
define i8 @params0_8bitret() {
- ; CHECK: params0_8bitret:
+ ; CHECK-LABEL: params0_8bitret:
ret i8 1
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
}
define i16 @params0_16bitret() {
- ; CHECK: params0_16bitret:
+ ; CHECK-LABEL: params0_16bitret:
ret i16 1
; CHECK: rtsd
; CHECK: {{.* r3, r0, 1}}
}
define i32 @params0_32bitret() {
- ; CHECK: params0_32bitret:
+ ; CHECK-LABEL: params0_32bitret:
ret i32 1
; CHECK-NOT: {{.* r4, .*, .*}}
; CHECK: rtsd
}
define i64 @params0_64bitret() {
- ; CHECK: params0_64bitret:
+ ; CHECK-LABEL: params0_64bitret:
ret i64 1
; CHECK: {{.* r3, r0, .*}}
; CHECK: rtsd
}
define i32 @params1_32bitret(i32 %a) {
- ; CHECK: params1_32bitret:
+ ; CHECK-LABEL: params1_32bitret:
ret i32 %a
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
}
define i32 @params2_32bitret(i32 %a, i32 %b) {
- ; CHECK: params2_32bitret:
+ ; CHECK-LABEL: params2_32bitret:
ret i32 %b
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
}
define i32 @params3_32bitret(i32 %a, i32 %b, i32 %c) {
- ; CHECK: params3_32bitret:
+ ; CHECK-LABEL: params3_32bitret:
ret i32 %c
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
}
define i32 @params4_32bitret(i32 %a, i32 %b, i32 %c, i32 %d) {
- ; CHECK: params4_32bitret:
+ ; CHECK-LABEL: params4_32bitret:
ret i32 %d
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
}
define i32 @params5_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {
- ; CHECK: params5_32bitret:
+ ; CHECK-LABEL: params5_32bitret:
ret i32 %e
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
}
define i32 @params6_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
- ; CHECK: params6_32bitret:
+ ; CHECK-LABEL: params6_32bitret:
ret i32 %f
; CHECK-NOT: {{.* r3, .*, .*}}
; CHECK-NOT: {{.* r4, .*, .*}}
define i32 @params7_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g) {
- ; CHECK: params7_32bitret:
+ ; CHECK-LABEL: params7_32bitret:
ret i32 %g
; CHECK: {{lwi? r3, r1, 32}}
; CHECK-NOT: {{.* r4, .*, .*}}
define i32 @params8_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h) {
- ; CHECK: params8_32bitret:
+ ; CHECK-LABEL: params8_32bitret:
ret i32 %h
; CHECK: {{lwi? r3, r1, 36}}
; CHECK-NOT: {{.* r4, .*, .*}}
define i32 @params9_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h, i32 %i) {
- ; CHECK: params9_32bitret:
+ ; CHECK-LABEL: params9_32bitret:
ret i32 %i
; CHECK: {{lwi? r3, r1, 40}}
; CHECK-NOT: {{.* r4, .*, .*}}
define i32 @params10_32bitret(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f,
i32 %g, i32 %h, i32 %i, i32 %j) {
- ; CHECK: params10_32bitret:
+ ; CHECK-LABEL: params10_32bitret:
ret i32 %j
; CHECK: {{lwi? r3, r1, 44}}
; CHECK-NOT: {{.* r4, .*, .*}}
; RUN: llc < %s -march=mblaze -mattr=+div | FileCheck -check-prefix=DIV %s
define i8 @test_i8(i8 %a, i8 %b) {
- ; FUN: test_i8:
- ; DIV: test_i8:
+ ; FUN-LABEL: test_i8:
+ ; DIV-LABEL: test_i8:
%tmp.1 = udiv i8 %a, %b
; FUN-NOT: idiv
}
define i16 @test_i16(i16 %a, i16 %b) {
- ; FUN: test_i16:
- ; DIV: test_i16:
+ ; FUN-LABEL: test_i16:
+ ; DIV-LABEL: test_i16:
%tmp.1 = udiv i16 %a, %b
; FUN-NOT: idiv
}
define i32 @test_i32(i32 %a, i32 %b) {
- ; FUN: test_i32:
- ; DIV: test_i32:
+ ; FUN-LABEL: test_i32:
+ ; DIV-LABEL: test_i32:
%tmp.1 = udiv i32 %a, %b
; FUN-NOT: idiv
; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
define float @test_add(float %a, float %b) {
- ; FUN: test_add:
- ; FPU: test_add:
+ ; FUN-LABEL: test_add:
+ ; FPU-LABEL: test_add:
%tmp.1 = fadd float %a, %b
; FUN: brlid
}
define float @test_sub(float %a, float %b) {
- ; FUN: test_sub:
- ; FPU: test_sub:
+ ; FUN-LABEL: test_sub:
+ ; FPU-LABEL: test_sub:
%tmp.1 = fsub float %a, %b
; FUN: brlid
}
define float @test_mul(float %a, float %b) {
- ; FUN: test_mul:
- ; FPU: test_mul:
+ ; FUN-LABEL: test_mul:
+ ; FPU-LABEL: test_mul:
%tmp.1 = fmul float %a, %b
; FUN: brlid
}
define float @test_div(float %a, float %b) {
- ; FUN: test_div:
- ; FPU: test_div:
+ ; FUN-LABEL: test_div:
+ ; FPU-LABEL: test_div:
%tmp.1 = fdiv float %a, %b
; FUN: brlid
declare void @llvm.mblaze.fsl.tncaput(i32 %port)
define void @fsl_get(i32 %port) {
- ; CHECK: fsl_get:
+ ; CHECK-LABEL: fsl_get:
%v0 = call i32 @llvm.mblaze.fsl.get(i32 %port)
; CHECK: getd
%v1 = call i32 @llvm.mblaze.fsl.aget(i32 %port)
}
define void @fslc_get() {
- ; CHECK: fslc_get:
+ ; CHECK-LABEL: fslc_get:
%v0 = call i32 @llvm.mblaze.fsl.get(i32 1)
; CHECK: get
%v1 = call i32 @llvm.mblaze.fsl.aget(i32 1)
}
define void @putfsl(i32 %value, i32 %port) {
- ; CHECK: putfsl:
+ ; CHECK-LABEL: putfsl:
call void @llvm.mblaze.fsl.put(i32 %value, i32 %port)
; CHECK: putd
call void @llvm.mblaze.fsl.aput(i32 %value, i32 %port)
}
define void @putfsl_const(i32 %value) {
- ; CHECK: putfsl_const:
+ ; CHECK-LABEL: putfsl_const:
call void @llvm.mblaze.fsl.put(i32 %value, i32 1)
; CHECK-NOT: putd
; CHECK: put
; RUN: llc < %s -march=mblaze -mattr=+fpu | FileCheck -check-prefix=FPU %s
define i8 @retimm_i8() {
- ; CHECK: retimm_i8:
+ ; CHECK-LABEL: retimm_i8:
; CHECK: rtsd
; CHECK-NEXT: add
- ; FPU: retimm_i8:
+ ; FPU-LABEL: retimm_i8:
; FPU: rtsd
; FPU-NEXT: add
ret i8 123
}
define i16 @retimm_i16() {
- ; CHECK: retimm_i16:
+ ; CHECK-LABEL: retimm_i16:
; CHECK: rtsd
; CHECK-NEXT: add
- ; FPU: retimm_i16:
+ ; FPU-LABEL: retimm_i16:
; FPU: rtsd
; FPU-NEXT: add
ret i16 31212
}
define i32 @retimm_i32() {
- ; CHECK: retimm_i32:
+ ; CHECK-LABEL: retimm_i32:
; CHECK: add
; CHECK-NEXT: rtsd
- ; FPU: retimm_i32:
+ ; FPU-LABEL: retimm_i32:
; FPU: add
; FPU-NEXT: rtsd
ret i32 2938128
}
define i64 @retimm_i64() {
- ; CHECK: retimm_i64:
+ ; CHECK-LABEL: retimm_i64:
; CHECK: add
; CHECK-NEXT: rtsd
; CHECK-NEXT: add
- ; FPU: retimm_i64:
+ ; FPU-LABEL: retimm_i64:
; FPU: add
; FPU-NEXT: rtsd
; FPU-NEXT: add
}
define float @retimm_float() {
- ; CHECK: retimm_float:
+ ; CHECK-LABEL: retimm_float:
; CHECK: add
; CHECK-NEXT: rtsd
- ; FPU: retimm_float:
+ ; FPU-LABEL: retimm_float:
; FPU: or
; FPU-NEXT: rtsd
ret float 12.0
}
define double @retimm_double() {
- ; CHECK: retimm_double:
+ ; CHECK-LABEL: retimm_double:
; CHECK: add
; CHECK-NEXT: add
; CHECK-NEXT: rtsd
- ; FPU: retimm_double:
+ ; FPU-LABEL: retimm_double:
; FPU: add
; FPU-NEXT: add
; FPU-NEXT: rtsd
@_interrupt_handler = alias void ()* @myintr
define cc73 void @myintr() nounwind noinline {
- ; CHECK: myintr:
+ ; CHECK-LABEL: myintr:
; CHECK: swi r3, r1
; CHECK: swi r4, r1
; CHECK: swi r5, r1
define i32 @jmptable(i32 %arg)
{
- ; CHECK: jmptable:
+ ; CHECK-LABEL: jmptable:
switch i32 %arg, label %DEFAULT [ i32 0, label %L0
i32 1, label %L1
i32 2, label %L2
define i32 @loop(i32 %a, i32 %b)
{
- ; CHECK: loop:
+ ; CHECK-LABEL: loop:
entry:
br label %loop_outer
; RUN: llc < %s -march=mblaze -mattr=+mul | FileCheck -check-prefix=MUL %s
define i8 @test_i8(i8 %a, i8 %b) {
- ; FUN: test_i8:
- ; MUL: test_i8:
+ ; FUN-LABEL: test_i8:
+ ; MUL-LABEL: test_i8:
%tmp.1 = mul i8 %a, %b
; FUN-NOT: mul
}
define i16 @test_i16(i16 %a, i16 %b) {
- ; FUN: test_i16:
- ; MUL: test_i16:
+ ; FUN-LABEL: test_i16:
+ ; MUL-LABEL: test_i16:
%tmp.1 = mul i16 %a, %b
; FUN-NOT: mul
}
define i32 @test_i32(i32 %a, i32 %b) {
- ; FUN: test_i32:
- ; MUL: test_i32:
+ ; FUN-LABEL: test_i32:
+ ; MUL-LABEL: test_i32:
%tmp.1 = mul i32 %a, %b
; FUN-NOT: mul
; RUN: FileCheck -check-prefix=MUL %s
define i64 @test_i64(i64 %a, i64 %b) {
- ; FUN: test_i64:
- ; MUL: test_i64:
+ ; FUN-LABEL: test_i64:
+ ; MUL-LABEL: test_i64:
%tmp.1 = mul i64 %a, %b
; FUN-NOT: mul
define i32 @testsel(i32 %a, i32 %b)
{
- ; CHECK: testsel:
+ ; CHECK-LABEL: testsel:
%tmp.1 = icmp eq i32 %a, %b
; CHECK: cmp
%tmp.2 = select i1 %tmp.1, i32 %a, i32 %b
; RUN: llc < %s -march=mblaze -mattr=+barrel | FileCheck -check-prefix=SHT %s
define i8 @test_i8(i8 %a, i8 %b) {
- ; FUN: test_i8:
- ; SHT: test_i8:
+ ; FUN-LABEL: test_i8:
+ ; SHT-LABEL: test_i8:
%tmp.1 = shl i8 %a, %b
; FUN: andi
}
define i8 @testc_i8(i8 %a, i8 %b) {
- ; FUN: testc_i8:
- ; SHT: testc_i8:
+ ; FUN-LABEL: testc_i8:
+ ; SHT-LABEL: testc_i8:
%tmp.1 = shl i8 %a, 5
; FUN: andi
}
define i16 @test_i16(i16 %a, i16 %b) {
- ; FUN: test_i16:
- ; SHT: test_i16:
+ ; FUN-LABEL: test_i16:
+ ; SHT-LABEL: test_i16:
%tmp.1 = shl i16 %a, %b
; FUN: andi
}
define i16 @testc_i16(i16 %a, i16 %b) {
- ; FUN: testc_i16:
- ; SHT: testc_i16:
+ ; FUN-LABEL: testc_i16:
+ ; SHT-LABEL: testc_i16:
%tmp.1 = shl i16 %a, 5
; FUN: andi
}
define i32 @test_i32(i32 %a, i32 %b) {
- ; FUN: test_i32:
- ; SHT: test_i32:
+ ; FUN-LABEL: test_i32:
+ ; SHT-LABEL: test_i32:
%tmp.1 = shl i32 %a, %b
; FUN: andi
}
define i32 @testc_i32(i32 %a, i32 %b) {
- ; FUN: testc_i32:
- ; SHT: testc_i32:
+ ; FUN-LABEL: testc_i32:
+ ; SHT-LABEL: testc_i32:
%tmp.1 = shl i32 %a, 5
; FUN: andi
@.str = private constant [28 x i8] c"The interrupt has gone off\0A\00"
define cc74 void @mysvol() nounwind noinline {
- ; CHECK: mysvol:
+ ; CHECK-LABEL: mysvol:
; CHECK: swi r3, r1
; CHECK: swi r4, r1
; CHECK: swi r5, r1
}
define cc74 void @mysvol2() nounwind noinline {
- ; CHECK: mysvol2:
+ ; CHECK-LABEL: mysvol2:
; CHECK-NOT: swi r3, r1
; CHECK-NOT: swi r4, r1
; CHECK-NOT: swi r5, r1
define signext i8 @foo(i8 signext %_si1, i8 signext %_si2) nounwind readnone {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: call #__mulqi3
%mul = mul i8 %_si2, %_si1 ; <i8> [#uses=1]
ret i8 %mul
%2 = or i16 %1,%x
ret i16 %2
}
-; CHECK: am1:
+; CHECK-LABEL: am1:
; CHECK: bis.w 0(r14), r15
@foo = external global i16
%2 = or i16 %1,%x
ret i16 %2
}
-; CHECK: am2:
+; CHECK-LABEL: am2:
; CHECK: bis.w &foo, r15
@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
%3 = or i8 %2,%x
ret i8 %3
}
-; CHECK: am3:
+; CHECK-LABEL: am3:
; CHECK: bis.b bar(r14), r15
define i16 @am4(i16 %x) nounwind {
%2 = or i16 %1,%x
ret i16 %2
}
-; CHECK: am4:
+; CHECK-LABEL: am4:
; CHECK: bis.w &32, r15
define i16 @am5(i16 %x, i16* %a) nounwind {
%3 = or i16 %2,%x
ret i16 %3
}
-; CHECK: am5:
+; CHECK-LABEL: am5:
; CHECK: bis.w 4(r14), r15
%S = type { i16, i16 }
%2 = or i16 %1,%x
ret i16 %2
}
-; CHECK: am6:
+; CHECK-LABEL: am6:
; CHECK: bis.w &baz+2, r15
%T = type { i16, [2 x i8] }
%4 = or i8 %3,%x
ret i8 %4
}
-; CHECK: am7:
+; CHECK-LABEL: am7:
; CHECK: bis.b duh+2(r14), r15
store i16 %2, i16* %a
ret void
}
-; CHECK: am1:
+; CHECK-LABEL: am1:
; CHECK: bis.w r14, 0(r15)
@foo = external global i16
store i16 %2, i16* @foo
ret void
}
-; CHECK: am2:
+; CHECK-LABEL: am2:
; CHECK: bis.w r15, &foo
@bar = external global [2 x i8]
store i8 %3, i8* %1
ret void
}
-; CHECK: am3:
+; CHECK-LABEL: am3:
; CHECK: bis.b r14, bar(r15)
define void @am4(i16 %x) nounwind {
store volatile i16 %2, i16* inttoptr(i16 32 to i16*)
ret void
}
-; CHECK: am4:
+; CHECK-LABEL: am4:
; CHECK: bis.w r15, &32
define void @am5(i16* %a, i16 %x) readonly {
store i16 %3, i16* %1
ret void
}
-; CHECK: am5:
+; CHECK-LABEL: am5:
; CHECK: bis.w r14, 4(r15)
%S = type { i16, i16 }
store i16 %2, i16* getelementptr (%S* @baz, i32 0, i32 1)
ret void
}
-; CHECK: am6:
+; CHECK-LABEL: am6:
; CHECK: bis.w r15, &baz+2
%T = type { i16, [2 x i8] }
store i8 %4, i8* %2
ret void
}
-; CHECK: am7:
+; CHECK-LABEL: am7:
; CHECK: bis.b r14, duh+2(r15)
%1 = load i16* %a
ret i16 %1
}
-; CHECK: am1:
+; CHECK-LABEL: am1:
; CHECK: mov.w 0(r15), r15
@foo = external global i16
%1 = load i16* @foo
ret i16 %1
}
-; CHECK: am2:
+; CHECK-LABEL: am2:
; CHECK: mov.w &foo, r15
@bar = internal constant [2 x i8] [ i8 32, i8 64 ]
%2 = load i8* %1
ret i8 %2
}
-; CHECK: am3:
+; CHECK-LABEL: am3:
; CHECK: mov.b bar(r15), r15
define i16 @am4() nounwind {
%1 = load volatile i16* inttoptr(i16 32 to i16*)
ret i16 %1
}
-; CHECK: am4:
+; CHECK-LABEL: am4:
; CHECK: mov.w &32, r15
define i16 @am5(i16* %a) nounwind {
%2 = load i16* %1
ret i16 %2
}
-; CHECK: am5:
+; CHECK-LABEL: am5:
; CHECK: mov.w 4(r15), r15
%S = type { i16, i16 }
%1 = load i16* getelementptr (%S* @baz, i32 0, i32 1)
ret i16 %1
}
-; CHECK: am6:
+; CHECK-LABEL: am6:
; CHECK: mov.w &baz+2, r15
%T = type { i16, [2 x i8] }
%3= load i8* %2
ret i8 %3
}
-; CHECK: am7:
+; CHECK-LABEL: am7:
; CHECK: mov.b duh+2(r15), r15
store i16 %b, i16* %a
ret void
}
-; CHECK: am1:
+; CHECK-LABEL: am1:
; CHECK: mov.w r14, 0(r15)
@foo = external global i16
store i16 %a, i16* @foo
ret void
}
-; CHECK: am2:
+; CHECK-LABEL: am2:
; CHECK: mov.w r15, &foo
@bar = external global [2 x i8]
store i8 %a, i8* %1
ret void
}
-; CHECK: am3:
+; CHECK-LABEL: am3:
; CHECK: mov.b r14, bar(r15)
define void @am4(i16 %a) nounwind {
store volatile i16 %a, i16* inttoptr(i16 32 to i16*)
ret void
}
-; CHECK: am4:
+; CHECK-LABEL: am4:
; CHECK: mov.w r15, &32
define void @am5(i16* nocapture %p, i16 %a) nounwind readonly {
store i16 %a, i16* %1
ret void
}
-; CHECK: am5:
+; CHECK-LABEL: am5:
; CHECK: mov.w r14, 4(r15)
%S = type { i16, i16 }
store i16 %a, i16* getelementptr (%S* @baz, i32 0, i32 1)
ret void
}
-; CHECK: am6:
+; CHECK-LABEL: am6:
; CHECK: mov.w r15, &baz+2
%T = type { i16, [2 x i8] }
store i8 %a, i8* %2
ret void
}
-; CHECK: am7:
+; CHECK-LABEL: am7:
; CHECK: mov.b r14, duh+2(r15)
@foo = common global i16 0, align 2
define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w #2, &foo
store i16 2, i16 * @foo
ret void
}
define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w #2, &foo
%1 = load i16* @foo
%2 = add i16 %1, 2
}
define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w #2, &foo
%1 = load i16* @foo
%2 = and i16 %1, 2
}
define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w #2, &foo
%1 = load i16* @foo
%2 = or i16 %1, 2
}
define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w #2, &foo
%1 = load i16* @foo
%2 = xor i16 %1, 2
@bar = common global i16 0, align 2
define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w &bar, &foo
%1 = load i16* @bar
store i16 %1, i16* @foo
}
define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w &bar, &foo
%1 = load i16* @bar
%2 = load i16* @foo
}
define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w &bar, &foo
%1 = load i16* @bar
%2 = load i16* @foo
}
define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w &bar, &foo
%1 = load i16* @bar
%2 = load i16* @foo
}
define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w &bar, &foo
%1 = load i16* @bar
%2 = load i16* @foo
store i16 0, i16* %retval
%0 = load i16* %retval ; <i16> [#uses=1]
ret i16 %0
-; CHECK: mov2:
+; CHECK-LABEL: mov2:
; CHECK: mov.w 2(r1), 6(r1)
; CHECK: mov.w 0(r1), 4(r1)
}
@foo = common global i16 0, align 2
define void @mov(i16 %a) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w r15, &foo
store i16 %a, i16* @foo
ret void
}
define void @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w r15, &foo
%1 = load i16* @foo
%2 = add i16 %a, %1
}
define void @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w r15, &foo
%1 = load i16* @foo
%2 = and i16 %a, %1
}
define void @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w r15, &foo
%1 = load i16* @foo
%2 = or i16 %a, %1
}
define void @bic(i16 zeroext %m) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.w r15, &foo
%1 = xor i16 %m, -1
%2 = load i16* @foo
}
define void @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w r15, &foo
%1 = load i16* @foo
%2 = xor i16 %a, %1
target triple = "msp430-generic-generic"
define i16 @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w #1, r15
ret i16 1
}
define i16 @add(i16 %a, i16 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w #1, r15
%1 = add i16 %a, 1
ret i16 %1
}
define i16 @and(i16 %a, i16 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w #1, r15
%1 = and i16 %a, 1
ret i16 %1
}
define i16 @bis(i16 %a, i16 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w #1, r15
%1 = or i16 %a, 1
ret i16 %1
}
define i16 @xor(i16 %a, i16 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w #1, r15
%1 = xor i16 %a, 1
ret i16 %1
@foo = common global i16 0, align 2
define i16 @add(i16 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w &foo, r15
%1 = load i16* @foo
%2 = add i16 %a, %1
}
define i16 @and(i16 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w &foo, r15
%1 = load i16* @foo
%2 = and i16 %a, %1
}
define i16 @bis(i16 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w &foo, r15
%1 = load i16* @foo
%2 = or i16 %a, %1
}
define i16 @bic(i16 %a) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.w &foo, r15
%1 = load i16* @foo
%2 = xor i16 %1, -1
}
define i16 @xor(i16 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w &foo, r15
%1 = load i16* @foo
%2 = xor i16 %a, %1
target triple = "msp430-generic-generic"
define i16 @mov(i16 %a, i16 %b) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.w r14, r15
ret i16 %b
}
define i16 @add(i16 %a, i16 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w r14, r15
%1 = add i16 %a, %b
ret i16 %1
}
define i16 @and(i16 %a, i16 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w r14, r15
%1 = and i16 %a, %b
ret i16 %1
}
define i16 @bis(i16 %a, i16 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w r14, r15
%1 = or i16 %a, %b
ret i16 %1
}
define i16 @bic(i16 %a, i16 %b) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.w r14, r15
%1 = xor i16 %b, -1
%2 = and i16 %a, %1
}
define i16 @xor(i16 %a, i16 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w r14, r15
%1 = xor i16 %a, %b
ret i16 %1
@foo = common global i8 0, align 1
define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.b #2, &foo
store i8 2, i8 * @foo
ret void
}
define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b #2, &foo
%1 = load i8* @foo
%2 = add i8 %1, 2
}
define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b #2, &foo
%1 = load i8* @foo
%2 = and i8 %1, 2
}
define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b #2, &foo
%1 = load i8* @foo
%2 = or i8 %1, 2
}
define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b #2, &foo
%1 = load i8* @foo
%2 = xor i8 %1, 2
@bar = common global i8 0, align 1
define void @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.b &bar, &foo
%1 = load i8* @bar
store i8 %1, i8* @foo
}
define void @add() nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b &bar, &foo
%1 = load i8* @bar
%2 = load i8* @foo
}
define void @and() nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b &bar, &foo
%1 = load i8* @bar
%2 = load i8* @foo
}
define void @bis() nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b &bar, &foo
%1 = load i8* @bar
%2 = load i8* @foo
}
define void @xor() nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b &bar, &foo
%1 = load i8* @bar
%2 = load i8* @foo
@foo = common global i8 0, align 1
define void @mov(i8 %a) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.b r15, &foo
store i8 %a, i8* @foo
ret void
}
define void @and(i8 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b r15, &foo
%1 = load i8* @foo
%2 = and i8 %a, %1
}
define void @add(i8 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b r15, &foo
%1 = load i8* @foo
%2 = add i8 %a, %1
}
define void @bis(i8 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b r15, &foo
%1 = load i8* @foo
%2 = or i8 %a, %1
}
define void @bic(i8 zeroext %m) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.b r15, &foo
%1 = xor i8 %m, -1
%2 = load i8* @foo
}
define void @xor(i8 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b r15, &foo
%1 = load i8* @foo
%2 = xor i8 %a, %1
target triple = "msp430-generic-generic"
define i8 @mov() nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.b #1, r15
ret i8 1
}
define i8 @add(i8 %a, i8 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b #1, r15
%1 = add i8 %a, 1
ret i8 %1
}
define i8 @and(i8 %a, i8 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b #1, r15
%1 = and i8 %a, 1
ret i8 %1
}
define i8 @bis(i8 %a, i8 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b #1, r15
%1 = or i8 %a, 1
ret i8 %1
}
define i8 @xor(i8 %a, i8 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b #1, r15
%1 = xor i8 %a, 1
ret i8 %1
@foo = common global i8 0, align 1
define i8 @add(i8 %a) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b &foo, r15
%1 = load i8* @foo
%2 = add i8 %a, %1
}
define i8 @and(i8 %a) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.b &foo, r15
%1 = load i8* @foo
%2 = and i8 %a, %1
}
define i8 @bis(i8 %a) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.b &foo, r15
%1 = load i8* @foo
%2 = or i8 %a, %1
}
define i8 @bic(i8 %a) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.b &foo, r15
%1 = load i8* @foo
%2 = xor i8 %1, -1
}
define i8 @xor(i8 %a) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.b &foo, r15
%1 = load i8* @foo
%2 = xor i8 %a, %1
target triple = "msp430-generic-generic"
define i8 @mov(i8 %a, i8 %b) nounwind {
-; CHECK: mov:
+; CHECK-LABEL: mov:
; CHECK: mov.{{[bw]}} r14, r15
ret i8 %b
}
define i8 @add(i8 %a, i8 %b) nounwind {
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.b
%1 = add i8 %a, %b
ret i8 %1
}
define i8 @and(i8 %a, i8 %b) nounwind {
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w r14, r15
%1 = and i8 %a, %b
ret i8 %1
}
define i8 @bis(i8 %a, i8 %b) nounwind {
-; CHECK: bis:
+; CHECK-LABEL: bis:
; CHECK: bis.w r14, r15
%1 = or i8 %a, %b
ret i8 %1
}
define i8 @bic(i8 %a, i8 %b) nounwind {
-; CHECK: bic:
+; CHECK-LABEL: bic:
; CHECK: bic.b r14, r15
%1 = xor i8 %b, -1
%2 = and i8 %a, %1
}
define i8 @xor(i8 %a, i8 %b) nounwind {
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w r14, r15
%1 = xor i8 %a, %b
ret i8 %1
%t3 = zext i1 %t2 to i8
ret i8 %t3
}
-; CHECK: bitbrr:
+; CHECK-LABEL: bitbrr:
; CHECK: bit.b r14, r15
define i8 @bitbri(i8 %a) nounwind {
%t3 = zext i1 %t2 to i8
ret i8 %t3
}
-; CHECK: bitbri:
+; CHECK-LABEL: bitbri:
; CHECK: bit.b #15, r15
define i8 @bitbir(i8 %a) nounwind {
%t3 = zext i1 %t2 to i8
ret i8 %t3
}
-; CHECK: bitbir:
+; CHECK-LABEL: bitbir:
; CHECK: bit.b #15, r15
define i8 @bitbmi() nounwind {
%t4 = zext i1 %t3 to i8
ret i8 %t4
}
-; CHECK: bitbmi:
+; CHECK-LABEL: bitbmi:
; CHECK: bit.b #15, &foo8
define i8 @bitbim() nounwind {
%t4 = zext i1 %t3 to i8
ret i8 %t4
}
-; CHECK: bitbim:
+; CHECK-LABEL: bitbim:
; CHECK: bit.b #15, &foo8
define i8 @bitbrm(i8 %a) nounwind {
%t4 = zext i1 %t3 to i8
ret i8 %t4
}
-; CHECK: bitbrm:
+; CHECK-LABEL: bitbrm:
; CHECK: bit.b &foo8, r15
define i8 @bitbmr(i8 %a) nounwind {
%t4 = zext i1 %t3 to i8
ret i8 %t4
}
-; CHECK: bitbmr:
+; CHECK-LABEL: bitbmr:
; CHECK: bit.b r15, &foo8
define i8 @bitbmm() nounwind {
%t5 = zext i1 %t4 to i8
ret i8 %t5
}
-; CHECK: bitbmm:
+; CHECK-LABEL: bitbmm:
; CHECK: bit.b &bar8, &foo8
@foo16 = external global i16
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: bitwrr:
+; CHECK-LABEL: bitwrr:
; CHECK: bit.w r14, r15
define i16 @bitwri(i16 %a) nounwind {
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: bitwri:
+; CHECK-LABEL: bitwri:
; CHECK: bit.w #4080, r15
define i16 @bitwir(i16 %a) nounwind {
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: bitwir:
+; CHECK-LABEL: bitwir:
; CHECK: bit.w #4080, r15
define i16 @bitwmi() nounwind {
%t4 = zext i1 %t3 to i16
ret i16 %t4
}
-; CHECK: bitwmi:
+; CHECK-LABEL: bitwmi:
; CHECK: bit.w #4080, &foo16
define i16 @bitwim() nounwind {
%t4 = zext i1 %t3 to i16
ret i16 %t4
}
-; CHECK: bitwim:
+; CHECK-LABEL: bitwim:
; CHECK: bit.w #4080, &foo16
define i16 @bitwrm(i16 %a) nounwind {
%t4 = zext i1 %t3 to i16
ret i16 %t4
}
-; CHECK: bitwrm:
+; CHECK-LABEL: bitwrm:
; CHECK: bit.w &foo16, r15
define i16 @bitwmr(i16 %a) nounwind {
%t4 = zext i1 %t3 to i16
ret i16 %t4
}
-; CHECK: bitwmr:
+; CHECK-LABEL: bitwmr:
; CHECK: bit.w r15, &foo16
define i16 @bitwmm() nounwind {
%t5 = zext i1 %t4 to i16
ret i16 %t5
}
-; CHECK: bitwmm:
+; CHECK-LABEL: bitwmm:
; CHECK: bit.w &bar16, &foo16
define i16 @callee(%struct.Foo* byval %f) nounwind {
entry:
-; CHECK: callee:
+; CHECK-LABEL: callee:
; CHECK: mov.w 2(r1), r15
%0 = getelementptr inbounds %struct.Foo* %f, i32 0, i32 0
%1 = load i16* %0, align 2
define void @caller() nounwind {
entry:
-; CHECK: caller:
+; CHECK-LABEL: caller:
; CHECK: mov.w &foo+4, 4(r1)
; CHECK-NEXT: mov.w &foo+2, 2(r1)
; CHECK-NEXT: mov.w &foo, 0(r1)
define void @fp() nounwind {
entry:
-; CHECK: fp:
+; CHECK-LABEL: fp:
; CHECK: push.w r4
; CHECK: mov.w r1, r4
; CHECK: sub.w #2, r1
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: add:
+; CHECK-LABEL: add:
; CHECK: add.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = add i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: sub:
+; CHECK-LABEL: sub:
; CHECK: sub.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = sub i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: or:
+; CHECK-LABEL: or:
; CHECK: bis.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = or i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: xor:
+; CHECK-LABEL: xor:
; CHECK: xor.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = xor i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%i.010 = phi i16 [ 0, %entry ], [ %inc, %for.body ] ; <i16> [#uses=2]
%sum.09 = phi i16 [ 0, %entry ], [ %add, %for.body ] ; <i16> [#uses=1]
%arrayidx = getelementptr i16* %a, i16 %i.010 ; <i16*> [#uses=1]
-; CHECK: and:
+; CHECK-LABEL: and:
; CHECK: and.w @r{{[0-9]+}}+, r{{[0-9]+}}
%tmp4 = load i16* %arrayidx ; <i16> [#uses=1]
%add = and i16 %tmp4, %sum.09 ; <i16> [#uses=2]
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: sccweqand:
+; CHECK-LABEL: sccweqand:
; CHECK: bit.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: rra.w r15
%t3 = zext i1 %t2 to i16
ret i16 %t3
}
-; CHECK: sccwneand:
+; CHECK-LABEL: sccwneand:
; CHECK: bit.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwne:
+; CHECK-LABEL:sccwne:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r12
; CHECK: rra.w r12
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccweq:
+; CHECK-LABEL:sccweq:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: rra.w r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwugt:
+; CHECK-LABEL:sccwugt:
; CHECK: cmp.w r15, r14
; CHECK: mov.w #1, r15
; CHECK: bic.w r2, r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwuge:
+; CHECK-LABEL:sccwuge:
; CHECK: cmp.w r14, r15
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwult:
+; CHECK-LABEL:sccwult:
; CHECK: cmp.w r14, r15
; CHECK: mov.w #1, r15
; CHECK: bic.w r2, r15
%t2 = zext i1 %t1 to i16
ret i16 %t2
}
-; CHECK:sccwule:
+; CHECK-LABEL:sccwule:
; CHECK: cmp.w r15, r14
; CHECK: mov.w r2, r15
; CHECK: and.w #1, r15
define zeroext i8 @lshr8(i8 zeroext %a, i8 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: lshr8:
+; CHECK-LABEL: lshr8:
; CHECK: rrc.b
%shr = lshr i8 %a, %cnt
ret i8 %shr
define signext i8 @ashr8(i8 signext %a, i8 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: ashr8:
+; CHECK-LABEL: ashr8:
; CHECK: rra.b
%shr = ashr i8 %a, %cnt
ret i8 %shr
define zeroext i16 @lshr16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: lshr16:
+; CHECK-LABEL: lshr16:
; CHECK: rrc.w
%shr = lshr i16 %a, %cnt
ret i16 %shr
define signext i16 @ashr16(i16 signext %a, i16 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: ashr16:
+; CHECK-LABEL: ashr16:
; CHECK: rra.w
%shr = ashr i16 %a, %cnt
ret i16 %shr
define zeroext i16 @shl16(i16 zeroext %a, i16 zeroext %cnt) nounwind readnone {
entry:
-; CHECK: shl16:
+; CHECK-LABEL: shl16:
; CHECK: rla.w
%shl = shl i16 %a, %cnt
ret i16 %shl
define void @va_start(i16 %a, ...) nounwind {
entry:
-; CHECK: va_start:
+; CHECK-LABEL: va_start:
; CHECK: sub.w #2, r1
%vl = alloca i8*, align 2
%vl1 = bitcast i8** %vl to i8*
define i16 @va_arg(i8* %vl) nounwind {
entry:
-; CHECK: va_arg:
+; CHECK-LABEL: va_arg:
%vl.addr = alloca i8*, align 2
; CHECK: mov.w r15, 0(r1)
store i8* %vl, i8** %vl.addr, align 2
define void @va_copy(i8* %vl) nounwind {
entry:
-; CHECK: va_copy:
+; CHECK-LABEL: va_copy:
%vl.addr = alloca i8*, align 2
%vl2 = alloca i8*, align 2
; CHECK: mov.w r15, 2(r1)
%0 = atomicrmw add i32* @x, i32 %incr monotonic
ret i32 %0
-; CHECK-EL: AtomicLoadAdd32:
+; CHECK-EL-LABEL: AtomicLoadAdd32:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])
; CHECK-EL: sc $[[R2]], 0($[[R0]])
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
-; CHECK-EB: AtomicLoadAdd32:
+; CHECK-EB-LABEL: AtomicLoadAdd32:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])
%0 = atomicrmw nand i32* @x, i32 %incr monotonic
ret i32 %0
-; CHECK-EL: AtomicLoadNand32:
+; CHECK-EL-LABEL: AtomicLoadNand32:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EL: ll $[[R1:[0-9]+]], 0($[[R0]])
; CHECK-EL: sc $[[R2]], 0($[[R0]])
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
-; CHECK-EB: AtomicLoadNand32:
+; CHECK-EB-LABEL: AtomicLoadNand32:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EB: ll $[[R1:[0-9]+]], 0($[[R0]])
%0 = atomicrmw xchg i32* @x, i32 %tmp monotonic
ret i32 %0
-; CHECK-EL: AtomicSwap32:
+; CHECK-EL-LABEL: AtomicSwap32:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EL: ll ${{[0-9]+}}, 0($[[R0]])
; CHECK-EL: sc $[[R2:[0-9]+]], 0($[[R0]])
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
-; CHECK-EB: AtomicSwap32:
+; CHECK-EB-LABEL: AtomicSwap32:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EB: ll ${{[0-9]+}}, 0($[[R0]])
%0 = cmpxchg i32* @x, i32 %oldval, i32 %tmp monotonic
ret i32 %0
-; CHECK-EL: AtomicCmpSwap32:
+; CHECK-EL-LABEL: AtomicCmpSwap32:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EL: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EL: ll $2, 0($[[R0]])
; CHECK-EL: beq $[[R2]], $zero, $[[BB0]]
; CHECK-EL: $[[BB1]]:
-; CHECK-EB: AtomicCmpSwap32:
+; CHECK-EB-LABEL: AtomicCmpSwap32:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(x)
; CHECK-EB: $[[BB0:[A-Z_0-9]+]]:
; CHECK-EB: ll $2, 0($[[R0]])
%0 = atomicrmw add i8* @y, i8 %incr monotonic
ret i8 %0
-; CHECK-EL: AtomicLoadAdd8:
+; CHECK-EL-LABEL: AtomicLoadAdd8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicLoadAdd8:
+; CHECK-EB-LABEL: AtomicLoadAdd8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
%0 = atomicrmw sub i8* @y, i8 %incr monotonic
ret i8 %0
-; CHECK-EL: AtomicLoadSub8:
+; CHECK-EL-LABEL: AtomicLoadSub8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicLoadSub8:
+; CHECK-EB-LABEL: AtomicLoadSub8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
%0 = atomicrmw nand i8* @y, i8 %incr monotonic
ret i8 %0
-; CHECK-EL: AtomicLoadNand8:
+; CHECK-EL-LABEL: AtomicLoadNand8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicLoadNand8:
+; CHECK-EB-LABEL: AtomicLoadNand8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
%0 = atomicrmw xchg i8* @y, i8 %newval monotonic
ret i8 %0
-; CHECK-EL: AtomicSwap8:
+; CHECK-EL-LABEL: AtomicSwap8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicSwap8:
+; CHECK-EB-LABEL: AtomicSwap8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
%0 = cmpxchg i8* @y, i8 %oldval, i8 %newval monotonic
ret i8 %0
-; CHECK-EL: AtomicCmpSwap8:
+; CHECK-EL-LABEL: AtomicCmpSwap8:
; CHECK-EL: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EL: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EL: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
; CHECK-EL: sll $[[R17:[0-9]+]], $[[R16]], 24
; CHECK-EL: sra $2, $[[R17]], 24
-; CHECK-EB: AtomicCmpSwap8:
+; CHECK-EB-LABEL: AtomicCmpSwap8:
; CHECK-EB: lw $[[R0:[0-9]+]], %got(y)
; CHECK-EB: addiu $[[R1:[0-9]+]], $zero, -4
; CHECK-EB: and $[[R2:[0-9]+]], $[[R0]], $[[R1]]
%0 = atomicrmw add i32* @countsint, i32 %v seq_cst
ret i32 %0
-; CHECK-EL: CheckSync:
+; CHECK-EL-LABEL: CheckSync:
; CHECK-EL: sync 0
; CHECK-EL: ll
; CHECK-EL: sc
; CHECK-EL: beq
; CHECK-EL: sync 0
-; CHECK-EB: CheckSync:
+; CHECK-EB-LABEL: CheckSync:
; CHECK-EB: sync 0
; CHECK-EB: ll
; CHECK-EB: sc
%0 = atomicrmw add i32* %mem, i32 %val seq_cst
%add = add nsw i32 %0, %c
ret i32 %add
-; 16: foo:
+; 16-LABEL: foo:
; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
}
%4 = atomicrmw xchg i32* %x, i32 1 seq_cst
%5 = load volatile i32* %x, align 4
%call3 = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([8 x i8]* @.str, i32 0, i32 0), i32 %4, i32 %5) nounwind
-; 16: main:
+; 16-LABEL: main:
; 16: lw ${{[0-9]+}}, %call16(__sync_synchronize)(${{[0-9]+}})
; 16: lw ${{[0-9]+}}, %call16(__sync_fetch_and_add_4)(${{[0-9]+}})
; 16: lw ${{[0-9]+}}, %call16(__sync_val_compare_and_swap_4)(${{[0-9]+}})
define void @foo2(i32* nocapture %d, i32* nocapture %s, i32 %n) nounwind {
entry:
-; O32: foo2:
+; O32-LABEL: foo2:
; O32: lui $[[R2:[0-9]+]], %call_hi(memcpy)
; O32: addu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
; O32: lw ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
-; N64: foo2:
+; N64-LABEL: foo2:
; N64: lui $[[R2:[0-9]+]], %call_hi(memcpy)
; N64: daddu $[[R3:[0-9]+]], $[[R2]], ${{[a-z0-9]+}}
; N64: ld ${{[0-9]+}}, %call_lo(memcpy)($[[R3]])
;
define void @foo3(i32 %a) nounwind {
entry:
-; Default: foo3:
+; Default-LABEL: foo3:
; Default: jalr
; Default: cvt.d.w
; Check that branch delay slot can be filled with an instruction with operand
; $1.
;
-; Default: foo5:
+; Default-LABEL: foo5:
; Default-NOT: nop
define void @foo5(i32 %a) nounwind {
; Check that delay slot filler can place mov.s or mov.d in delay slot.
;
-; Default: foo6:
+; Default-LABEL: foo6:
; Default-NOT: nop
; Default: .end foo6
; Check that a store can move past other memory instructions.
;
-; STATICO1: foo8:
+; STATICO1-LABEL: foo8:
; STATICO1: jalr ${{[0-9]+}}
; STATICO1-NEXT: sw ${{[0-9]+}}, %lo(g1)
; Test searchForward. Check that the second jal's slot is filled with another
; instruction in the same block.
;
-; FORWARD: foo10:
+; FORWARD-LABEL: foo10:
; FORWARD: jal foo11
; FORWARD: jal foo11
; FORWARD-NOT: nop
; Check that delay slots of branches in both the entry block and loop body are
; filled.
;
-; SUCCBB: succbbs_loop1:
+; SUCCBB-LABEL: succbbs_loop1:
; SUCCBB: blez $5, $BB
; SUCCBB-NEXT: addiu
; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
; Check that the first branch has its slot filled.
;
-; SUCCBB: succbbs_br1:
+; SUCCBB-LABEL: succbbs_br1:
; SUCCBB: beq ${{[0-9]+}}, $zero, $BB
; SUCCBB-NEXT: lw $25, %call16(foo100)
define i32 @bswap32(i32 %x) nounwind readnone {
entry:
-; MIPS32: bswap32:
+; MIPS32-LABEL: bswap32:
; MIPS32: wsbh $[[R0:[0-9]+]]
; MIPS32: rotr ${{[0-9]+}}, $[[R0]], 16
%or.3 = call i32 @llvm.bswap.i32(i32 %x)
define i64 @bswap64(i64 %x) nounwind readnone {
entry:
-; MIPS64: bswap64:
+; MIPS64-LABEL: bswap64:
; MIPS64: dsbh $[[R0:[0-9]+]]
; MIPS64: dshd ${{[0-9]+}}, $[[R0]]
%or.7 = call i64 @llvm.bswap.i64(i64 %x)
define void @f() nounwind readnone {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: .set noat
; CHECK: .set at
@c = global i32 1, align 4
@d = global i32 0, align 4
-; O32: cmov2:
+; O32-LABEL: cmov2:
; O32: addiu $[[R1:[0-9]+]], ${{[a-z0-9]+}}, %got(d)
; O32: addiu $[[R0:[0-9]+]], ${{[a-z0-9]+}}, %got(c)
; O32: movn $[[R1]], $[[R0]], ${{[0-9]+}}
-; N64: cmov2:
+; N64-LABEL: cmov2:
; N64: daddiu $[[R1:[0-9]+]], ${{[0-9]+}}, %got_disp(d)
; N64: daddiu $[[R0:[0-9]+]], ${{[0-9]+}}, %got_disp(c)
; N64: movn $[[R1]], $[[R0]], ${{[0-9]+}}
ret i32 %cond
}
-; O32: cmov3:
+; O32-LABEL: cmov3:
; O32: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
define i32 @cmov3(i32 %a, i32 %b, i32 %c) nounwind readnone {
ret i32 %cond
}
-; N64: cmov4:
+; N64-LABEL: cmov4:
; N64: xori $[[R0:[0-9]+]], ${{[0-9]+}}, 234
; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
define i64 @cmov4(i32 %a, i64 %b, i64 %c) nounwind readnone {
; (movz t, (setlt a, N + 1), f)
; if N + 1 fits in 16-bit.
-; O32: slti0:
+; O32-LABEL: slti0:
; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
ret i32 %cond
}
-; O32: slti1:
+; O32-LABEL: slti1:
; O32: slt ${{[0-9]+}}
define i32 @slti1(i32 %a) {
ret i32 %cond
}
-; O32: slti2:
+; O32-LABEL: slti2:
; O32: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
ret i32 %cond
}
-; O32: slti3:
+; O32-LABEL: slti3:
; O32: slt ${{[0-9]+}}
define i32 @slti3(i32 %a) {
; 64-bit patterns.
-; N64: slti64_0:
+; N64-LABEL: slti64_0:
; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
ret i64 %conv
}
-; N64: slti64_1:
+; N64-LABEL: slti64_1:
; N64: slt ${{[0-9]+}}
define i64 @slti64_1(i64 %a) {
ret i64 %conv
}
-; N64: slti64_2:
+; N64-LABEL: slti64_2:
; N64: slti $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
; N64: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
ret i64 %conv
}
-; N64: slti64_3:
+; N64-LABEL: slti64_3:
; N64: slt ${{[0-9]+}}
define i64 @slti64_3(i64 %a) {
; sltiu instructions.
-; O32: sltiu0:
+; O32-LABEL: sltiu0:
; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, 32767
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
ret i32 %cond
}
-; O32: sltiu1:
+; O32-LABEL: sltiu1:
; O32: sltu ${{[0-9]+}}
define i32 @sltiu1(i32 %a) {
ret i32 %cond
}
-; O32: sltiu2:
+; O32-LABEL: sltiu2:
; O32: sltiu $[[R0:[0-9]+]], ${{[0-9]+}}, -32768
; O32: movz ${{[0-9]+}}, ${{[0-9]+}}, $[[R0]]
ret i32 %cond
}
-; O32: sltiu3:
+; O32-LABEL: sltiu3:
; O32: sltu ${{[0-9]+}}
define i32 @sltiu3(i32 %a) {
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK
; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=CHECK64
-; CHECK: mul5_32:
+; CHECK-LABEL: mul5_32:
; CHECK: sll $[[R0:[0-9]+]], $4, 2
; CHECK: addu ${{[0-9]+}}, $[[R0]], $4
ret i32 %mul
}
-; CHECK: mul27_32:
+; CHECK-LABEL: mul27_32:
; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 5
ret i32 %mul
}
-; CHECK: muln2147483643_32:
+; CHECK-LABEL: muln2147483643_32:
; CHECK-DAG: sll $[[R0:[0-9]+]], $4, 2
; CHECK-DAG: addu $[[R1:[0-9]+]], $[[R0]], $4
; CHECK-DAG: sll $[[R2:[0-9]+]], $4, 31
ret i32 %mul
}
-; CHECK64: muln9223372036854775805_64:
+; CHECK64-LABEL: muln9223372036854775805_64:
; CHECK64-DAG: dsll $[[R0:[0-9]+]], $4, 1
; CHECK64-DAG: daddu $[[R1:[0-9]+]], $[[R0]], $4
; CHECK64-DAG: dsll $[[R2:[0-9]+]], $4, 63
; RUN: llc -march=mips -mno-check-zero-division < %s |\
; RUN: FileCheck %s -check-prefix=NOCHECK
-; TRAP: sdiv1:
+; TRAP-LABEL: sdiv1:
; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; TRAP: teq $[[R0]], $zero, 7
; TRAP: mflo
-; NOCHECK: sdiv1:
+; NOCHECK-LABEL: sdiv1:
; NOCHECK-NOT: teq
; NOCHECK: .end sdiv1
ret i32 %div
}
-; TRAP: srem1:
+; TRAP-LABEL: srem1:
; TRAP: div $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; TRAP: teq $[[R0]], $zero, 7
; TRAP: mfhi
ret i32 %rem
}
-; TRAP: udiv1:
+; TRAP-LABEL: udiv1:
; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; TRAP: teq $[[R0]], $zero, 7
; TRAP: mflo
ret i32 %div
}
-; TRAP: urem1:
+; TRAP-LABEL: urem1:
; TRAP: divu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; TRAP: teq $[[R0]], $zero, 7
; TRAP: mfhi
; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s
-; CHECK: select_v2q15_eq_:
+; CHECK-LABEL: select_v2q15_eq_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_lt_:
+; CHECK-LABEL: select_v2q15_lt_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_le_:
+; CHECK-LABEL: select_v2q15_le_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $6, $7
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_ne_:
+; CHECK-LABEL: select_v2q15_ne_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_gt_:
+; CHECK-LABEL: select_v2q15_gt_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2q15_ge_:
+; CHECK-LABEL: select_v2q15_ge_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, $7, $6
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_eq_:
+; CHECK-LABEL: select_v4ui8_eq_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_lt_:
+; CHECK-LABEL: select_v4ui8_lt_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_le_:
+; CHECK-LABEL: select_v4ui8_le_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $6, $7
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_ne_:
+; CHECK-LABEL: select_v4ui8_ne_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_gt_:
+; CHECK-LABEL: select_v4ui8_gt_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4ui8_ge_:
+; CHECK-LABEL: select_v4ui8_ge_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, $7, $6
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_lt_:
+; CHECK-LABEL: select_v2ui16_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_le_:
+; CHECK-LABEL: select_v2ui16_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_gt_:
+; CHECK-LABEL: select_v2ui16_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v2ui16_ge_:
+; CHECK-LABEL: select_v2ui16_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_lt_:
+; CHECK-LABEL: select_v4i8_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_le_:
+; CHECK-LABEL: select_v4i8_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_gt_:
+; CHECK-LABEL: select_v4i8_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: select_v4i8_ge_:
+; CHECK-LABEL: select_v4i8_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_eq_:
+; CHECK-LABEL: compare_v2q15_eq_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_lt_:
+; CHECK-LABEL: compare_v2q15_lt_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_le_:
+; CHECK-LABEL: compare_v2q15_le_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_ne_:
+; CHECK-LABEL: compare_v2q15_ne_:
; CHECK: cmp.eq.ph ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_gt_:
+; CHECK-LABEL: compare_v2q15_gt_:
; CHECK: cmp.le.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2q15_ge_:
+; CHECK-LABEL: compare_v2q15_ge_:
; CHECK: cmp.lt.ph $4, $5
; CHECK: pick.ph ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_eq_:
+; CHECK-LABEL: compare_v4ui8_eq_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_lt_:
+; CHECK-LABEL: compare_v4ui8_lt_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_le_:
+; CHECK-LABEL: compare_v4ui8_le_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_ne_:
+; CHECK-LABEL: compare_v4ui8_ne_:
; CHECK: cmpu.eq.qb ${{[0-9]+}}, ${{[0-9]+}}
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_gt_:
+; CHECK-LABEL: compare_v4ui8_gt_:
; CHECK: cmpu.le.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4ui8_ge_:
+; CHECK-LABEL: compare_v4ui8_ge_:
; CHECK: cmpu.lt.qb $4, $5
; CHECK: pick.qb ${{[0-9]+}}, ${{[a-z0-9]+}}, ${{[a-z0-9]+}}
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_lt_:
+; CHECK-LABEL: compare_v2ui16_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_le_:
+; CHECK-LABEL: compare_v2ui16_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_gt_:
+; CHECK-LABEL: compare_v2ui16_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v2ui16_ge_:
+; CHECK-LABEL: compare_v2ui16_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_lt_:
+; CHECK-LABEL: compare_v4i8_lt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_le_:
+; CHECK-LABEL: compare_v4i8_le_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_gt_:
+; CHECK-LABEL: compare_v4i8_gt_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret { i32 } %.fca.0.insert
}
-; CHECK: compare_v4i8_ge_:
+; CHECK-LABEL: compare_v4i8_ge_:
; CHECK-NOT: cmp
; CHECK-NOT: pick
ret i64 %add
}
-; R1: shift1_v2i16_shl_:
+; R1-LABEL: shift1_v2i16_shl_:
; R1: shll.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) {
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v2i16_sra_:
+; R1-LABEL: shift1_v2i16_sra_:
; R1: shra.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) {
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v2ui16_srl_:
+; R1-LABEL: shift1_v2ui16_srl_:
; R1-NOT: shrl.ph
-; R2: shift1_v2ui16_srl_:
+; R2-LABEL: shift1_v2ui16_srl_:
; R2: shrl.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) {
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v4i8_shl_:
+; R1-LABEL: shift1_v4i8_shl_:
; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) {
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v4i8_sra_:
+; R1-LABEL: shift1_v4i8_sra_:
; R1-NOT: shra.qb
-; R2: shift1_v4i8_sra_:
+; R2-LABEL: shift1_v4i8_sra_:
; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) {
ret { i32 } %.fca.0.insert
}
-; R1: shift1_v4ui8_srl_:
+; R1-LABEL: shift1_v4ui8_srl_:
; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) {
@_ZTIPKc = external constant i8*
define i32 @main() {
-; 16: main:
+; 16-LABEL: main:
; 16: .cfi_startproc
; 16: save $ra, $s0, $s1, 32
; 16: .cfi_def_cfa_offset 32
; X with -3
define i32 @constraint_X() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_X:
+;CHECK_LITTLE_32-LABEL: constraint_X:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffffffffffffffd
;CHECK_LITTLE_32: #NO_APP
; x with -3
define i32 @constraint_x() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_x:
+;CHECK_LITTLE_32-LABEL: constraint_x:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},0xfffd
;CHECK_LITTLE_32: #NO_APP
; d with -3
define i32 @constraint_d() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_d:
+;CHECK_LITTLE_32-LABEL: constraint_d:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-3
;CHECK_LITTLE_32: #NO_APP
; m with -3
define i32 @constraint_m() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_m:
+;CHECK_LITTLE_32-LABEL: constraint_m:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-4
;CHECK_LITTLE_32: #NO_APP
; z with -3
define i32 @constraint_z() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_z:
+;CHECK_LITTLE_32-LABEL: constraint_z:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},-3
;CHECK_LITTLE_32: #NO_APP
; a long long in 32 bit mode (use to assert)
define i32 @constraint_longlong() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_longlong:
+;CHECK_LITTLE_32-LABEL: constraint_longlong:
;CHECK_LITTLE_32: #APP
;CHECK_LITTLE_32: addi ${{[0-9]+}},${{[0-9]+}},3
;CHECK_LITTLE_32: #NO_APP
; D, in little endian the source reg will be 4 bytes into the long long
define i32 @constraint_D() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_D:
+;CHECK_LITTLE_32-LABEL: constraint_D:
;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_LITTLE_32: #NO_APP
; D, in big endian the source reg will also be 4 bytes into the long long
-;CHECK_BIG_32: constraint_D:
+;CHECK_BIG_32-LABEL: constraint_D:
;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
; L, in little endian the source reg will be 0 bytes into the long long
define i32 @constraint_L() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_L:
+;CHECK_LITTLE_32-LABEL: constraint_L:
;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_LITTLE_32: or ${{[0-9]+}},$[[FIRST]],${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
; L, in big endian the source reg will be 4 bytes into the long long
-;CHECK_BIG_32: constraint_L:
+;CHECK_BIG_32-LABEL: constraint_L:
;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
; M, in little endian the source reg will be 4 bytes into the long long
define i32 @constraint_M() nounwind {
entry:
-;CHECK_LITTLE_32: constraint_M:
+;CHECK_LITTLE_32-LABEL: constraint_M:
;CHECK_LITTLE_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_LITTLE_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_LITTLE_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
;CHECK_LITTLE_32: or ${{[0-9]+}},$[[SECOND]],${{[0-9]+}}
;CHECK_LITTLE_32: #NO_APP
; M, in big endian the source reg will be 0 bytes into the long long
-;CHECK_BIG_32: constraint_M:
+;CHECK_BIG_32-LABEL: constraint_M:
;CHECK_BIG_32: lw ${{[0-9]+}}, %got(uval)(${{[0-9,a-z]+}})
;CHECK_BIG_32: lw $[[SECOND:[0-9]+]], 4(${{[0-9]+}})
;CHECK_BIG_32: lw $[[FIRST:[0-9]+]], 0(${{[0-9]+}})
define i32 @main() nounwind {
entry:
-; 1: main:
+; 1-LABEL: main:
; 1: 1: .word -797992
; 1: li ${{[0-9]+}}, 12
; 1: sll ${{[0-9]+}}, ${{[0-9]+}}, 16
define void @test_addsf3() nounwind {
entry:
-;16hf: test_addsf3:
+;16hf-LABEL: test_addsf3:
%0 = load float* @x, align 4
%1 = load float* @y, align 4
%add = fadd float %0, %1
define void @test_adddf3() nounwind {
entry:
-;16hf: test_adddf3:
+;16hf-LABEL: test_adddf3:
%0 = load double* @xd, align 8
%1 = load double* @yd, align 8
%add = fadd double %0, %1
define void @test_subsf3() nounwind {
entry:
-;16hf: test_subsf3:
+;16hf-LABEL: test_subsf3:
%0 = load float* @x, align 4
%1 = load float* @y, align 4
%sub = fsub float %0, %1
define void @test_subdf3() nounwind {
entry:
-;16hf: test_subdf3:
+;16hf-LABEL: test_subdf3:
%0 = load double* @xd, align 8
%1 = load double* @yd, align 8
%sub = fsub double %0, %1
define void @test_mulsf3() nounwind {
entry:
-;16hf: test_mulsf3:
+;16hf-LABEL: test_mulsf3:
%0 = load float* @x, align 4
%1 = load float* @y, align 4
%mul = fmul float %0, %1
define void @test_muldf3() nounwind {
entry:
-;16hf: test_muldf3:
+;16hf-LABEL: test_muldf3:
%0 = load double* @xd, align 8
%1 = load double* @yd, align 8
%mul = fmul double %0, %1
define void @test_divsf3() nounwind {
entry:
-;16hf: test_divsf3:
+;16hf-LABEL: test_divsf3:
%0 = load float* @y, align 4
%1 = load float* @x, align 4
%div = fdiv float %0, %1
define void @test_divdf3() nounwind {
entry:
-;16hf: test_divdf3:
+;16hf-LABEL: test_divdf3:
%0 = load double* @yd, align 8
%mul = fmul double %0, 2.000000e+00
%1 = load double* @xd, align 8
define void @test_extendsfdf2() nounwind {
entry:
-;16hf: test_extendsfdf2:
+;16hf-LABEL: test_extendsfdf2:
%0 = load float* @x, align 4
%conv = fpext float %0 to double
store double %conv, double* @extendsfdf2_result, align 8
define void @test_truncdfsf2() nounwind {
entry:
-;16hf: test_truncdfsf2:
+;16hf-LABEL: test_truncdfsf2:
%0 = load double* @xd2, align 8
%conv = fptrunc double %0 to float
store float %conv, float* @truncdfsf2_result, align 4
define void @test_fix_truncsfsi() nounwind {
entry:
-;16hf: test_fix_truncsfsi:
+;16hf-LABEL: test_fix_truncsfsi:
%0 = load float* @x, align 4
%conv = fptosi float %0 to i32
store i32 %conv, i32* @fix_truncsfsi_result, align 4
define void @test_fix_truncdfsi() nounwind {
entry:
-;16hf: test_fix_truncdfsi:
+;16hf-LABEL: test_fix_truncdfsi:
%0 = load double* @xd, align 8
%conv = fptosi double %0 to i32
store i32 %conv, i32* @fix_truncdfsi_result, align 4
define void @test_floatsisf() nounwind {
entry:
-;16hf: test_floatsisf:
+;16hf-LABEL: test_floatsisf:
%0 = load i32* @si, align 4
%conv = sitofp i32 %0 to float
store float %conv, float* @floatsisf_result, align 4
define void @test_floatsidf() nounwind {
entry:
-;16hf: test_floatsidf:
+;16hf-LABEL: test_floatsidf:
%0 = load i32* @si, align 4
%conv = sitofp i32 %0 to double
store double %conv, double* @floatsidf_result, align 8
define void @test_floatunsisf() nounwind {
entry:
-;16hf: test_floatunsisf:
+;16hf-LABEL: test_floatunsisf:
%0 = load i32* @ui, align 4
%conv = uitofp i32 %0 to float
store float %conv, float* @floatunsisf_result, align 4
define void @test_floatunsidf() nounwind {
entry:
-;16hf: test_floatunsidf:
+;16hf-LABEL: test_floatunsidf:
%0 = load i32* @ui, align 4
%conv = uitofp i32 %0 to double
store double %conv, double* @floatunsidf_result, align 8
define void @test_eqsf2() nounwind {
entry:
-;16hf: test_eqsf2:
+;16hf-LABEL: test_eqsf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%cmp = fcmp oeq float %0, %1
define void @test_eqdf2() nounwind {
entry:
-;16hf: test_eqdf2:
+;16hf-LABEL: test_eqdf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%cmp = fcmp oeq double %0, %1
define void @test_nesf2() nounwind {
entry:
-;16hf: test_nesf2:
+;16hf-LABEL: test_nesf2:
%0 = load float* @x, align 4
%1 = load float* @y, align 4
%cmp = fcmp une float %0, %1
define void @test_nedf2() nounwind {
entry:
-;16hf: test_nedf2:
+;16hf-LABEL: test_nedf2:
%0 = load double* @xd, align 8
%1 = load double* @yd, align 8
%cmp = fcmp une double %0, %1
define void @test_gesf2() nounwind {
entry:
-;16hf: test_gesf2:
+;16hf-LABEL: test_gesf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%cmp = fcmp oge float %0, %1
define void @test_gedf2() nounwind {
entry:
-;16hf: test_gedf2:
+;16hf-LABEL: test_gedf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%cmp = fcmp oge double %0, %1
define void @test_ltsf2() nounwind {
entry:
-;16hf: test_ltsf2:
+;16hf-LABEL: test_ltsf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%lnot = fcmp uge float %0, %1
define void @test_ltdf2() nounwind {
entry:
-;16hf: test_ltdf2:
+;16hf-LABEL: test_ltdf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%lnot = fcmp uge double %0, %1
define void @test_lesf2() nounwind {
entry:
-;16hf: test_lesf2:
+;16hf-LABEL: test_lesf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%cmp = fcmp ole float %0, %1
define void @test_ledf2() nounwind {
entry:
-;16hf: test_ledf2:
+;16hf-LABEL: test_ledf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%cmp = fcmp ole double %0, %1
define void @test_gtsf2() nounwind {
entry:
-;16hf: test_gtsf2:
+;16hf-LABEL: test_gtsf2:
%0 = load float* @x, align 4
%1 = load float* @xx, align 4
%lnot = fcmp ule float %0, %1
define void @test_gtdf2() nounwind {
entry:
-;16hf: test_gtdf2:
+;16hf-LABEL: test_gtdf2:
%0 = load double* @xd, align 8
%1 = load double* @xxd, align 8
%lnot = fcmp ule double %0, %1
@gf1 = external global float
@gd1 = external global double
-; CHECK: addLD:
+; CHECK-LABEL: addLD:
; CHECK: ld $25, %call16(__addtf3)
define fp128 @addLD() {
ret fp128 %add
}
-; CHECK: subLD:
+; CHECK-LABEL: subLD:
; CHECK: ld $25, %call16(__subtf3)
define fp128 @subLD() {
ret fp128 %sub
}
-; CHECK: mulLD:
+; CHECK-LABEL: mulLD:
; CHECK: ld $25, %call16(__multf3)
define fp128 @mulLD() {
ret fp128 %mul
}
-; CHECK: divLD:
+; CHECK-LABEL: divLD:
; CHECK: ld $25, %call16(__divtf3)
define fp128 @divLD() {
ret fp128 %div
}
-; CHECK: conv_LD_char:
+; CHECK-LABEL: conv_LD_char:
; CHECK: ld $25, %call16(__floatsitf)
define fp128 @conv_LD_char(i8 signext %a) {
ret fp128 %conv
}
-; CHECK: conv_LD_short:
+; CHECK-LABEL: conv_LD_short:
; CHECK: ld $25, %call16(__floatsitf)
define fp128 @conv_LD_short(i16 signext %a) {
ret fp128 %conv
}
-; CHECK: conv_LD_int:
+; CHECK-LABEL: conv_LD_int:
; CHECK: ld $25, %call16(__floatsitf)
define fp128 @conv_LD_int(i32 %a) {
ret fp128 %conv
}
-; CHECK: conv_LD_LL:
+; CHECK-LABEL: conv_LD_LL:
; CHECK: ld $25, %call16(__floatditf)
define fp128 @conv_LD_LL(i64 %a) {
ret fp128 %conv
}
-; CHECK: conv_LD_UChar:
+; CHECK-LABEL: conv_LD_UChar:
; CHECK: ld $25, %call16(__floatunsitf)
define fp128 @conv_LD_UChar(i8 zeroext %a) {
ret fp128 %conv
}
-; CHECK: conv_LD_UShort:
+; CHECK-LABEL: conv_LD_UShort:
; CHECK: ld $25, %call16(__floatunsitf)
define fp128 @conv_LD_UShort(i16 zeroext %a) {
ret fp128 %conv
}
-; CHECK: conv_LD_UInt:
+; CHECK-LABEL: conv_LD_UInt:
; CHECK: ld $25, %call16(__floatunsitf)
define fp128 @conv_LD_UInt(i32 %a) {
ret fp128 %conv
}
-; CHECK: conv_LD_ULL:
+; CHECK-LABEL: conv_LD_ULL:
; CHECK: ld $25, %call16(__floatunditf)
define fp128 @conv_LD_ULL(i64 %a) {
ret fp128 %conv
}
-; CHECK: conv_char_LD:
+; CHECK-LABEL: conv_char_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define signext i8 @conv_char_LD(fp128 %a) {
ret i8 %conv
}
-; CHECK: conv_short_LD:
+; CHECK-LABEL: conv_short_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define signext i16 @conv_short_LD(fp128 %a) {
ret i16 %conv
}
-; CHECK: conv_int_LD:
+; CHECK-LABEL: conv_int_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define i32 @conv_int_LD(fp128 %a) {
ret i32 %conv
}
-; CHECK: conv_LL_LD:
+; CHECK-LABEL: conv_LL_LD:
; CHECK: ld $25, %call16(__fixtfdi)
define i64 @conv_LL_LD(fp128 %a) {
ret i64 %conv
}
-; CHECK: conv_UChar_LD:
+; CHECK-LABEL: conv_UChar_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define zeroext i8 @conv_UChar_LD(fp128 %a) {
ret i8 %conv
}
-; CHECK: conv_UShort_LD:
+; CHECK-LABEL: conv_UShort_LD:
; CHECK: ld $25, %call16(__fixtfsi)
define zeroext i16 @conv_UShort_LD(fp128 %a) {
ret i16 %conv
}
-; CHECK: conv_UInt_LD:
+; CHECK-LABEL: conv_UInt_LD:
; CHECK: ld $25, %call16(__fixunstfsi)
define i32 @conv_UInt_LD(fp128 %a) {
ret i32 %conv
}
-; CHECK: conv_ULL_LD:
+; CHECK-LABEL: conv_ULL_LD:
; CHECK: ld $25, %call16(__fixunstfdi)
define i64 @conv_ULL_LD(fp128 %a) {
ret i64 %conv
}
-; CHECK: conv_LD_float:
+; CHECK-LABEL: conv_LD_float:
; CHECK: ld $25, %call16(__extendsftf2)
define fp128 @conv_LD_float(float %a) {
ret fp128 %conv
}
-; CHECK: conv_LD_double:
+; CHECK-LABEL: conv_LD_double:
; CHECK: ld $25, %call16(__extenddftf2)
define fp128 @conv_LD_double(double %a) {
ret fp128 %conv
}
-; CHECK: conv_float_LD:
+; CHECK-LABEL: conv_float_LD:
; CHECK: ld $25, %call16(__trunctfsf2)
define float @conv_float_LD(fp128 %a) {
ret float %conv
}
-; CHECK: conv_double_LD:
+; CHECK-LABEL: conv_double_LD:
; CHECK: ld $25, %call16(__trunctfdf2)
define double @conv_double_LD(fp128 %a) {
ret double %conv
}
-; CHECK: libcall1_fabsl:
+; CHECK-LABEL: libcall1_fabsl:
; CHECK-DAG: ld $[[R0:[0-9]+]], 8($[[R4:[0-9]+]])
; CHECK-DAG: daddiu $[[R1:[0-9]+]], $zero, 1
; CHECK-DAG: dsll $[[R2:[0-9]+]], $[[R1]], 63
declare fp128 @fabsl(fp128) #1
-; CHECK: libcall1_ceill:
+; CHECK-LABEL: libcall1_ceill:
; CHECK: ld $25, %call16(ceill)
define fp128 @libcall1_ceill() {
declare fp128 @ceill(fp128) #1
-; CHECK: libcall1_sinl:
+; CHECK-LABEL: libcall1_sinl:
; CHECK: ld $25, %call16(sinl)
define fp128 @libcall1_sinl() {
declare fp128 @sinl(fp128) #2
-; CHECK: libcall1_cosl:
+; CHECK-LABEL: libcall1_cosl:
; CHECK: ld $25, %call16(cosl)
define fp128 @libcall1_cosl() {
declare fp128 @cosl(fp128) #2
-; CHECK: libcall1_expl:
+; CHECK-LABEL: libcall1_expl:
; CHECK: ld $25, %call16(expl)
define fp128 @libcall1_expl() {
declare fp128 @expl(fp128) #2
-; CHECK: libcall1_exp2l:
+; CHECK-LABEL: libcall1_exp2l:
; CHECK: ld $25, %call16(exp2l)
define fp128 @libcall1_exp2l() {
declare fp128 @exp2l(fp128) #2
-; CHECK: libcall1_logl:
+; CHECK-LABEL: libcall1_logl:
; CHECK: ld $25, %call16(logl)
define fp128 @libcall1_logl() {
declare fp128 @logl(fp128) #2
-; CHECK: libcall1_log2l:
+; CHECK-LABEL: libcall1_log2l:
; CHECK: ld $25, %call16(log2l)
define fp128 @libcall1_log2l() {
declare fp128 @log2l(fp128) #2
-; CHECK: libcall1_log10l:
+; CHECK-LABEL: libcall1_log10l:
; CHECK: ld $25, %call16(log10l)
define fp128 @libcall1_log10l() {
declare fp128 @log10l(fp128) #2
-; CHECK: libcall1_nearbyintl:
+; CHECK-LABEL: libcall1_nearbyintl:
; CHECK: ld $25, %call16(nearbyintl)
define fp128 @libcall1_nearbyintl() {
declare fp128 @nearbyintl(fp128) #1
-; CHECK: libcall1_floorl:
+; CHECK-LABEL: libcall1_floorl:
; CHECK: ld $25, %call16(floorl)
define fp128 @libcall1_floorl() {
declare fp128 @floorl(fp128) #1
-; CHECK: libcall1_sqrtl:
+; CHECK-LABEL: libcall1_sqrtl:
; CHECK: ld $25, %call16(sqrtl)
define fp128 @libcall1_sqrtl() {
declare fp128 @sqrtl(fp128) #2
-; CHECK: libcall1_rintl:
+; CHECK-LABEL: libcall1_rintl:
; CHECK: ld $25, %call16(rintl)
define fp128 @libcall1_rintl() {
declare fp128 @rintl(fp128) #1
-; CHECK: libcall_powil:
+; CHECK-LABEL: libcall_powil:
; CHECK: ld $25, %call16(__powitf2)
define fp128 @libcall_powil(fp128 %a, i32 %b) {
declare fp128 @llvm.powi.f128(fp128, i32) #3
-; CHECK: libcall2_copysignl:
+; CHECK-LABEL: libcall2_copysignl:
; CHECK-DAG: daddiu $[[R2:[0-9]+]], $zero, 1
; CHECK-DAG: dsll $[[R3:[0-9]+]], $[[R2]], 63
; CHECK-DAG: ld $[[R0:[0-9]+]], %got_disp(gld1)
declare fp128 @copysignl(fp128, fp128) #1
-; CHECK: libcall2_powl:
+; CHECK-LABEL: libcall2_powl:
; CHECK: ld $25, %call16(powl)
define fp128 @libcall2_powl() {
declare fp128 @powl(fp128, fp128) #2
-; CHECK: libcall2_fmodl:
+; CHECK-LABEL: libcall2_fmodl:
; CHECK: ld $25, %call16(fmodl)
define fp128 @libcall2_fmodl() {
declare fp128 @fmodl(fp128, fp128) #2
-; CHECK: libcall3_fmal:
+; CHECK-LABEL: libcall3_fmal:
; CHECK: ld $25, %call16(fmal)
define fp128 @libcall3_fmal() {
declare fp128 @llvm.fma.f128(fp128, fp128, fp128) #4
-; CHECK: cmp_lt:
+; CHECK-LABEL: cmp_lt:
; CHECK: ld $25, %call16(__lttf2)
define i32 @cmp_lt(fp128 %a, fp128 %b) {
ret i32 %conv
}
-; CHECK: cmp_le:
+; CHECK-LABEL: cmp_le:
; CHECK: ld $25, %call16(__letf2)
define i32 @cmp_le(fp128 %a, fp128 %b) {
ret i32 %conv
}
-; CHECK: cmp_gt:
+; CHECK-LABEL: cmp_gt:
; CHECK: ld $25, %call16(__gttf2)
define i32 @cmp_gt(fp128 %a, fp128 %b) {
ret i32 %conv
}
-; CHECK: cmp_ge:
+; CHECK-LABEL: cmp_ge:
; CHECK: ld $25, %call16(__getf2)
define i32 @cmp_ge(fp128 %a, fp128 %b) {
ret i32 %conv
}
-; CHECK: cmp_eq:
+; CHECK-LABEL: cmp_eq:
; CHECK: ld $25, %call16(__eqtf2)
define i32 @cmp_eq(fp128 %a, fp128 %b) {
ret i32 %conv
}
-; CHECK: cmp_ne:
+; CHECK-LABEL: cmp_ne:
; CHECK: ld $25, %call16(__netf2)
define i32 @cmp_ne(fp128 %a, fp128 %b) {
ret i32 %conv
}
-; CHECK: load_LD_LD:
+; CHECK-LABEL: load_LD_LD:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
; CHECK: ld $2, 0($[[R0]])
; CHECK: ld $4, 8($[[R0]])
ret fp128 %0
}
-; CHECK: load_LD_float:
+; CHECK-LABEL: load_LD_float:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gf1)
; CHECK: lw $4, 0($[[R0]])
; CHECK: ld $25, %call16(__extendsftf2)
ret fp128 %conv
}
-; CHECK: load_LD_double:
+; CHECK-LABEL: load_LD_double:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gd1)
; CHECK: ld $4, 0($[[R0]])
; CHECK: ld $25, %call16(__extenddftf2)
ret fp128 %conv
}
-; CHECK: store_LD_LD:
+; CHECK-LABEL: store_LD_LD:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
; CHECK: ld $[[R1:[0-9]+]], 0($[[R0]])
; CHECK: ld $[[R2:[0-9]+]], 8($[[R0]])
ret void
}
-; CHECK: store_LD_float:
+; CHECK-LABEL: store_LD_float:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
; CHECK: ld $4, 0($[[R0]])
; CHECK: ld $5, 8($[[R0]])
ret void
}
-; CHECK: store_LD_double:
+; CHECK-LABEL: store_LD_double:
; CHECK: ld $[[R0:[0-9]+]], %got_disp(gld1)
; CHECK: ld $4, 0($[[R0]])
; CHECK: ld $5, 8($[[R0]])
ret void
}
-; CHECK: select_LD:
+; CHECK-LABEL: select_LD:
; CHECK: movn $8, $6, $4
; CHECK: movn $9, $7, $4
; CHECK: move $2, $8
ret fp128 %cond
}
-; CHECK: selectCC_LD:
+; CHECK-LABEL: selectCC_LD:
; CHECK: move $[[R0:[0-9]+]], $11
; CHECK: move $[[R1:[0-9]+]], $10
; CHECK: move $[[R2:[0-9]+]], $9
; Check that %add is not passed in an integer register.
;
-; HARD: callfloor:
+; HARD-LABEL: callfloor:
; HARD-NOT: dmfc1 $4
define double @callfloor(double %d) nounwind readnone {
; Check call16.
;
-; SOFT: f64add:
+; SOFT-LABEL: f64add:
; SOFT: ld $25, %call16(__adddf3)
define double @f64add(double %a, double %b) {
define i64 @f14(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; CHECK: teq $[[R0]], $zero, 7
; CHECK: mflo
define i64 @f15(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; CHECK: teq $[[R0]], $zero, 7
; CHECK: mflo
define i64 @f16(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: ddiv $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; CHECK: teq $[[R0]], $zero, 7
; CHECK: mfhi
define i64 @f17(i64 %a, i64 %b) nounwind readnone {
entry:
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: ddivu $zero, ${{[0-9]+}}, $[[R0:[0-9]+]]
; CHECK: teq $[[R0]], $zero, 7
; CHECK: mfhi
%inc = add nsw i32 %i.010, 1
%cmp = icmp eq i32 %inc, %conv
br i1 %cmp, label %for.end, label %for.body
-; 16: sumc:
+; 16-LABEL: sumc:
; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
; 16: lbu ${{[0-9]+}}, 0(${{[0-9]+}})
-; 16: sum:
+; 16-LABEL: sum:
; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
; 16: lhu ${{[0-9]+}}, 0(${{[0-9]+}})
@g0 = common global double 0.000000e+00, align 8
-; LE-PIC: test_ldc1:
+; LE-PIC-LABEL: test_ldc1:
; LE-PIC: lwc1 $f0, 0(${{[0-9]+}})
; LE-PIC: lwc1 $f1, 4(${{[0-9]+}})
-; LE-STATIC: test_ldc1:
+; LE-STATIC-LABEL: test_ldc1:
; LE-STATIC: lwc1 $f0, %lo(g0)(${{[0-9]+}})
; LE-STATIC: lwc1 $f1, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_ldc1:
+; BE-PIC-LABEL: test_ldc1:
; BE-PIC: lwc1 $f1, 0(${{[0-9]+}})
; BE-PIC: lwc1 $f0, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_ldc1:
+; CHECK-LDC1-SDC1-LABEL: test_ldc1:
; CHECK-LDC1-SDC1: ldc1 $f{{[0-9]+}}
define double @test_ldc1() {
ret double %0
}
-; LE-PIC: test_sdc1:
+; LE-PIC-LABEL: test_sdc1:
; LE-PIC: swc1 $f12, 0(${{[0-9]+}})
; LE-PIC: swc1 $f13, 4(${{[0-9]+}})
-; LE-STATIC: test_sdc1:
+; LE-STATIC-LABEL: test_sdc1:
; LE-STATIC: swc1 $f12, %lo(g0)(${{[0-9]+}})
; LE-STATIC: swc1 $f13, %lo(g0+4)(${{[0-9]+}})
-; BE-PIC: test_sdc1:
+; BE-PIC-LABEL: test_sdc1:
; BE-PIC: swc1 $f13, 0(${{[0-9]+}})
; BE-PIC: swc1 $f12, 4(${{[0-9]+}})
-; CHECK-LDC1-SDC1: test_sdc1:
+; CHECK-LDC1-SDC1-LABEL: test_sdc1:
; CHECK-LDC1-SDC1: sdc1 $f{{[0-9]+}}
define void @test_sdc1(double %a) {
%tmp = load i32* %b, align 4
ret i32 %tmp
-; CHECK: va1:
+; CHECK-LABEL: va1:
; CHECK: addiu $sp, $sp, -16
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
%tmp = load double* %b, align 8
ret double %tmp
-; CHECK: va2:
+; CHECK-LABEL: va2:
; CHECK: addiu $sp, $sp, -16
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
%tmp = load i32* %b, align 4
ret i32 %tmp
-; CHECK: va3:
+; CHECK-LABEL: va3:
; CHECK: addiu $sp, $sp, -16
; CHECK: sw $7, 28($sp)
; CHECK: sw $6, 24($sp)
%tmp = load double* %b, align 8
ret double %tmp
-; CHECK: va4:
+; CHECK-LABEL: va4:
; CHECK: addiu $sp, $sp, -24
; CHECK: sw $7, 36($sp)
; CHECK: sw $6, 32($sp)
%tmp = load i32* %d, align 4
ret i32 %tmp
-; CHECK: va5:
+; CHECK-LABEL: va5:
; CHECK: addiu $sp, $sp, -24
; CHECK: sw $7, 36($sp)
; CHECK: lw $2, 36($sp)
%tmp = load double* %d, align 8
ret double %tmp
-; CHECK: va6:
+; CHECK-LABEL: va6:
; CHECK: addiu $sp, $sp, -24
; CHECK: sw $7, 36($sp)
; CHECK: addiu $[[R0:[0-9]+]], $sp, 36
%tmp = load i32* %c, align 4
ret i32 %tmp
-; CHECK: va7:
+; CHECK-LABEL: va7:
; CHECK: addiu $sp, $sp, -24
; CHECK: lw $2, 40($sp)
}
%tmp = load double* %c, align 8
ret double %tmp
-; CHECK: va8:
+; CHECK-LABEL: va8:
; CHECK: addiu $sp, $sp, -32
; CHECK: addiu ${{[0-9]+}}, $sp, 48
; CHECK: ldc1 $f0, 48($sp)
%tmp = load i32* %d, align 4
ret i32 %tmp
-; CHECK: va9:
+; CHECK-LABEL: va9:
; CHECK: addiu $sp, $sp, -32
; CHECK: lw $2, 52($sp)
}
%tmp = load double* %d, align 8
ret double %tmp
-; CHECK: va10:
+; CHECK-LABEL: va10:
; CHECK: addiu $sp, $sp, -32
; CHECK: addiu $[[R0:[0-9]+]], $sp, 52
; CHECK: addiu $[[R1:[0-9]+]], $[[R0]], 7
; RUN: llc -march=mips < %s | FileCheck %s
define private void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
ret void
}
@baz = private global i32 4
define i32 @bar() {
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: call16($foo)
; CHECK: lw $[[R0:[0-9]+]], %got($baz)($
; CHECK: lw ${{[0-9]+}}, %lo($baz)($[[R0]])
%add7 = add i32 %add5, %add6
ret i32 %add7
-; CHECK: call_i8:
+; CHECK-LABEL: call_i8:
; CHECK: call16(i8)
; CHECK: addiu $4, $sp, 32
; CHECK: lw $[[R0:[a-z0-9]+]], 60($sp)
%add3 = fadd float %add1, %add2
ret float %add3
-; CHECK: call_f4:
+; CHECK-LABEL: call_f4:
; CHECK: call16(f4)
; CHECK: addiu $4, $sp, 16
; CHECK: lwc1 $[[R0:[a-z0-9]+]], 28($sp)
%add3 = fadd double %add1, %add2
ret double %add3
-; CHECK: call_d4:
+; CHECK-LABEL: call_d4:
; CHECK: call16(d4)
; CHECK: addiu $4, $sp, 32
; CHECK: ldc1 $[[R0:[a-z0-9]+]], 56($sp)
%add3 = add i32 %add1, %add2
ret i32 %add3
-; CHECK: call_i4:
+; CHECK-LABEL: call_i4:
; CHECK: call16(i4)
; CHECK-NOT: lw
; CHECK: addu $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
%add1 = fadd float %v0, %v1
ret float %add1
-; CHECK: call_f2:
+; CHECK-LABEL: call_f2:
; CHECK: call16(f2)
; CHECK-NOT: lwc1
; CHECK: add.s $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
%add1 = fadd double %v0, %v1
ret double %add1
-; CHECK: call_d2:
+; CHECK-LABEL: call_d2:
; CHECK: call16(d2)
; CHECK-NOT: ldc1
; CHECK: add.d $[[R2:[a-z0-9]+]], $[[R0:[a-z0-9]+]], $[[R1:[a-z0-9]+]]
entry:
ret <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
-; CHECK: return_i8:
+; CHECK-LABEL: return_i8:
; CHECK: sw $[[R0:[a-z0-9]+]], 28($4)
; CHECK: sw $[[R1:[a-z0-9]+]], 24($4)
; CHECK: sw $[[R2:[a-z0-9]+]], 20($4)
%vecins4 = insertelement <4 x float> %vecins3, float %d, i32 3
ret <4 x float> %vecins4
-; CHECK: return_f4:
+; CHECK-LABEL: return_f4:
; CHECK-DAG: lwc1 $[[R0:[a-z0-9]+]], 16($sp)
; CHECK-DAG: swc1 $[[R0]], 12($4)
; CHECK-DAG: sw $7, 8($4)
%vecins4 = insertelement <4 x double> %vecins3, double %d, i32 3
ret <4 x double> %vecins4
-; CHECK: return_d4:
+; CHECK-LABEL: return_d4:
; CHECK-DAG: sdc1 $[[R0:[a-z0-9]+]], 24($4)
; CHECK-DAG: sdc1 $[[R1:[a-z0-9]+]], 16($4)
; CHECK-DAG: sdc1 $[[R2:[a-z0-9]+]], 8($4)
entry:
ret <4 x i32> <i32 0, i32 1, i32 2, i32 3>
-; CHECK: return_i4:
+; CHECK-LABEL: return_i4:
; CHECK: addiu $2, $zero, 0
; CHECK: addiu $3, $zero, 1
; CHECK: addiu $4, $zero, 2
%vecins2 = insertelement <2 x float> %vecins1, float %b, i32 1
ret <2 x float> %vecins2
-; CHECK: return_f2:
+; CHECK-LABEL: return_f2:
; CHECK: mov.s $f0, $f12
; CHECK: mov.s $f2, $f14
}
%vecins2 = insertelement <2 x double> %vecins1, double %b, i32 1
ret <2 x double> %vecins2
-; CHECK: return_d2:
+; CHECK-LABEL: return_d2:
; CHECK: mov.d $f0, $f12
; CHECK: mov.d $f2, $f14
}
@g1 = external global i32
-; CHECK: seteq0:
+; CHECK-LABEL: seteq0:
; CHECK: sltiu ${{[0-9]+}}, $4, 1
define i32 @seteq0(i32 %a) {
ret i32 %conv
}
-; CHECK: setne0:
+; CHECK-LABEL: setne0:
; CHECK: sltu ${{[0-9]+}}, $zero, $4
define i32 @setne0(i32 %a) {
ret i32 %conv
}
-; CHECK: slti_beq0:
+; CHECK-LABEL: slti_beq0:
; CHECK: slti $[[R0:[0-9]+]], $4, -32768
; CHECK: beq $[[R0]], $zero
ret void
}
-; CHECK: slti_beq1:
+; CHECK-LABEL: slti_beq1:
; CHECK: slt ${{[0-9]+}}
define void @slti_beq1(i32 %a) {
ret void
}
-; CHECK: slti_beq2:
+; CHECK-LABEL: slti_beq2:
; CHECK: slti $[[R0:[0-9]+]], $4, 32767
; CHECK: beq $[[R0]], $zero
ret void
}
-; CHECK: slti_beq3:
+; CHECK-LABEL: slti_beq3:
; CHECK: slt ${{[0-9]+}}
define void @slti_beq3(i32 %a) {
ret void
}
-; CHECK: sltiu_beq0:
+; CHECK-LABEL: sltiu_beq0:
; CHECK: sltiu $[[R0:[0-9]+]], $4, 32767
; CHECK: beq $[[R0]], $zero
ret void
}
-; CHECK: sltiu_beq1:
+; CHECK-LABEL: sltiu_beq1:
; CHECK: sltu ${{[0-9]+}}
define void @sltiu_beq1(i32 %a) {
ret void
}
-; CHECK: sltiu_beq2:
+; CHECK-LABEL: sltiu_beq2:
; CHECK: sltiu $[[R0:[0-9]+]], $4, -32768
; CHECK: beq $[[R0]], $zero
ret void
}
-; CHECK: sltiu_beq3:
+; CHECK-LABEL: sltiu_beq3:
; CHECK: sltu ${{[0-9]+}}
define void @sltiu_beq3(i32 %a) {
@gint_ = external global i32
@gLL_ = external global i64
-; 32: store_int_float_:
+; 32-LABEL: store_int_float_:
; 32: trunc.w.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 32: swc1 $f[[R0]],
ret void
}
-; 32: store_int_double_:
+; 32-LABEL: store_int_double_:
; 32: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 32: swc1 $f[[R0]],
-; 64: store_int_double_:
+; 64-LABEL: store_int_double_:
; 64: trunc.w.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 64: swc1 $f[[R0]],
ret void
}
-; 64: store_LL_float_:
+; 64-LABEL: store_LL_float_:
; 64: trunc.l.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 64: sdc1 $f[[R0]],
ret void
}
-; 64: store_LL_double_:
+; 64-LABEL: store_LL_double_:
; 64: trunc.l.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
; 64: sdc1 $f[[R0]],
@g1 = external global i32*
-; CHECK: foo1:
+; CHECK-LABEL: foo1:
; CHECK: lw ${{[0-9]+}}, %got(g1)
; CHECK: # %for.body
; CHECK: # %for.end
%conv1.i = sext i8 %3 to i32
%call.i = call i32 (i8*, ...)* @printf(i8* getelementptr inbounds ([9 x i8]* @.str, i32 0, i32 0), i32 %conv.i, i32 %conv1.i) nounwind
ret void
-; 16_b: test:
-; 16_h: test:
+; 16_b-LABEL: test:
+; 16_h-LABEL: test:
; 16_b: sb ${{[0-9]+}}, [[offset1:[0-9]+]](${{[0-9]+}})
; 16_b: lb ${{[0-9]+}}, [[offset1]](${{[0-9]+}})
; 16_h: sh ${{[0-9]+}}, [[offset2:[0-9]+]](${{[0-9]+}})
ret i32* @external_gd
; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
- ; CHECK-NONPIC: f1:
+ ; CHECK-NONPIC-LABEL: f1:
; CHECK-NONPIC: %gottprel
- ; CHECK-PIC: f1:
+ ; CHECK-PIC-LABEL: f1:
; CHECK-PIC: %tlsgd
}
ret i32* @internal_gd
; Non-PIC code can use local exec, PIC code can use local dynamic.
- ; CHECK-NONPIC: f2:
+ ; CHECK-NONPIC-LABEL: f2:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f2:
+ ; CHECK-PIC-LABEL: f2:
; CHECK-PIC: %tlsldm
}
ret i32* @external_ld
; Non-PIC code can use initial exec, PIC should use local dynamic.
- ; CHECK-NONPIC: f3:
+ ; CHECK-NONPIC-LABEL: f3:
; CHECK-NONPIC: %gottprel
- ; CHECK-PIC: f3:
+ ; CHECK-PIC-LABEL: f3:
; CHECK-PIC: %tlsldm
}
ret i32* @internal_ld
; Non-PIC code can use local exec, PIC code can use local dynamic.
- ; CHECK-NONPIC: f4:
+ ; CHECK-NONPIC-LABEL: f4:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f4:
+ ; CHECK-PIC-LABEL: f4:
; CHECK-PIC: %tlsldm
}
ret i32* @external_ie
; Non-PIC and PIC code will use initial exec as specified.
- ; CHECK-NONPIC: f5:
+ ; CHECK-NONPIC-LABEL: f5:
; CHECK-NONPIC: %gottprel
- ; CHECK-PIC: f5:
+ ; CHECK-PIC-LABEL: f5:
; CHECK-PIC: %gottprel
}
ret i32* @internal_ie
; Non-PIC code can use local exec, PIC code use initial exec as specified.
- ; CHECK-NONPIC: f6:
+ ; CHECK-NONPIC-LABEL: f6:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f6:
+ ; CHECK-PIC-LABEL: f6:
; CHECK-PIC: %gottprel
}
ret i32* @external_le
; Non-PIC and PIC code will use local exec as specified.
- ; CHECK-NONPIC: f7:
+ ; CHECK-NONPIC-LABEL: f7:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f7:
+ ; CHECK-PIC-LABEL: f7:
; CHECK-PIC: %tprel_hi
}
ret i32* @internal_le
; Non-PIC and PIC code will use local exec as specified.
- ; CHECK-NONPIC: f8:
+ ; CHECK-NONPIC-LABEL: f8:
; CHECK-NONPIC: %tprel_hi
- ; CHECK-PIC: f8:
+ ; CHECK-PIC-LABEL: f8:
; CHECK-PIC: %tprel_hi
}
%tmp = load i32* @t1, align 4
ret i32 %tmp
-; PIC: f1:
+; PIC-LABEL: f1:
; PIC-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
; PIC-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
; PIC-DAG: addiu $4, $[[R0]], %tlsgd(t1)
; PIC-DAG: jalr $25
; PIC-DAG: lw $2, 0($2)
-; STATIC: f1:
+; STATIC-LABEL: f1:
; STATIC: lui $[[R0:[0-9]+]], %tprel_hi(t1)
; STATIC: addiu $[[R1:[0-9]+]], $[[R0]], %tprel_lo(t1)
; STATIC: rdhwr $3, $29
%tmp = load i32* @t2, align 4
ret i32 %tmp
-; PIC: f2:
+; PIC-LABEL: f2:
; PIC-DAG: addu $[[R0:[a-z0-9]+]], $2, $25
; PIC-DAG: lw $25, %call16(__tls_get_addr)($[[R0]])
; PIC-DAG: addiu $4, $[[R0]], %tlsgd(t2)
; PIC-DAG: jalr $25
; PIC-DAG: lw $2, 0($2)
-; STATICGP: f2:
+; STATICGP-LABEL: f2:
; STATICGP: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
; STATICGP: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
; STATICGP: lw ${{[0-9]+}}, %gottprel(t2)($[[GP]])
-; STATIC: f2:
+; STATIC-LABEL: f2:
; STATIC: lui $[[R0:[0-9]+]], %hi(__gnu_local_gp)
; STATIC: addiu $[[GP:[0-9]+]], $[[R0]], %lo(__gnu_local_gp)
; STATIC: rdhwr $3, $29
define i32 @f3() nounwind {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; PIC: addiu $4, ${{[a-z0-9]+}}, %tlsldm(f3.i)
; PIC: jalr $25
}
; CHECK: .ent tnaked
-; CHECK: tnaked:
+; CHECK-LABEL: tnaked:
; CHECK-NOT: .frame {{.*}}
; CHECK-NOT: .mask {{.*}}
; CHECK-NOT: .fmask {{.*}}
}
; CHECK: .ent tnonaked
-; CHECK: tnonaked:
+; CHECK-LABEL: tnonaked:
; CHECK: .frame $fp,8,$ra
; CHECK: .mask 0x40000000,-4
; CHECK: .fmask 0x00000000,0
define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: subfc
; CHECK: subfe
; CHECK: subfc
define i32 @main() nounwind {
entry:
; Make sure we're generating references using the red zone
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: stw r2, -12(r1)
%retval = alloca i32
%0 = alloca i32
entry:
%tmp.2 = add i64 %b, %a ; <i64> [#uses=1]
ret i64 %tmp.2
-; CHECK: add_ll:
+; CHECK-LABEL: add_ll:
; CHECK: addc r4, r6, r4
; CHECK: adde r3, r5, r3
; CHECK: blr
entry:
%tmp.1 = add i64 %a, 5 ; <i64> [#uses=1]
ret i64 %tmp.1
-; CHECK: add_l_5:
+; CHECK-LABEL: add_l_5:
; CHECK: addic r4, r4, 5
; CHECK: addze r3, r3
; CHECK: blr
entry:
%tmp.1 = add i64 %a, -5 ; <i64> [#uses=1]
ret i64 %tmp.1
-; CHECK: add_l_m5:
+; CHECK-LABEL: add_l_m5:
; CHECK: addic r4, r4, -5
; CHECK: addme r3, r3
; CHECK: blr
ret i8* %ptr
}
-; CHECK: func1:
+; CHECK-LABEL: func1:
; CHECK: cmpld {{[0-9]+}}, 4, 5
; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
ret i8* %array2_ptr
}
-; CHECK: func2:
+; CHECK-LABEL: func2:
; CHECK: addi [[REG1:[0-9]+]], 1, 64
; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
ret i8* %array2_ptr
}
-; CHECK: func3:
+; CHECK-LABEL: func3:
; CHECK: addi [[REG1:[0-9]+]], 1, 64
; CHECK: addi [[REG2:[0-9]+]], 1, 48
; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
ret i8* %array2_ptr
}
-; CHECK: func4:
+; CHECK-LABEL: func4:
; CHECK: addi [[REG1:[0-9]+]], 1, 128
; CHECK: ld [[REG2:[0-9]+]], 120(1)
; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 | FileCheck %s
define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}}
%tmp = atomicrmw add i32* %mem, i32 %val monotonic
; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}}
}
define i32 @exchange_and_cmp(i32* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
; CHECK: lwarx
%tmp = cmpxchg i32* %mem, i32 0, i32 1 monotonic
; CHECK: stwcx.
}
define i32 @exchange(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
; CHECK: lwarx
%tmp = atomicrmw xchg i32* %mem, i32 1 monotonic
; CHECK: stwcx.
; RUN: llc < %s -march=ppc64 | FileCheck %s
define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
; CHECK: ldarx
%tmp = atomicrmw add i64* %mem, i64 %val monotonic
; CHECK: stdcx.
}
define i64 @exchange_and_cmp(i64* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
; CHECK: ldarx
%tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic
; CHECK: stdcx.
}
define i64 @exchange(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
; CHECK: ldarx
%tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
; CHECK: stdcx.
ret { ppc_fp128, ppc_fp128 } %0
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: lfd 3
; CHECK: lfd 4
; CHECK: lfd 2
ret { float, float } %0
}
-; CHECK: oof:
+; CHECK-LABEL: oof:
; CHECK: lfs 2
; CHECK: lfs 1
; RUN: llc < %s -break-anti-dependencies=all -march=ppc64 -mcpu=g5 | FileCheck %s
-; CHECK: main:
+; CHECK-LABEL: main:
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"
ret void
}
-; CHECK: callee:
+; CHECK-LABEL: callee:
; CHECK: std 4,
; CHECK-NOT: std 5,
; CHECK-NOT: std 6,
ret void
}
-; CHECK: caller:
+; CHECK-LABEL: caller:
; CHECK: addi 4,
; CHECK-NOT: std 5,
; CHECK-NOT: std 6,
@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
define internal i32 @foo(i32 %i) nounwind {
-; PIC: foo:
-; STATIC: foo:
-; PPC64: foo:
+; PIC-LABEL: foo:
+; STATIC-LABEL: foo:
+; PPC64-LABEL: foo:
entry:
%0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
define i64 @access_int64(i64 %a) nounwind readonly {
entry:
-; CHECK: access_int64:
+; CHECK-LABEL: access_int64:
; CHECK-NEXT: .align 3
; CHECK-NEXT: .quad .L.access_int64
; CHECK-NEXT: .quad .TOC.@tocbase
define i64 @internal_static_var(i64 %a) nounwind {
entry:
-; CHECK: internal_static_var:
+; CHECK-LABEL: internal_static_var:
; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
%0 = load i64* @internal_static_var.x, align 8
%cmp = icmp eq i64 %0, %a
define i32 @access_double(double %a) nounwind readnone {
entry:
-; CHECK: access_double:
+; CHECK-LABEL: access_double:
; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
%cmp = fcmp oeq double %a, 2.000000e+00
%conv = zext i1 %cmp to i32
define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
entry:
-; CHECK: access_double_array:
+; CHECK-LABEL: access_double_array:
%idxprom = sext i32 %i to i64
%arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
%0 = load double* %arrayidx, align 8
%struct.foo = type { i8, i8 }
define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline {
-; CHECK: _Z5check3foos:
+; CHECK-LABEL: _Z5check3foos:
; CHECK: sth 3, {{[0-9]+}}(1)
; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1)
entry:
; CHECK-LABEL: test1:
; CHECK: frim 1, 1
-; CHECK-FM: test1:
+; CHECK-FM-LABEL: test1:
; CHECK-FM: frim 1, 1
}
; CHECK-LABEL: test2:
; CHECK: frim 1, 1
-; CHECK-FM: test2:
+; CHECK-FM-LABEL: test2:
; CHECK-FM: frim 1, 1
}
; CHECK-LABEL: test3:
; CHECK-NOT: frin
-; CHECK-FM: test3:
+; CHECK-FM-LABEL: test3:
; CHECK-FM: frin 1, 1
}
; CHECK-LABEL: test4:
; CHECK-NOT: frin
-; CHECK-FM: test4:
+; CHECK-FM-LABEL: test4:
; CHECK-FM: frin 1, 1
}
; CHECK-LABEL: test5:
; CHECK: frip 1, 1
-; CHECK-FM: test5:
+; CHECK-FM-LABEL: test5:
; CHECK-FM: frip 1, 1
}
; CHECK-LABEL: test6:
; CHECK: frip 1, 1
-; CHECK-FM: test6:
+; CHECK-FM-LABEL: test6:
; CHECK-FM: frip 1, 1
}
; CHECK-LABEL: test9:
; CHECK: friz 1, 1
-; CHECK-FM: test9:
+; CHECK-FM-LABEL: test9:
; CHECK-FM: friz 1, 1
}
; CHECK-LABEL: test10:
; CHECK: friz 1, 1
-; CHECK-FM: test10:
+; CHECK-FM-LABEL: test10:
; CHECK-FM: friz 1, 1
}
; CHECK-LABEL: test11:
; CHECK-NOT: frin
-; CHECK-FM: test11:
+; CHECK-FM-LABEL: test11:
; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
; CHECK-LABEL: test12:
; CHECK-NOT: frin
-; CHECK-FM: test12:
+; CHECK-FM-LABEL: test12:
; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
%0 = add i32 1, 2
ret void
}
-; PPC32: regalloc:
+; PPC32-LABEL: regalloc:
; PPC32-NOT: stwu 1, -{{[0-9]+}}(1)
; PPC32: blr
-; PPC64: regalloc:
+; PPC64-LABEL: regalloc:
; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
; PPC64: blr
%0 = alloca i8, i32 4
ret void
}
-; PPC32: smallstack:
+; PPC32-LABEL: smallstack:
; PPC32: stwu 1, -16(1)
-; PPC64: smallstack:
+; PPC64-LABEL: smallstack:
; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
; PPC64: blr
%0 = alloca i8, i32 230
ret void
}
-; PPC32: bigstack:
+; PPC32-LABEL: bigstack:
; PPC32: stwu 1, -240(1)
-; PPC64: bigstack:
+; PPC64-LABEL: bigstack:
; PPC64: stdu 1, -352(1)
@a = thread_local global i32 0, align 4
-;CHECK: localexec:
+;CHECK-LABEL: localexec:
define i32 @localexec() nounwind {
entry:
;CHECK: addis [[REG1:[0-9]+]], 13, a@tprel@ha
@a = thread_local global i32 0, align 4
-;OPT0: localexec:
-;OPT1: localexec:
+;OPT0-LABEL: localexec:
+;OPT1-LABEL: localexec:
define i32 @localexec() nounwind {
entry:
;OPT0: addis [[REG1:[0-9]+]], 13, a@tprel@ha
%sext = sext <2 x i1> %cmp to <2 x i8>
ret <2 x i8> %sext
}
-; CHECK: v2si8_cmp:
+; CHECK-LABEL: v2si8_cmp:
; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <4 x i1> %cmp to <4 x i8>
ret <4 x i8> %sext
}
-; CHECK: v4si8_cmp:
+; CHECK-LABEL: v4si8_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <8 x i1> %cmp to <8 x i8>
ret <8 x i8> %sext
}
-; CHECK: v8si8_cmp:
+; CHECK-LABEL: v8si8_cmp:
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_eq:
+; CHECK-LABEL: v16si8_cmp_eq:
; CHECK: vcmpequb 2, 2, 3
define <16 x i8> @v16si8_cmp_ne(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_ne:
+; CHECK-LABEL: v16si8_cmp_ne:
; CHECK: vcmpequb [[RET:[0-9]+]], 2, 3
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_le:
+; CHECK-LABEL: v16si8_cmp_le:
; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16ui8_cmp_le:
+; CHECK-LABEL: v16ui8_cmp_le:
; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_lt:
+; CHECK-LABEL: v16si8_cmp_lt:
; CHECK: vcmpgtsb 2, 3, 2
define <16 x i8> @v16ui8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16ui8_cmp_lt:
+; CHECK-LABEL: v16ui8_cmp_lt:
; CHECK: vcmpgtub 2, 3, 2
define <16 x i8> @v16si8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_gt:
+; CHECK-LABEL: v16si8_cmp_gt:
; CHECK: vcmpgtsb 2, 2, 3
define <16 x i8> @v16ui8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16ui8_cmp_gt:
+; CHECK-LABEL: v16ui8_cmp_gt:
; CHECK: vcmpgtub 2, 2, 3
define <16 x i8> @v16si8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16si8_cmp_ge:
+; CHECK-LABEL: v16si8_cmp_ge:
; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
}
-; CHECK: v16ui8_cmp_ge:
+; CHECK-LABEL: v16ui8_cmp_ge:
; CHECK: vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
%sext = sext <32 x i1> %cmp to <32 x i8>
ret <32 x i8> %sext
}
-; CHECK: v32si8_cmp:
+; CHECK-LABEL: v32si8_cmp:
; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <2 x i1> %cmp to <2 x i16>
ret <2 x i16> %sext
}
-; CHECK: v2si16_cmp:
+; CHECK-LABEL: v2si16_cmp:
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <4 x i1> %cmp to <4 x i16>
ret <4 x i16> %sext
}
-; CHECK: v4si16_cmp:
+; CHECK-LABEL: v4si16_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_eq:
+; CHECK-LABEL: v8si16_cmp_eq:
; CHECK: vcmpequh 2, 2, 3
define <8 x i16> @v8si16_cmp_ne(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_ne:
+; CHECK-LABEL: v8si16_cmp_ne:
; CHECK: vcmpequh [[RET:[0-9]+]], 2, 3
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_le:
+; CHECK-LABEL: v8si16_cmp_le:
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8ui16_cmp_le:
+; CHECK-LABEL: v8ui16_cmp_le:
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_lt:
+; CHECK-LABEL: v8si16_cmp_lt:
; CHECK: vcmpgtsh 2, 3, 2
define <8 x i16> @v8ui16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8ui16_cmp_lt:
+; CHECK-LABEL: v8ui16_cmp_lt:
; CHECK: vcmpgtuh 2, 3, 2
define <8 x i16> @v8si16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_gt:
+; CHECK-LABEL: v8si16_cmp_gt:
; CHECK: vcmpgtsh 2, 2, 3
define <8 x i16> @v8ui16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8ui16_cmp_gt:
+; CHECK-LABEL: v8ui16_cmp_gt:
; CHECK: vcmpgtuh 2, 2, 3
define <8 x i16> @v8si16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8si16_cmp_ge:
+; CHECK-LABEL: v8si16_cmp_ge:
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
}
-; CHECK: v8ui16_cmp_ge:
+; CHECK-LABEL: v8ui16_cmp_ge:
; CHECK: vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
%sext = sext <16 x i1> %cmp to <16 x i16>
ret <16 x i16> %sext
}
-; CHECK: v16si16_cmp:
+; CHECK-LABEL: v16si16_cmp:
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <32 x i1> %cmp to <32 x i16>
ret <32 x i16> %sext
}
-; CHECK: v32si16_cmp:
+; CHECK-LABEL: v32si16_cmp:
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <2 x i1> %cmp to <2 x i32>
ret <2 x i32> %sext
}
-; CHECK: v2si32_cmp:
+; CHECK-LABEL: v2si32_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_eq:
+; CHECK-LABEL: v4si32_cmp_eq:
; CHECK: vcmpequw 2, 2, 3
define <4 x i32> @v4si32_cmp_ne(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_ne:
+; CHECK-LABEL: v4si32_cmp_ne:
; CHECK: vcmpequw [[RCMP:[0-9]+]], 2, 3
; CHECK-NEXT: vnor 2, [[RCMP]], [[RCMP]]
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_le:
+; CHECK-LABEL: v4si32_cmp_le:
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4ui32_cmp_le:
+; CHECK-LABEL: v4ui32_cmp_le:
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_lt:
+; CHECK-LABEL: v4si32_cmp_lt:
; CHECK: vcmpgtsw 2, 3, 2
define <4 x i32> @v4ui32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4ui32_cmp_lt:
+; CHECK-LABEL: v4ui32_cmp_lt:
; CHECK: vcmpgtuw 2, 3, 2
define <4 x i32> @v4si32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_gt:
+; CHECK-LABEL: v4si32_cmp_gt:
; CHECK: vcmpgtsw 2, 2, 3
define <4 x i32> @v4ui32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4ui32_cmp_gt:
+; CHECK-LABEL: v4ui32_cmp_gt:
; CHECK: vcmpgtuw 2, 2, 3
define <4 x i32> @v4si32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4si32_cmp_ge:
+; CHECK-LABEL: v4si32_cmp_ge:
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
}
-; CHECK: v4ui32_cmp_ge:
+; CHECK-LABEL: v4ui32_cmp_ge:
; CHECK: vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3
; CHECK-NEXT: vor 2, [[RCMPGT]], [[RCMPEQ]]
%sext = sext <8 x i1> %cmp to <8 x i32>
ret <8 x i32> %sext
}
-; CHECK: v8si32_cmp:
+; CHECK-LABEL: v8si32_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <16 x i1> %cmp to <16 x i32>
ret <16 x i32> %sext
}
-; CHECK: v16si32_cmp:
+; CHECK-LABEL: v16si32_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%sext = sext <32 x i1> %cmp to <32 x i32>
ret <32 x i32> %sext
}
-; CHECK: v32si32_cmp:
+; CHECK-LABEL: v32si32_cmp:
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%0 = bitcast <2 x i32> %sext to <2 x float>
ret <2 x float> %0
}
-; CHECK: v2f32_cmp:
+; CHECK-LABEL: v2f32_cmp:
; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_eq:
+; CHECK-LABEL: v4f32_cmp_eq:
; CHECK: vcmpeqfp 2, 2, 3
define <4 x float> @v4f32_cmp_ne(<4 x float> %x, <4 x float> %y) nounwind readnone {
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_ne:
+; CHECK-LABEL: v4f32_cmp_ne:
; CHECK: vcmpeqfp [[RET:[0-9]+]], 2, 3
; CHECK-NEXT: vnor 2, [[RET]], [[RET]]
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_le:
+; CHECK-LABEL: v4f32_cmp_le:
; CHECK: vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3
; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2
; CHECK-NEXT: vor 2, [[RCMPLE]], [[RCMPEQ]]
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_lt:
+; CHECK-LABEL: v4f32_cmp_lt:
; CHECK: vcmpgtfp 2, 3, 2
define <4 x float> @v4f32_cmp_ge(<4 x float> %x, <4 x float> %y) nounwind readnone {
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_ge:
+; CHECK-LABEL: v4f32_cmp_ge:
; CHECK: vcmpgefp 2, 2, 3
define <4 x float> @v4f32_cmp_gt(<4 x float> %x, <4 x float> %y) nounwind readnone {
%0 = bitcast <4 x i32> %sext to <4 x float>
ret <4 x float> %0
}
-; CHECK: v4f32_cmp_gt:
+; CHECK-LABEL: v4f32_cmp_gt:
; CHECK: vcmpgtfp 2, 2, 3
%0 = bitcast <8 x i32> %sext to <8 x float>
ret <8 x float> %0
}
-; CHECK: v8f32_cmp:
+; CHECK-LABEL: v8f32_cmp:
; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
store <4 x i32> %1, <4 x i32>* %y, align 16
ret void
}
-;CHECK: v4f32_to_v4i32:
+;CHECK-LABEL: v4f32_to_v4i32:
;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0
store <4 x i32> %1, <4 x i32>* %y, align 16
ret void
}
-;CHECK: v4f32_to_v4u32:
+;CHECK-LABEL: v4f32_to_v4u32:
;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0
store <4 x float> %1, <4 x float>* %y, align 16
ret void
}
-;CHECK: v4i32_to_v4f32:
+;CHECK-LABEL: v4i32_to_v4f32:
;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0
store <4 x float> %1, <4 x float>* %y, align 16
ret void
}
-;CHECK: v4u32_to_v4f32:
+;CHECK-LABEL: v4u32_to_v4f32:
;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0
%c = sext <16 x i4> %b to <16 x i8>
ret <16 x i8> %c
}
-; CHECK: v16si8_sext_in_reg:
+; CHECK-LABEL: v16si8_sext_in_reg:
; CHECK: vslb
; CHECK: vsrab
; CHECK: blr
%c = zext <16 x i4> %b to <16 x i8>
ret <16 x i8> %c
}
-; CHECK: v16si8_zext_in_reg:
+; CHECK-LABEL: v16si8_zext_in_reg:
; CHECK: vspltisb [[VMASK:[0-9]+]], 15
; CHECK-NEXT: vand 2, 2, [[VMASK]]
%c = sext <8 x i8> %b to <8 x i16>
ret <8 x i16> %c
}
-; CHECK: v8si16_sext_in_reg:
+; CHECK-LABEL: v8si16_sext_in_reg:
; CHECK: vslh
; CHECK: vsrah
; CHECK: blr
%c = zext <8 x i8> %b to <8 x i16>
ret <8 x i16> %c
}
-; CHECK: v8si16_zext_in_reg:
+; CHECK-LABEL: v8si16_zext_in_reg:
; CHECK: ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
; CHECK-NEXT: vand 2, 2, [[VMASK]]
%c = sext <4 x i16> %b to <4 x i32>
ret <4 x i32> %c
}
-; CHECK: v4si32_sext_in_reg:
+; CHECK-LABEL: v4si32_sext_in_reg:
; CHECK: vslw
; CHECK: vsraw
; CHECK: blr
%c = zext <4 x i16> %b to <4 x i32>
ret <4 x i32> %c
}
-; CHECK: v4si32_zext_in_reg:
+; CHECK-LABEL: v4si32_zext_in_reg:
; CHECK: vspltisw [[VMASK:[0-9]+]], -16
; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
; CHECK-NEXT: vand 2, 2, [[VMASK]]
%t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK: floor_v2f64:
+; CHECK-LABEL: floor_v2f64:
; CHECK: frim
; CHECK: frim
%t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK: floor_v4f64:
+; CHECK-LABEL: floor_v4f64:
; CHECK: frim
; CHECK: frim
; CHECK: frim
%t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK: ceil_v2f64:
+; CHECK-LABEL: ceil_v2f64:
; CHECK: frip
; CHECK: frip
%t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK: ceil_v4f64:
+; CHECK-LABEL: ceil_v4f64:
; CHECK: frip
; CHECK: frip
; CHECK: frip
%t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK: trunc_v2f64:
+; CHECK-LABEL: trunc_v2f64:
; CHECK: friz
; CHECK: friz
%t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK: trunc_v4f64:
+; CHECK-LABEL: trunc_v4f64:
; CHECK: friz
; CHECK: friz
; CHECK: friz
%t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
ret <2 x double> %t
}
-; CHECK: nearbyint_v2f64:
+; CHECK-LABEL: nearbyint_v2f64:
; CHECK: bl nearbyint
; CHECK: bl nearbyint
%t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
ret <4 x double> %t
}
-; CHECK: nearbyint_v4f64:
+; CHECK-LABEL: nearbyint_v4f64:
; CHECK: bl nearbyint
; CHECK: bl nearbyint
; CHECK: bl nearbyint
%t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK: floor_v4f32:
+; CHECK-LABEL: floor_v4f32:
; CHECK: vrfim
declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
%t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK: floor_v8f32:
+; CHECK-LABEL: floor_v8f32:
; CHECK: vrfim
; CHECK: vrfim
%t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK: ceil_v4f32:
+; CHECK-LABEL: ceil_v4f32:
; CHECK: vrfip
declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
%t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK: ceil_v8f32:
+; CHECK-LABEL: ceil_v8f32:
; CHECK: vrfip
; CHECK: vrfip
%t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK: trunc_v4f32:
+; CHECK-LABEL: trunc_v4f32:
; CHECK: vrfiz
declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
%t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK: trunc_v8f32:
+; CHECK-LABEL: trunc_v8f32:
; CHECK: vrfiz
; CHECK: vrfiz
%t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
ret <4 x float> %t
}
-; CHECK: nearbyint_v4f32:
+; CHECK-LABEL: nearbyint_v4f32:
; CHECK: vrfin
declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
%t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
ret <8 x float> %t
}
-; CHECK: nearbyint_v8f32:
+; CHECK-LABEL: nearbyint_v8f32:
; CHECK: vrfin
; CHECK: vrfin
ret <2 x float> %sqrt
}
; sqrt (<2 x float>) is promoted to sqrt (<4 x float>)
-; CHECK: v2f32_sqrt:
+; CHECK-LABEL: v2f32_sqrt:
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
%sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %x)
ret <4 x float> %sqrt
}
-; CHECK: v4f32_sqrt:
+; CHECK-LABEL: v4f32_sqrt:
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
%sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x)
ret <8 x float> %sqrt
}
-; CHECK: v8f32_sqrt:
+; CHECK-LABEL: v8f32_sqrt:
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
%sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %x)
ret <2 x double> %sqrt
}
-; CHECK: v2f64_sqrt:
+; CHECK-LABEL: v2f64_sqrt:
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
%sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x)
ret <4 x double> %sqrt
}
-; CHECK: v4f64_sqrt:
+; CHECK-LABEL: v4f64_sqrt:
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
define i32 @restore_add(i32 %a, i32 %b) {
entry:
-;CHECK: restore_add:
+;CHECK-LABEL: restore_add:
;CHECK: jmp %i7+8
;CHECK: restore %o0, %i1, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
define i32 @restore_add_imm(i32 %a) {
entry:
-;CHECK: restore_add_imm:
+;CHECK-LABEL: restore_add_imm:
;CHECK: jmp %i7+8
;CHECK: restore %o0, 20, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
define i32 @restore_or(i32 %a) {
entry:
-;CHECK: restore_or:
+;CHECK-LABEL: restore_or:
;CHECK: jmp %i7+8
;CHECK: restore %g0, %o0, %o0
%0 = tail call i32 @bar(i32 %a) nounwind
define i32 @restore_or_imm(i32 %a) {
entry:
-;CHECK: restore_or_imm:
+;CHECK-LABEL: restore_or_imm:
;CHECK: or %o0, 20, %i0
;CHECK: jmp %i7+8
;CHECK: restore %g0, %g0, %g0
; RUN: llc < %s -march=sparcv9 -disable-sparc-delay-filler -disable-sparc-leaf-proc | FileCheck %s
; RUN: llc < %s -march=sparcv9 | FileCheck %s -check-prefix=OPT
-; CHECK: ret2:
+; CHECK-LABEL: ret2:
; CHECK: or %g0, %i1, %i0
-; OPT: ret2:
+; OPT-LABEL: ret2:
; OPT: jmp %o7+8
; OPT: or %g0, %o1, %o0
define i64 @ret2(i64 %a, i64 %b) {
; CHECK: shl_imm
; CHECK: sllx %i0, 7, %i0
-; OPT: shl_imm:
+; OPT-LABEL: shl_imm:
; OPT: jmp %o7+8
; OPT: sllx %o0, 7, %o0
define i64 @shl_imm(i64 %a) {
; CHECK: sra_reg
; CHECK: srax %i0, %i1, %i0
-; OPT: sra_reg:
+; OPT-LABEL: sra_reg:
; OPT: jmp %o7+8
; OPT: srax %o0, %o1, %o0
define i64 @sra_reg(i64 %a, i64 %b) {
ret double %y
}
-; CHECK: store_zero:
+; CHECK-LABEL: store_zero:
; CHECK: stx %g0, [%i0]
; CHECK: stx %g0, [%i1+8]
-; OPT: store_zero:
+; OPT-LABEL: store_zero:
; OPT: stx %g0, [%o0]
; OPT: stx %g0, [%o1+8]
define i64 @store_zero(i64* nocapture %a, i64* nocapture %b) {
; CHECK: xnor %o0, %o1, %o0
}
-; CHECK: store_zero:
+; CHECK-LABEL: store_zero:
; CHECK: st %g0, [%o0]
; CHECK: st %g0, [%o1+4]
define i32 @store_zero(i32* %a, i32* %b) {
ret i8* %x
}
-; abs32: func_block_addr:
+; abs32-LABEL: func_block_addr:
; abs32: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
; abs32: call dummy
; abs32: add [[R]], %lo([[BLK]]), %o0
; abs32: jmp %o0
-; abs44: func_block_addr:
+; abs44-LABEL: func_block_addr:
; abs44: sethi %h44([[BLK:.+]]), [[R:%[gilo][0-7]]]
; abs44: add [[R]], %m44([[BLK]]), [[R1:%[gilo][0-7]]]
; abs44: sllx [[R1]], 12, [[R2:%[gilo][0-7]]]
; abs44: add [[R2]], %l44([[BLK]]), %o0
; abs44: jmp %o0
-; abs64: func_block_addr:
+; abs64-LABEL: func_block_addr:
; abs64: sethi %hi([[BLK:.+]]), [[R:%[gilo][0-7]]]
; abs64: add [[R]], %lo([[BLK]]), [[R1:%[gilo][0-7]]]
; abs64: sethi %hh([[BLK]]), [[R2:%[gilo][0-7]]]
; V8: call get_double
; V8: fnegs %f0, %f0
-; V8-UNOPT: test_neg:
+; V8-UNOPT-LABEL: test_neg:
; V8-UNOPT: fnegs
; V8-UNOPT: ! implicit-def
; V8-UNOPT: fmovs {{.+}}, %f0
; V8-LABEL: test_abs:
; V8: fabss %f0, %f0
-; V8-UNOPT: test_abs:
+; V8-UNOPT-LABEL: test_abs:
; V8-UNOPT: fabss
; V8-UNOPT: ! implicit-def
; V8-UNOPT: fmovs {{.+}}, %f0
; RUN: llc -march=sparc -disable-sparc-leaf-proc=0 < %s | FileCheck %s
-; CHECK: func_nobody:
+; CHECK-LABEL: func_nobody:
; CHECK: jmp %o7+8
; CHECK-NEXT: nop
define void @func_nobody() {
}
-; CHECK: return_int_const:
+; CHECK-LABEL: return_int_const:
; CHECK: jmp %o7+8
; CHECK-NEXT: or %g0, 1729, %o0
define i32 @return_int_const() {
ret i32 1729
}
-; CHECK: return_double_const:
+; CHECK-LABEL: return_double_const:
; CHECK: sethi
; CHECK: jmp %o7+8
; CHECK-NEXT: ldd {{.*}}, %f0
ret double 0.000000e+00
}
-; CHECK: leaf_proc_with_args:
+; CHECK-LABEL: leaf_proc_with_args:
; CHECK: add {{%o[0-1]}}, {{%o[0-1]}}, [[R:%[go][0-7]]]
; CHECK: jmp %o7+8
; CHECK-NEXT: add [[R]], %o2, %o0
ret i32 %1
}
-; CHECK: leaf_proc_with_args_in_stack:
+; CHECK-LABEL: leaf_proc_with_args_in_stack:
; CHECK-DAG: ld [%sp+92], {{%[go][0-7]}}
; CHECK-DAG: ld [%sp+96], {{%[go][0-7]}}
; CHECK: jmp %o7+8
ret i32 %6
}
-; CHECK: leaf_proc_with_local_array:
+; CHECK-LABEL: leaf_proc_with_local_array:
; CHECK: add %sp, -104, %sp
; CHECK: or %g0, 1, [[R1:%[go][0-7]]]
; CHECK: st [[R1]], [%sp+96]
; A simple index address.
define void @f1(i64 %addr, i64 %index) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lb %r0, 0(%r3,%r2)
; CHECK: br %r14
%add = add i64 %addr, %index
; An address with an index and a displacement (order 1).
define void @f2(i64 %addr, i64 %index) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lb %r0, 100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, %index
; An address with an index and a displacement (order 2).
define void @f3(i64 %addr, i64 %index) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lb %r0, 100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, 100
; An address with an index and a subtracted displacement (order 1).
define void @f4(i64 %addr, i64 %index) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lb %r0, -100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, %index
; An address with an index and a subtracted displacement (order 2).
define void @f5(i64 %addr, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lb %r0, -100(%r3,%r2)
; CHECK: br %r14
%add1 = sub i64 %addr, 100
; An address with an index and a displacement added using OR.
define void @f6(i64 %addr, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
; CHECK: lb %r0, 6(%r3,[[BASE]])
; CHECK: br %r14
; Like f6, but without the masking. This OR doesn't count as a displacement.
define void @f7(i64 %addr, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oill %r2, 6
; CHECK: lb %r0, 0(%r3,%r2)
; CHECK: br %r14
; Like f6, but with the OR applied after the index. We don't know anything
; about the alignment of %add here.
define void @f8(i64 %addr, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
; CHECK: agr [[BASE]], %r3
; CHECK: oill [[BASE]], 6
; A simple index address.
define void @f1(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lb %r0, 0(%r3,%r2)
; CHECK: br %r14
%add = add i64 %addr, %index
; An address with an index and a displacement (order 1).
define void @f2(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lb %r0, 100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, %index
; An address with an index and a displacement (order 2).
define void @f3(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lb %r0, 100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, 100
; An address with an index and a subtracted displacement (order 1).
define void @f4(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lb %r0, -100(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %addr, %index
; An address with an index and a subtracted displacement (order 2).
define void @f5(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lb %r0, -100(%r3,%r2)
; CHECK: br %r14
%add1 = sub i64 %addr, 100
; An address with an index and a displacement added using OR.
define void @f6(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
; CHECK: lb %r0, 6(%r3,[[BASE]])
; CHECK: br %r14
; Like f6, but without the masking. This OR doesn't count as a displacement.
define void @f7(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oill %r2, 6
; CHECK: lb %r0, 0(%r3,%r2)
; CHECK: br %r14
; Like f6, but with the OR applied after the index. We don't know anything
; about the alignment of %add here.
define void @f8(i64 %addr, i64 %index, i8 **%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
; CHECK: agr [[BASE]], %r3
; CHECK: oill [[BASE]], 6
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lb %r0, 0
; CHECK: br %r14
%ptr = inttoptr i64 0 to i8 *
}
define void @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lb %r0, -524288
; CHECK: br %r14
%ptr = inttoptr i64 -524288 to i8 *
}
define void @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: lb %r0, -524289
; CHECK: br %r14
%ptr = inttoptr i64 -524289 to i8 *
}
define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lb %r0, 524287
; CHECK: br %r14
%ptr = inttoptr i64 524287 to i8 *
}
define void @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: lb %r0, 524288
; CHECK: br %r14
%ptr = inttoptr i64 524288 to i8 *
; risbg %r1, %r1, 0, 188, 0
; lgr %r15, %r1
;
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: la [[REG1:%r[0-5]]], 7(%r2)
; CHECK-DAG: risbg [[REG2:%r[0-5]]], [[REG1]], 0, 188, 0
; CHECK-DAG: lgr [[REG3:%r[0-5]]], %r15
; CHECK: sgr [[REG3]], [[REG2]]
; CHECK: lgr %r15, [[REG3]]
;
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
; CHECK-A: lgr %r15, %r1
; CHECK-A: la %r2, 176(%r1)
;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
; CHECK-B: lgr %r15, %r1
; CHECK-B: la %r3, 177(%r1)
;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
; CHECK-C: lgr %r15, %r1
; CHECK-C: la %r4, 4095({{%r3,%r1|%r1,%r3}})
;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
; CHECK-D: lgr %r15, %r1
; CHECK-D: lay %r5, 4096({{%r3,%r1|%r1,%r3}})
;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
; CHECK-E: lgr %r15, %r1
; CHECK-E: lay %r6, 4271({{%r3,%r1|%r1,%r3}})
;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
; CHECK-FP: lgr %r11, %r15
; CHECK-FP: lmg %r6, %r15, 224(%r11)
%a = alloca i8, i64 %length
declare i64 @bar(i8 *%a)
define i64 @f1(i64 %length, i64 %index) {
-; CHECK-A: f1:
+; CHECK-A-LABEL: f1:
; CHECK-A: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-A: la %r2, 160([[ADDR]])
; CHECK-A: mvi 0(%r2), 0
;
-; CHECK-B: f1:
+; CHECK-B-LABEL: f1:
; CHECK-B: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-B: la %r2, 160([[ADDR]])
; CHECK-B: mvi 4095(%r2), 1
;
-; CHECK-C: f1:
+; CHECK-C-LABEL: f1:
; CHECK-C: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-C: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
; CHECK-C: mvi 0([[TMP]]), 2
;
-; CHECK-D: f1:
+; CHECK-D-LABEL: f1:
; CHECK-D: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-D: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
; CHECK-D: mvi 4095([[TMP]]), 3
;
-; CHECK-E: f1:
+; CHECK-E-LABEL: f1:
; CHECK-E: lgr %r15, [[ADDR:%r[1-5]]]
; CHECK-E: la [[TMP:%r[1-5]]], 160(%r3,[[ADDR]])
; CHECK-E: mviy 4096([[TMP]]), 4
; Check NR.
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: nr %r2, %r3
; CHECK: br %r14
%and = and i32 %a, %b
; Check the low end of the N range.
define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: n %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned N range.
define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: n %r2, 4092(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
; Check the next word up, which should use NY instead of N.
define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ny %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
; Check the high end of the aligned NY range.
define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ny %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: n %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned NY range.
define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ny %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the NY range.
define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ny %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: n %r2, 0(%r3)
; CHECK: br %r14
; Check that N allows an index.
define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: n %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that NY allows an index.
define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: ny %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that ANDs of spilled values can use N rather than NR.
define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK: n %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; ANDs with 1 should use RISBG
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: risbg %r2, %r2, 63, 191, 0
; CHECK: br %r14
%and = and i32 %a, 1
; ...same for 2.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: risbg %r2, %r2, 62, 190, 0
; CHECK: br %r14
%and = and i32 %a, 2
; ...and 3.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: risbg %r2, %r2, 62, 191, 0
; CHECK: br %r14
%and = and i32 %a, 3
; ...and 4.
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r2, 61, 189, 0
; CHECK: br %r14
%and = and i32 %a, 4
; Check the lowest useful NILF value.
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilf %r2, 5
; CHECK: br %r14
%and = and i32 %a, 5
; Check the highest 16-bit constant that must be handled by NILF.
define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilf %r2, 65533
; CHECK: br %r14
%and = and i32 %a, 65533
; ANDs of 0xffff are zero extensions from i16.
define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llhr %r2, %r2
; CHECK: br %r14
%and = and i32 %a, 65535
; Check the next value up, which can use RISBG.
define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: risbg %r2, %r2, 47, 175, 0
; CHECK: br %r14
%and = and i32 %a, 65536
; Check the next value up, which must again use NILF.
define i32 @f9(i32 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: nilf %r2, 65537
; CHECK: br %r14
%and = and i32 %a, 65537
; This value is in range of NILH, but we use RISBG instead.
define i32 @f10(i32 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: risbg %r2, %r2, 47, 191, 0
; CHECK: br %r14
%and = and i32 %a, 131071
; Check the lowest useful NILH value.
define i32 @f11(i32 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: nilh %r2, 2
; CHECK: br %r14
%and = and i32 %a, 196607
; Check the highest useful NILH value.
define i32 @f12(i32 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: nilh %r2, 65530
; CHECK: br %r14
%and = and i32 %a, -327681
; Check the equivalent of NILH of 65531, which can use RISBG.
define i32 @f13(i32 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: risbg %r2, %r2, 46, 172, 0
; CHECK: br %r14
%and = and i32 %a, -262145
; ...same for 65532.
define i32 @f14(i32 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: risbg %r2, %r2, 48, 173, 0
; CHECK: br %r14
%and = and i32 %a, -196609
; ...and 65533.
define i32 @f15(i32 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: risbg %r2, %r2, 47, 173, 0
; CHECK: br %r14
%and = and i32 %a, -131073
; Check the highest useful NILF value.
define i32 @f16(i32 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: nilf %r2, 4294901758
; CHECK: br %r14
%and = and i32 %a, -65538
; Check the next value up, which is the equivalent of an NILH of 65534.
; We use RISBG instead.
define i32 @f17(i32 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: risbg %r2, %r2, 48, 174, 0
; CHECK: br %r14
%and = and i32 %a, -65537
; Check the next value up, which can also use RISBG.
define i32 @f18(i32 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: risbg %r2, %r2, 32, 175, 0
; CHECK: br %r14
%and = and i32 %a, -65536
; ...and again.
define i32 @f19(i32 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: risbg %r2, %r2, 63, 175, 0
; CHECK: br %r14
%and = and i32 %a, -65535
; Check the next value up again, which is the lowest useful NILL value.
define i32 @f20(i32 %a) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: nill %r2, 2
; CHECK: br %r14
%and = and i32 %a, -65534
; Check the highest useful NILL value.
define i32 @f21(i32 %a) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK: nill %r2, 65530
; CHECK: br %r14
%and = and i32 %a, -6
; Check the next value up, which can use RISBG.
define i32 @f22(i32 %a) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK: risbg %r2, %r2, 62, 188, 0
; CHECK: br %r14
%and = and i32 %a, -5
; ...and again.
define i32 @f23(i32 %a) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
; CHECK: risbg %r2, %r2, 32, 189, 0
; CHECK: br %r14
%and = and i32 %a, -4
; ...and again.
define i32 @f24(i32 %a) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
; CHECK: risbg %r2, %r2, 63, 189, 0
; CHECK: br %r14
%and = and i32 %a, -3
; Check the last useful mask.
define i32 @f25(i32 %a) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
; CHECK: risbg %r2, %r2, 32, 190, 0
; CHECK: br %r14
%and = and i32 %a, -2
; Check NGR.
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ngr %r2, %r3
; CHECK: br %r14
%and = and i64 %a, %b
; Check NG with no displacement.
define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ng %r2, 0(%r3)
; CHECK: br %r14
%b = load i64 *%src
; Check the high end of the aligned NG range.
define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ng %r2, 524280(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: ng %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned NG range.
define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ng %r2, -8(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the NG range.
define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ng %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: ng %r2, 0(%r3)
; CHECK: br %r14
; Check that NG allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ng %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that ANDs of spilled values can use NG rather than NGR.
define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: ng %r2, 160(%r15)
; CHECK: br %r14
; Use RISBG for a single bit.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: risbg %r2, %r2, 63, 191, 0
; CHECK: br %r14
%and = and i64 %a, 1
; Likewise 0xfffe.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: risbg %r2, %r2, 48, 190, 0
; CHECK: br %r14
%and = and i64 %a, 65534
; ...but 0xffff is a 16-bit zero extension.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llghr %r2, %r2
; CHECK: br %r14
%and = and i64 %a, 65535
; Check the next value up, which can again use RISBG.
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r2, 47, 175, 0
; CHECK: br %r14
%and = and i64 %a, 65536
; Check 0xfffffffe, which can also use RISBG.
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: risbg %r2, %r2, 32, 190, 0
; CHECK: br %r14
%and = and i64 %a, 4294967294
; Check the next value up, which is a 32-bit zero extension.
define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: llgfr %r2, %r2
; CHECK: br %r14
%and = and i64 %a, 4294967295
; Check the lowest useful NIHF value (0x00000002_ffffffff).
define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nihf %r2, 2
; CHECK: br %r14
%and = and i64 %a, 12884901887
; Check the lowest useful NIHH value (0x0002ffff_ffffffff).
define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nihh %r2, 2
; CHECK: br %r14
%and = and i64 %a, 844424930131967
; Check the highest useful NIHH value (0xfffaffff_ffffffff).
define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: nihh %r2, 65530
; CHECK: br %r14
%and = and i64 %a, -1407374883553281
; Check the highest useful NIHF value (0xfffefffe_ffffffff).
define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: nihf %r2, 4294901758
; CHECK: br %r14
%and = and i64 %a, -281479271677953
; Check the lowest useful NIHL value (0xffff0002_ffffffff).
define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: nihl %r2, 2
; CHECK: br %r14
%and = and i64 %a, -281462091808769
; Check the highest useful NIHL value (0xfffffffa_ffffffff).
define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: nihl %r2, 65530
; CHECK: br %r14
%and = and i64 %a, -21474836481
; Check the lowest useful NILF range (0xffffffff_00000002).
define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: nilf %r2, 2
; CHECK: br %r14
%and = and i64 %a, -4294967294
; Check the low end of the NILH range (0xffffffff_0002ffff).
define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: nilh %r2, 2
; CHECK: br %r14
%and = and i64 %a, -4294770689
; Check the next value up, which must use NILF.
define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: nilf %r2, 196608
; CHECK: br %r14
%and = and i64 %a, -4294770688
; Check the highest useful NILH value (0xffffffff_fffaffff).
define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: nilh %r2, 65530
; CHECK: br %r14
%and = and i64 %a, -327681
; Check the maximum useful NILF value (0xffffffff_fffefffe).
define i64 @f17(i64 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: nilf %r2, 4294901758
; CHECK: br %r14
%and = and i64 %a, -65538
; Check the lowest useful NILL value (0xffffffff_ffff0002).
define i64 @f18(i64 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: nill %r2, 2
; CHECK: br %r14
%and = and i64 %a, -65534
; Check the highest useful NILL value.
define i64 @f19(i64 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: nill %r2, 65530
; CHECK: br %r14
%and = and i64 %a, -6
; Check the lowest useful constant, expressed as a signed integer.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ni 0(%r2), 1
; CHECK: br %r14
%val = load i8 *%ptr
; Check the highest useful constant, expressed as a signed integer.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Check the lowest useful constant, expressed as an unsigned integer.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ni 0(%r2), 1
; CHECK: br %r14
%val = load i8 *%ptr
; Check the highest useful constant, expressed as a unsigned integer.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Check the high end of the NI range.
define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ni 4095(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4095
; Check the next byte up, which should use NIY instead of NI.
define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: niy 4096(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4096
; Check the high end of the NIY range.
define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: niy 524287(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, 524288
; CHECK: ni 0(%r2), 127
; CHECK: br %r14
; Check the high end of the negative NIY range.
define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: niy -1(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the NIY range.
define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: niy -524288(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r2, -524289
; CHECK: ni 0(%r2), 127
; CHECK: br %r14
; Check that NI does not allow an index
define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: agr %r2, %r3
; CHECK: ni 4095(%r2), 127
; CHECK: br %r14
; Check that NIY does not allow an index
define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: agr %r2, %r3
; CHECK: niy 4096(%r2), 127
; CHECK: br %r14
; Zero extension to 32 bits, negative constant.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 64 bits, negative constant.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 32 bits, positive constant.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 64 bits, positive constant.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 32 bits, negative constant.
define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 64 bits, negative constant.
define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 32 bits, positive constant.
define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 64 bits, positive constant.
define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ni 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder
; them in response to future code changes.
define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
; CHECK-INT-DAG: lhi %r2, 1
; CHECK-INT-DAG: lhi %r3, 2
; CHECK-INT-DAG: lhi %r4, 3
; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
; CHECK-INT: brasl %r14, bar@PLT
;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
; CHECK-FLOAT: lzer %f0
; CHECK-FLOAT: lcebr %f4, %f0
; CHECK-FLOAT: brasl %r14, bar@PLT
;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
; CHECK-DOUBLE: lzdr %f2
; CHECK-DOUBLE: lcdbr %f6, %f2
; CHECK-DOUBLE: brasl %r14, bar@PLT
;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
; CHECK-FP128-1: aghi %r15, -256
; CHECK-FP128-1: lzxr %f0
; CHECK-FP128-1-DAG: std %f0, 224(%r15)
; CHECK-FP128-1-DAG: std %f2, 232(%r15)
; CHECK-FP128-1: brasl %r14, bar@PLT
;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
; CHECK-FP128-2: aghi %r15, -256
; CHECK-FP128-2: lzxr %f0
; CHECK-FP128-2-DAG: std %f0, 240(%r15)
; CHECK-FP128-2-DAG: std %f2, 248(%r15)
; CHECK-FP128-2: brasl %r14, bar@PLT
;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
; CHECK-STACK: aghi %r15, -256
; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
; CHECK-STACK: stg [[REGISTER]], 216(%r15)
; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder
; them in response to future code changes.
define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
; CHECK-INT-DAG: lghi %r2, -1
; CHECK-INT-DAG: lghi %r3, -2
; CHECK-INT-DAG: lghi %r4, -3
; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
; CHECK-INT: brasl %r14, bar@PLT
;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
; CHECK-FLOAT: lzer %f0
; CHECK-FLOAT: lcebr %f4, %f0
; CHECK-FLOAT: brasl %r14, bar@PLT
;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
; CHECK-DOUBLE: lzdr %f2
; CHECK-DOUBLE: lcdbr %f6, %f2
; CHECK-DOUBLE: brasl %r14, bar@PLT
;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
; CHECK-FP128-1: aghi %r15, -256
; CHECK-FP128-1: lzxr %f0
; CHECK-FP128-1-DAG: std %f0, 224(%r15)
; CHECK-FP128-1-DAG: std %f2, 232(%r15)
; CHECK-FP128-1: brasl %r14, bar@PLT
;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
; CHECK-FP128-2: aghi %r15, -256
; CHECK-FP128-2: lzxr %f0
; CHECK-FP128-2-DAG: std %f0, 240(%r15)
; CHECK-FP128-2-DAG: std %f2, 248(%r15)
; CHECK-FP128-2: brasl %r14, bar@PLT
;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
; CHECK-STACK: aghi %r15, -256
; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
; CHECK-STACK: stg [[REGISTER]], 216(%r15)
; The order of the CHECK-STACK stores doesn't matter. It would be OK to reorder
; them in response to future code changes.
define void @foo() {
-; CHECK-INT: foo:
+; CHECK-INT-LABEL: foo:
; CHECK-INT-DAG: lghi %r2, 255
; CHECK-INT-DAG: llill %r3, 65534
; CHECK-INT-DAG: llilf %r4, 4294967293
; CHECK-INT-DAG: la %r6, {{224|240}}(%r15)
; CHECK-INT: brasl %r14, bar@PLT
;
-; CHECK-FLOAT: foo:
+; CHECK-FLOAT-LABEL: foo:
; CHECK-FLOAT: lzer %f0
; CHECK-FLOAT: lcebr %f4, %f0
; CHECK-FLOAT: brasl %r14, bar@PLT
;
-; CHECK-DOUBLE: foo:
+; CHECK-DOUBLE-LABEL: foo:
; CHECK-DOUBLE: lzdr %f2
; CHECK-DOUBLE: lcdbr %f6, %f2
; CHECK-DOUBLE: brasl %r14, bar@PLT
;
-; CHECK-FP128-1: foo:
+; CHECK-FP128-1-LABEL: foo:
; CHECK-FP128-1: aghi %r15, -256
; CHECK-FP128-1: lzxr %f0
; CHECK-FP128-1-DAG: std %f0, 224(%r15)
; CHECK-FP128-1-DAG: std %f2, 232(%r15)
; CHECK-FP128-1: brasl %r14, bar@PLT
;
-; CHECK-FP128-2: foo:
+; CHECK-FP128-2-LABEL: foo:
; CHECK-FP128-2: aghi %r15, -256
; CHECK-FP128-2: lzxr %f0
; CHECK-FP128-2-DAG: std %f0, 240(%r15)
; CHECK-FP128-2-DAG: std %f2, 248(%r15)
; CHECK-FP128-2: brasl %r14, bar@PLT
;
-; CHECK-STACK: foo:
+; CHECK-STACK-LABEL: foo:
; CHECK-STACK: aghi %r15, -256
; CHECK-STACK: la [[REGISTER:%r[0-5]+]], {{224|240}}(%r15)
; CHECK-STACK: stg [[REGISTER]], 216(%r15)
; Do some arithmetic so that we can see the register being used.
define i8 @f1(i8 %r2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ahi %r2, 1
; CHECK: br %r14
%y = add i8 %r2, 1
}
define i16 @f2(i8 %r2, i16 %r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: {{lr|lgr}} %r2, %r3
; CHECK: br %r14
ret i16 %r3
}
define i32 @f3(i8 %r2, i16 %r3, i32 %r4) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: {{lr|lgr}} %r2, %r4
; CHECK: br %r14
ret i32 %r4
}
define i64 @f4(i8 %r2, i16 %r3, i32 %r4, i64 %r5) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: {{lr|lgr}} %r2, %r5
; CHECK: br %r14
ret i64 %r5
; Do some arithmetic so that we can see the register being used.
define float @f5(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aebr %f0, %f0
; CHECK: br %r14
%y = fadd float %f0, %f0
}
define double @f6(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ldr %f0, %f2
; CHECK: br %r14
ret double %f2
; be copied.
define void @f7(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ld %f0, 0(%r6)
; CHECK: ld %f2, 8(%r6)
; CHECK: axbr %f0, %f0
define i64 @f8(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lg %r2, 160(%r15)
; CHECK: br %r14
ret i64 %s1
define float @f9(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ler %f0, %f4
; CHECK: br %r14
ret float %f4
define double @f10(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4, double %f6) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ldr %f0, %f6
; CHECK: br %r14
ret double %f6
define i64 @f11(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: lg %r2, 168(%r15)
; CHECK: br %r14
ret i64 %s2
define float @f12(i8 %r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
float %s3) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: le %f0, 180(%r15)
; CHECK: br %r14
ret float %s3
define void @f13(fp128 *%r2, i16 %r3, i32 %r4, i64 %r5, float %f0, double %f2,
fp128 %r6, i64 %s1, float %f4, double %f6, i64 %s2,
float %s3, fp128 %s4) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: lg [[REGISTER:%r[1-5]+]], 184(%r15)
; CHECK: ld %f0, 0([[REGISTER]])
; CHECK: ld %f2, 8([[REGISTER]])
; Zero extension of something that is already zero-extended.
define void @f1(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: stg %r2, 0(%r3)
; CHECK: br %r14
; Sign extension of something that is already sign-extended.
define void @f2(i32 signext %r2, i64 *%r3) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: stg %r2, 0(%r3)
; CHECK: br %r14
; Sign extension of something that is already zero-extended.
define void @f3(i32 zeroext %r2, i64 *%r3) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lgfr [[REGISTER:%r[0-5]+]], %r2
; CHECK: stg [[REGISTER]], 0(%r3)
; CHECK: br %r14
; Zero extension of something that is already sign-extended.
define void @f4(i32 signext %r2, i64 *%r3) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llgfr [[REGISTER:%r[0-5]+]], %r2
; CHECK: stg [[REGISTER]], 0(%r3)
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i8 @f1(i8 %a, i8 %b, i8 %c, i8 %d, i8 %e, i8 %f, i8 %g) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ar %r2, %r3
; CHECK: ar %r2, %r4
; CHECK: ar %r2, %r5
}
define i16 @f2(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ar %r2, %r3
; CHECK: ar %r2, %r4
; CHECK: ar %r2, %r5
}
define i32 @f3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ar %r2, %r3
; CHECK: ar %r2, %r4
; CHECK: ar %r2, %r5
}
define i64 @f4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agr %r2, %r3
; CHECK: agr %r2, %r4
; CHECK: agr %r2, %r5
; Check the lowest range.
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
; Check the next lowest byte.
define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r2, -1
; CHECK: blah 0(%r2)
; CHECK: br %r14
; Check the highest range.
define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah 4095(%r2)
; CHECK: br %r14
%add = add i64 %base, 4095
; Check the next highest byte.
define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: blah 0(%r2)
; CHECK: br %r14
; Check that indices aren't allowed
define void @f5(i64 %base, i64 %index) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agr %r2, %r3
; CHECK: blah 0(%r2)
; CHECK: br %r14
; Check the lowest range.
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
; Check the next lowest byte.
define void @f2(i64 %base) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r2, -1
; CHECK: blah 0(%r2)
; CHECK: br %r14
; Check the highest range.
define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah 4095(%r2)
; CHECK: br %r14
%add = add i64 %base, 4095
; Check the next highest byte.
define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: blah 0(%r2)
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i64 %base) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: blah 0(%r2)
; CHECK: br %r14
%addr = inttoptr i64 %base to i64 *
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r1, 1
; CHECK: blah %r2 %r1
; CHECK: br %r14
}
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r1, 2
; CHECK: blah %r2 %r1
; CHECK: br %r14
}
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lhi %r1, 3
; CHECK: blah %r2 %r1
; CHECK: br %r14
}
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lghi %r1, 4
; CHECK: blah %r2 %r1
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r0, 1
; CHECK: blah %r2 %r0
; CHECK: br %r14
}
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r0, 2
; CHECK: blah %r2 %r0
; CHECK: br %r14
}
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lhi %r0, 3
; CHECK: blah %r2 %r0
; CHECK: br %r14
}
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lghi %r0, 4
; CHECK: blah %r2 %r0
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r0, 1
; CHECK: blah %r2 %r0
; CHECK: br %r14
}
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r0, 2
; CHECK: blah %r2 %r0
; CHECK: br %r14
}
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lhi %r0, 3
; CHECK: blah %r2 %r0
; CHECK: br %r14
}
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lghi %r0, 4
; CHECK: blah %r2 %r0
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r0, 100
; CHECK: blah %r0
; CHECK: st %r0, 0(%r2)
}
define void @f2(i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r0, 101
; CHECK: blah %r0
; CHECK: st %r0, 0(%r2)
}
define void @f3(i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lhi %r0, 102
; CHECK: blah %r0
; CHECK: st %r0, 0(%r2)
; FIXME: this uses "lhi %r0, 103", but should use "lghi %r0, 103".
define void @f4(i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: blah %r0
; CHECK: st %r0, 0(%r2)
; CHECK: br %r14
}
define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lghi %r2, 104
; CHECK: blah %r2
; CHECK: br %r14
}
define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lghi %r2, 105
; CHECK: blah %r2
; CHECK: br %r14
}
define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lghi %r2, 106
; CHECK: blah %r2
; CHECK: br %r14
}
define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lghi %r2, 107
; CHECK: blah %r2
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lzer %f1
; CHECK: blah %f0 %f1
; CHECK: br %r14
}
define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lzdr %f1
; CHECK: blah %f0 %f1
; CHECK: br %r14
}
define double @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lzxr %f1
; CHECK: blah %f0 %f1
; CHECK: br %r14
; Test 1 below the first valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 0
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rI" (i32 0)
; Test the last valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah %r2 255
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rI" (i32 255)
; Test 1 above the last valid value.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lhi [[REG:%r[0-5]]], 256
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test 1 below the first valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 0
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 0)
; Test the last valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah %r2 4095
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rJ" (i32 4095)
; Test 1 above the last valid value.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lhi [[REG:%r[0-5]]], 4096
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test 1 below the first valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 4294934527
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 -32768
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rK" (i32 -32768)
; Test the last valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah %r2 32767
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rK" (i32 32767)
; Test 1 above the last valid value.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llill [[REG:%r[0-5]]], 32768
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test 1 below the first valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 4294443007
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 -524288
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rL" (i32 -524288)
; Test the last valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blah %r2 524287
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rL" (i32 524287)
; Test 1 above the last valid value.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llilh [[REG:%r[0-5]]], 8
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test 1 below the valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 2147483646
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 2147483647
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
; Test 1 above the valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llilh [[REG:%r[0-5]]], 32768
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test 1 below the valid value.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: iilf [[REG:%r[0-5]]], 2147483646
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test the first valid value.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: blah %r2 2147483647
; CHECK: br %r14
%val = call i32 asm "blah $0 $1", "=&r,rM" (i32 2147483647)
; Test 1 above the valid value.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llilh [[REG:%r[0-5]]], 32768
; CHECK: blah %r2 [[REG]]
; CHECK: br %r14
; Test i32 GPRs.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r4, 1
; CHECK: blah %r4
; CHECK: lr %r2, %r4
; Test i64 GPRs.
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lghi %r4, 1
; CHECK: blah %r4
; CHECK: lgr %r2, %r4
; Test i32 FPRs.
define float @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lzer %f4
; CHECK: blah %f4
; CHECK: ler %f0, %f4
; Test i64 FPRs.
define double @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lzdr %f4
; CHECK: blah %f4
; CHECK: ldr %f0, %f4
; Test i128 FPRs.
define void @f5(fp128 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lzxr %f4
; CHECK: blah %f4
; CHECK-DAG: std %f4, 0(%r2)
; Test clobbers of GPRs and CC.
define i32 @f6(i32 %in) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lr [[REG:%r[01345]]], %r2
; CHECK: blah
; CHECK: lr %r2, [[REG]]
; Test clobbers of FPRs and CC.
define float @f7(float %in) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ler [[REG:%f[1-7]]], %f0
; CHECK: blah
; CHECK: ler %f0, [[REG]]
; This is just a placeholder to make sure that loads are handled.
; The CS-based sequence is probably far too conservative.
define i8 @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs
; CHECK: br %r14
%val = load atomic i8 *%src seq_cst, align 1
; This is just a placeholder to make sure that loads are handled.
; The CS-based sequence is probably far too conservative.
define i16 @f1(i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs
; CHECK: br %r14
%val = load atomic i16 *%src seq_cst, align 2
; This is just a placeholder to make sure that loads are handled.
; Using CS is probably too conservative.
define i32 @f1(i32 %dummy, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r2, 0
; CHECK: cs %r2, %r2, 0(%r3)
; CHECK: br %r14
; This is just a placeholder to make sure that loads are handled.
; Using CSG is probably too conservative.
define i64 @f1(i64 %dummy, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lghi %r2, 0
; CHECK: csg %r2, %r2, 0(%r3)
; CHECK: br %r14
; This is just a placeholder to make sure that stores are handled.
; The CS-based sequence is probably far too conservative.
define void @f1(i8 %val, i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs
; CHECK: br %r14
store atomic i8 %val, i8 *%src seq_cst, align 1
; This is just a placeholder to make sure that stores are handled.
; The CS-based sequence is probably far too conservative.
define void @f1(i16 %val, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs
; CHECK: br %r14
store atomic i16 %val, i16 *%src seq_cst, align 2
; This is just a placeholder to make sure that stores are handled.
; Using CS is probably too conservative.
define void @f1(i32 %val, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r0, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: cs %r0, %r2, 0(%r3)
; This is just a placeholder to make sure that stores are handled.
; Using CS is probably too conservative.
define void @f1(i64 %val, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r0, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: csg %r0, %r2, 0(%r3)
; before being used. This shift is independent of the other loop prologue
; instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
; Check the minimum signed value. We add 0x80000000 to the rotated word.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 -128 seq_cst
ret i8 %res
; Check addition of -1. We add 0xff000000 to the rotated word.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi [[ROT]], -16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 -1 seq_cst
ret i8 %res
; Check addition of 1. We add 0x01000000 to the rotated word.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi [[ROT]], 16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 1 seq_cst
ret i8 %res
; Check the maximum signed value. We add 0x7f000000 to the rotated word.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi [[ROT]], 2130706432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 127 seq_cst
ret i8 %res
; Check addition of a large unsigned value. We add 0xfe000000 to the
; rotated word, expressed as a negative AFI operand.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi [[ROT]], -33554432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i8 *%src, i8 254 seq_cst
ret i8 %res
; before being used. This shift is independent of the other loop prologue
; instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: ar {{%r[0-9]+}}, %r3
; Check the minimum signed value. We add 0x80000000 to the rotated word.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 -32768 seq_cst
ret i16 %res
; Check addition of -1. We add 0xffff0000 to the rotated word.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi [[ROT]], -65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 -1 seq_cst
ret i16 %res
; Check addition of 1. We add 0x00010000 to the rotated word.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi [[ROT]], 65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 1 seq_cst
ret i16 %res
; Check the maximum signed value. We add 0x7fff0000 to the rotated word.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi [[ROT]], 2147418112
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 32767 seq_cst
ret i16 %res
; Check addition of a large unsigned value. We add 0xfffe0000 to the
; rotated word, expressed as a negative AFI operand.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi [[ROT]], -131072
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw add i16 *%src, i16 65534 seq_cst
ret i16 %res
; Check addition of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2
; Check addition of 1, which can use AHI.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2
; Check the high end of the AHI range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ahi %r0, 32767
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 32767 seq_cst
; Check the next value up, which must use AFI.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi %r0, 32768
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 32768 seq_cst
; Check the high end of the AFI range.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi %r0, 2147483647
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 2147483647 seq_cst
; Check the next value up, which gets treated as a negative operand.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi %r0, -2147483648
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 2147483648 seq_cst
; Check addition of -1, which can use AHI.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ahi %r0, -1
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 -1 seq_cst
; Check the low end of the AHI range.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ahi %r0, -32768
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 -32768 seq_cst
; Check the next value down, which must use AFI instead.
define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: afi %r0, -32769
; CHECK: br %r14
%res = atomicrmw add i32 *%src, i32 -32769 seq_cst
; Check addition of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
; Check addition of 1, which can use AGHI.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
; Check the high end of the AGHI range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r0, 32767
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 32767 seq_cst
; Check the next value up, which must use AGFI.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r0, 32768
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 32768 seq_cst
; Check the high end of the AGFI range.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r0, 2147483647
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 2147483647 seq_cst
; Check the next value up, which must use a register addition.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agr
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 2147483648 seq_cst
; Check addition of -1, which can use AGHI.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: aghi %r0, -1
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -1 seq_cst
; Check the low end of the AGHI range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r0, -32768
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -32768 seq_cst
; Check the next value down, which must use AGFI instead.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r0, -32769
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -32769 seq_cst
; Check the low end of the AGFI range.
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r0, -2147483648
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -2147483648 seq_cst
; Check the next value down, which must use a register addition.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agr
; CHECK: br %r14
%res = atomicrmw add i64 *%src, i64 -2147483649 seq_cst
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: oilf %r3, 16777215
; CHECK-SHIFT2: rll
; Check the minimum signed value. We AND the rotated word with 0x80ffffff.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 -128 seq_cst
ret i8 %res
; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfeffffff.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh [[ROT]], 65279
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 -2 seq_cst
ret i8 %res
; Check ANDs of 1. We AND the rotated word with 0x01ffffff.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilh [[ROT]], 511
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 1 seq_cst
ret i8 %res
; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilh [[ROT]], 32767
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 127 seq_cst
ret i8 %res
; Check ANDs of a large unsigned value. We AND the rotated word with
; 0xfdffffff.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilh [[ROT]], 65023
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i8 *%src, i8 253 seq_cst
ret i8 %res
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: oill %r3, 65535
; CHECK-SHIFT2: rll
; Check the minimum signed value. We AND the rotated word with 0x8000ffff.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 -32768 seq_cst
ret i16 %res
; Check ANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfffeffff.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh [[ROT]], 65534
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 -2 seq_cst
ret i16 %res
; Check ANDs of 1. We AND the rotated word with 0x0001ffff.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilh [[ROT]], 1
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 1 seq_cst
ret i16 %res
; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilh [[ROT]], 32767
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 32767 seq_cst
ret i16 %res
; Check ANDs of a large unsigned value. We AND the rotated word with
; 0xfffdffff.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilh [[ROT]], 65533
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw and i16 *%src, i16 65533 seq_cst
ret i16 %res
; Check ANDs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
; Check ANDs of 1.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
; Check ANDs of the low end of the NILH range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh %r0, 0
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 65535 seq_cst
; Check the next value up, which must use NILF.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilf %r0, 65536
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 65536 seq_cst
; Check the largest useful NILL value.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nill %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 -2 seq_cst
; Check the low end of the NILL range.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nill %r0, 0
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 -65536 seq_cst
; Check the largest useful NILH value, which is one less than the above.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nilh %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 -65537 seq_cst
; Check the highest useful NILF value, which is one less than the above.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nilf %r0, 4294901758
; CHECK: br %r14
%res = atomicrmw and i32 *%src, i32 -65538 seq_cst
; Check ANDs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
; Check ANDs of 1, which must be done using a register.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 1 seq_cst
; Check the low end of the NIHF range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
; Check the next value up, which must use a register.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 4294967296 seq_cst
; Check the low end of the NIHH range.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nihh %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 281474976710655 seq_cst
; Check the next value up, which must use a register.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 281474976710656 seq_cst
; Check the highest useful NILL value.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nill %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -2 seq_cst
; Check the low end of the NILL range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nill %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -65536 seq_cst
; Check the highest useful NILH value, which is one less than the above.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: nilh %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -65537 seq_cst
; Check the highest useful NILF value, which is one less than the above.
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: nilf %r0, 4294901758
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -65538 seq_cst
; Check the low end of the NILH range.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: nilh %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -4294901761 seq_cst
; Check the low end of the NILF range.
define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: nilf %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -4294967296 seq_cst
; Check the highest useful NIHL value, which is one less than the above.
define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: nihl %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -4294967297 seq_cst
; Check the low end of the NIHL range.
define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: nihl %r0, 0
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -281470681743361 seq_cst
; Check the highest useful NIHH value, which is 1<<32 less than the above.
define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: nihh %r0, 65534
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -281474976710657 seq_cst
; Check the highest useful NIHF value, which is 1<<32 less than the above.
define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: nihf %r0, 4294901758
; CHECK: br %r14
%res = atomicrmw and i64 *%src, i64 -281479271677953 seq_cst
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
; Check signed maximum.
define i8 @f2(i8 *%src, i8 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
; Check unsigned minimum.
define i8 @f3(i8 *%src, i8 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
; Check unsigned maximum.
define i8 @f4(i8 *%src, i8 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
; Check the lowest useful signed minimum value. We need to load 0x81000000
; into the source register.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llilh [[SRC2:%r[0-9]+]], 33024
; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw min i8 *%src, i8 -127 seq_cst
ret i8 %res
; Check the highest useful signed maximum value. We need to load 0x7e000000
; into the source register.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: llilh [[SRC2:%r[0-9]+]], 32256
; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw max i8 *%src, i8 126 seq_cst
ret i8 %res
; Check the lowest useful unsigned minimum value. We need to load 0x01000000
; into the source register.
define i8 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llilh [[SRC2:%r[0-9]+]], 256
; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
; CHECK-SHIFT2: br %r14
%res = atomicrmw umin i8 *%src, i8 1 seq_cst
ret i8 %res
; Check the highest useful unsigned maximum value. We need to load 0xfe000000
; into the source register.
define i8 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llilh [[SRC2:%r[0-9]+]], 65024
; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 39, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
; CHECK-SHIFT2: br %r14
%res = atomicrmw umax i8 *%src, i8 254 seq_cst
ret i8 %res
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: crjle {{%r[0-9]+}}, %r3
; Check signed maximum.
define i16 @f2(i16 *%src, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: crjhe {{%r[0-9]+}}, %r3
; Check unsigned minimum.
define i16 @f3(i16 *%src, i16 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
; Check unsigned maximum.
define i16 @f4(i16 *%src, i16 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: clr {{%r[0-9]+}}, %r3
; Check the lowest useful signed minimum value. We need to load 0x80010000
; into the source register.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llilh [[SRC2:%r[0-9]+]], 32769
; CHECK: crjle [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw min i16 *%src, i16 -32767 seq_cst
ret i16 %res
; Check the highest useful signed maximum value. We need to load 0x7ffe0000
; into the source register.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: llilh [[SRC2:%r[0-9]+]], 32766
; CHECK: crjhe [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw max i16 *%src, i16 32766 seq_cst
ret i16 %res
; Check the lowest useful unsigned maximum value. We need to load 0x00010000
; into the source register.
define i16 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llilh [[SRC2:%r[0-9]+]], 1
; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f7:
+; CHECK-SHIFT1-LABEL: f7:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f7:
+; CHECK-SHIFT2-LABEL: f7:
; CHECK-SHIFT2: br %r14
%res = atomicrmw umin i16 *%src, i16 1 seq_cst
ret i16 %res
; Check the highest useful unsigned maximum value. We need to load 0xfffe0000
; into the source register.
define i16 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llilh [[SRC2:%r[0-9]+]], 65534
; CHECK: clr [[ROT:%r[0-9]+]], [[SRC2]]
; CHECK: risbg [[ROT]], [[SRC2]], 32, 47, 0
; CHECK: br %r14
;
-; CHECK-SHIFT1: f8:
+; CHECK-SHIFT1-LABEL: f8:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f8:
+; CHECK-SHIFT2-LABEL: f8:
; CHECK-SHIFT2: br %r14
%res = atomicrmw umax i16 *%src, i16 65534 seq_cst
ret i16 %res
; Check signed minium.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: lr [[NEW:%r[0-9]+]], %r2
; Check signed maximum.
define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: lr [[NEW:%r[0-9]+]], %r2
; Check unsigned minimum.
define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: clr %r2, %r4
; Check unsigned maximum.
define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: clr %r2, %r4
; Check the high end of the aligned CS range.
define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: l %r2, 4092(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
; CHECK: br %r14
; Check the next word up, which requires CSY.
define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ly %r2, 4096(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
; CHECK: br %r14
; Check the high end of the aligned CSY range.
define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ly %r2, 524284(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
; CHECK: br %r14
; Check the next word up, which needs separate address logic.
define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, 524288
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
; Check the high end of the negative aligned CSY range.
define i32 @f9(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ly %r2, -4(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
; CHECK: br %r14
; Check the low end of the CSY range.
define i32 @f10(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ly %r2, -524288(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
; CHECK: br %r14
; Check the next word down, which needs separate address logic.
define i32 @f11(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r3, -524292
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
; Check that indexed addresses are not allowed.
define i32 @f12(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: agr %r3, %r4
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
; Check that constants are handled.
define i32 @f13(i32 %dummy, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: lhi [[LIMIT:%r[0-9]+]], 42
; CHECK: l %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; Check signed minium.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: lgr [[NEW:%r[0-9]+]], %r2
; Check signed maximum.
define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: lgr [[NEW:%r[0-9]+]], %r2
; Check unsigned minimum.
define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: clgr %r2, %r4
; Check unsigned maximum.
define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; CHECK: clgr %r2, %r4
; Check the high end of the aligned CSG range.
define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lg %r2, 524280(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
; CHECK: br %r14
; Check the next doubleword up, which requires separate address logic.
define i64 @f6(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
; Check the low end of the CSG range.
define i64 @f7(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lg %r2, -524288(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
; CHECK: br %r14
; Check the next doubleword down, which requires separate address logic.
define i64 @f8(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524296
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
; Check that indexed addresses are not allowed.
define i64 @f9(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agr %r3, %r4
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
; Check that constants are handled.
define i64 @f10(i64 %dummy, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lghi [[LIMIT:%r[0-9]+]], 42
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LOOP:\.[^:]*]]:
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: oilf %r3, 16777215
; CHECK-SHIFT2: rll
; Check the minimum signed value. We AND the rotated word with 0x80ffffff.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 -128 seq_cst
ret i8 %res
; Check NANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfeffffff.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh [[ROT]], 65279
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 -2 seq_cst
ret i8 %res
; Check NANDs of 1. We AND the rotated word with 0x01ffffff.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilh [[ROT]], 511
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 1 seq_cst
ret i8 %res
; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilh [[ROT]], 32767
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 127 seq_cst
ret i8 %res
; Check NANDs of a large unsigned value. We AND the rotated word with
; 0xfdffffff.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilh [[ROT]], 65023
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i8 *%src, i8 253 seq_cst
ret i8 %res
; before being used, and that the low bits are set to 1. This sequence is
; independent of the other loop prologue instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: oill %r3, 65535
; CHECK-SHIFT2: rll
; Check the minimum signed value. We AND the rotated word with 0x8000ffff.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 -32768 seq_cst
ret i16 %res
; Check NANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfffeffff.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh [[ROT]], 65534
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 -2 seq_cst
ret i16 %res
; Check ANDs of 1. We AND the rotated word with 0x0001ffff.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilh [[ROT]], 1
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 1 seq_cst
ret i16 %res
; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nilh [[ROT]], 32767
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 32767 seq_cst
ret i16 %res
; Check NANDs of a large unsigned value. We AND the rotated word with
; 0xfffdffff.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nilh [[ROT]], 65533
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw nand i16 *%src, i16 65533 seq_cst
ret i16 %res
; Check NANDs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
; Check NANDs of 1.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
; Check NANDs of the low end of the NILH range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: nilh %r0, 0
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
; Check the next value up, which must use NILF.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: nilf %r0, 65536
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
; Check the largest useful NILL value.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nill %r0, 65534
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
; Check the low end of the NILL range.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: nill %r0, 0
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
; Check the largest useful NILH value, which is one less than the above.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nilh %r0, 65534
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
; Check the highest useful NILF value, which is one less than the above.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nilf %r0, 4294901758
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
; Check NANDs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
; Check NANDs of 1, which must be done using a register.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw nand i64 *%src, i64 1 seq_cst
; Check the low end of the NIHF range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
; Check the next value up, which must use a register.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw nand i64 *%src, i64 4294967296 seq_cst
; Check the low end of the NIHH range.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: nihh %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the next value up, which must use a register.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ngr
; CHECK: br %r14
%res = atomicrmw nand i64 *%src, i64 281474976710656 seq_cst
; Check the highest useful NILL value.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: nill %r0, 65534
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the low end of the NILL range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: nill %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the highest useful NILH value, which is one less than the above.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: nilh %r0, 65534
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the highest useful NILF value, which is one less than the above.
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: nilf %r0, 4294901758
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the low end of the NILH range.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: nilh %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the low end of the NILF range.
define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: nilf %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the highest useful NIHL value, which is one less than the above.
define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: nihl %r0, 65534
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the low end of the NIHL range.
define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: nihl %r0, 0
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the highest useful NIHH value, which is 1<<32 less than the above.
define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: nihh %r0, 65534
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; Check the highest useful NIHF value, which is 1<<32 less than the above.
define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: nihf %r0, 4294901758
; CHECK: lcgr %r0, %r0
; CHECK: aghi %r0, -1
; before being used. This shift is independent of the other loop prologue
; instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
; Check the minimum signed value. We OR the rotated word with 0x80000000.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 -128 seq_cst
ret i8 %res
; Check ORs of -2 (-1 isn't useful). We OR the rotated word with 0xfe000000.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oilh [[ROT]], 65024
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 -2 seq_cst
ret i8 %res
; Check ORs of 1. We OR the rotated word with 0x01000000.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilh [[ROT]], 256
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 1 seq_cst
ret i8 %res
; Check the maximum signed value. We OR the rotated word with 0x7f000000.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilh [[ROT]], 32512
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 127 seq_cst
ret i8 %res
; Check ORs of a large unsigned value. We OR the rotated word with
; 0xfd000000.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilh [[ROT]], 64768
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i8 *%src, i8 253 seq_cst
ret i8 %res
; before being used. This shift is independent of the other loop prologue
; instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: or {{%r[0-9]+}}, %r3
; Check the minimum signed value. We OR the rotated word with 0x80000000.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 -32768 seq_cst
ret i16 %res
; Check ORs of -2 (-1 isn't useful). We OR the rotated word with 0xfffe0000.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oilh [[ROT]], 65534
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 -2 seq_cst
ret i16 %res
; Check ORs of 1. We OR the rotated word with 0x00010000.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilh [[ROT]], 1
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 1 seq_cst
ret i16 %res
; Check the maximum signed value. We OR the rotated word with 0x7fff0000.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilh [[ROT]], 32767
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 32767 seq_cst
ret i16 %res
; Check ORs of a large unsigned value. We OR the rotated word with
; 0xfffd0000.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilh [[ROT]], 65533
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw or i16 *%src, i16 65533 seq_cst
ret i16 %res
; Check ORs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
; Check the lowest useful OILL value.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
; Check the high end of the OILL range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oill %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 65535 seq_cst
; Check the lowest useful OILH value, which is the next value up.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilh %r0, 1
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 65536 seq_cst
; Check the lowest useful OILF value, which is the next value up.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilf %r0, 65537
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 65537 seq_cst
; Check the high end of the OILH range.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilh %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 -65536 seq_cst
; Check the next value up, which must use OILF.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oilf %r0, 4294901761
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 -65535 seq_cst
; Check the largest useful OILF value.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: oilf %r0, 4294967294
; CHECK: br %r14
%res = atomicrmw or i32 *%src, i32 -2 seq_cst
; Check ORs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lgr %r0, %r2
; Check the lowest useful OILL value.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lgr %r0, %r2
; Check the high end of the OILL range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oill %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 65535 seq_cst
; Check the lowest useful OILH value, which is the next value up.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilh %r0, 1
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 65536 seq_cst
; Check the lowest useful OILF value, which is the next value up again.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilf %r0, 65537
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 65537 seq_cst
; Check the high end of the OILH range.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilh %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294901760 seq_cst
; Check the next value up, which must use OILF.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oilf %r0, 4294901761
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294901761 seq_cst
; Check the high end of the OILF range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: oilf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294967295 seq_cst
; Check the lowest useful OIHL value, which is one greater than above.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: oihl %r0, 1
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294967296 seq_cst
; Check the next value up, which must use a register. (We could use
; combinations of OIH* and OIL* instead, but that isn't implemented.)
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ogr
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 4294967297 seq_cst
; Check the high end of the OIHL range.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: oihl %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 281470681743360 seq_cst
; Check the lowest useful OIHH value, which is 1<<32 greater than above.
define i64 @f12(i64 %dummy, i64 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: oihh %r0, 1
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 281474976710656 seq_cst
; Check the lowest useful OIHF value, which is 1<<32 greater again.
define i64 @f13(i64 %dummy, i64 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: oihf %r0, 65537
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 281479271677952 seq_cst
; Check the high end of the OIHH range.
define i64 @f14(i64 %dummy, i64 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: oihh %r0, 65535
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 18446462598732840960 seq_cst
; Check the next value up, which must use a register.
define i64 @f15(i64 %dummy, i64 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: ogr
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 18446462598732840961 seq_cst
; Check the high end of the OIHF range.
define i64 @f16(i64 %dummy, i64 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: oihf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw or i64 *%src, i64 -4294967296 seq_cst
; before being used. This shift is independent of the other loop prologue
; instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
; Check the minimum signed value. We add 0x80000000 to the rotated word.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 -128 seq_cst
ret i8 %res
; Check subtraction of -1. We add 0x01000000 to the rotated word.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi [[ROT]], 16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 -1 seq_cst
ret i8 %res
; Check subtraction of -1. We add 0xff000000 to the rotated word.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi [[ROT]], -16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 1 seq_cst
ret i8 %res
; Check the maximum signed value. We add 0x81000000 to the rotated word.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi [[ROT]], -2130706432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 127 seq_cst
ret i8 %res
; Check subtraction of a large unsigned value. We add 0x02000000 to the
; rotated word.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi [[ROT]], 33554432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i8 *%src, i8 254 seq_cst
ret i8 %res
; before being used. This shift is independent of the other loop prologue
; instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: sr {{%r[0-9]+}}, %r3
; Check the minimum signed value. We add 0x80000000 to the rotated word.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 -32768 seq_cst
ret i16 %res
; Check subtraction of -1. We add 0x00010000 to the rotated word.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi [[ROT]], 65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 -1 seq_cst
ret i16 %res
; Check subtraction of 1. We add 0xffff0000 to the rotated word.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi [[ROT]], -65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 1 seq_cst
ret i16 %res
; Check the maximum signed value. We add 0x80010000 to the rotated word.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi [[ROT]], -2147418112
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 32767 seq_cst
ret i16 %res
; Check subtraction of a large unsigned value. We add 0x00020000 to the
; rotated word.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi [[ROT]], 131072
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw sub i16 *%src, i16 65534 seq_cst
ret i16 %res
; Check subtraction of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2
; Check subtraction of 1, which can use AHI.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lr %r0, %r2
; Check the low end of the AHI range.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ahi %r0, -32768
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 32768 seq_cst
; Check the next value down, which must use AFI.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi %r0, -32769
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 32769 seq_cst
; Check the low end of the AFI range.
define i32 @f5(i32 %dummy, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi %r0, -2147483648
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 2147483648 seq_cst
; Check the next value up, which gets treated as a positive operand.
define i32 @f6(i32 %dummy, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: afi %r0, 2147483647
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 2147483649 seq_cst
; Check subtraction of -1, which can use AHI.
define i32 @f7(i32 %dummy, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ahi %r0, 1
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 -1 seq_cst
; Check the high end of the AHI range.
define i32 @f8(i32 %dummy, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ahi %r0, 32767
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 -32767 seq_cst
; Check the next value down, which must use AFI instead.
define i32 @f9(i32 %dummy, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: afi %r0, 32768
; CHECK: br %r14
%res = atomicrmw sub i32 *%src, i32 -32768 seq_cst
; Check subtraction of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
; Check subtraction of 1, which can use AGHI.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: lgr %r0, %r2
; Check the low end of the AGHI range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r0, -32768
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 32768 seq_cst
; Check the next value up, which must use AGFI.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r0, -32769
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 32769 seq_cst
; Check the low end of the AGFI range.
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r0, -2147483648
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 2147483648 seq_cst
; Check the next value up, which must use a register operation.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sgr
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 2147483649 seq_cst
; Check subtraction of -1, which can use AGHI.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: aghi %r0, 1
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -1 seq_cst
; Check the high end of the AGHI range.
define i64 @f8(i64 %dummy, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r0, 32767
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -32767 seq_cst
; Check the next value down, which must use AGFI instead.
define i64 @f9(i64 %dummy, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r0, 32768
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -32768 seq_cst
; Check the high end of the AGFI range.
define i64 @f10(i64 %dummy, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r0, 2147483647
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -2147483647 seq_cst
; Check the next value down, which must use a register operation.
define i64 @f11(i64 %dummy, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: sgr
; CHECK: br %r14
%res = atomicrmw sub i64 *%src, i64 -2147483648 seq_cst
; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word).
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT-NOT: %r3
; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT-NOT: %r3
; Check exchange with a constant. We should force the constant into
; a register and use the sequence above.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi [[VALUE:%r[0-9]+]], 88
; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 39, 24
; CHECK: br %r14
;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
; CHECK-SHIFT: br %r14
%res = atomicrmw xchg i8 *%src, i8 88 seq_cst
ret i8 %res
; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word).
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT-NOT: %r3
; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT-NOT: %r3
; Check exchange with a constant. We should force the constant into
; a register and use the sequence above.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi [[VALUE:%r[0-9]+]], -25536
; CHECK: risbg {{%r[0-9]+}}, [[VALUE]], 32, 47, 16
; CHECK: br %r14
;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
; CHECK-SHIFT: br %r14
%res = atomicrmw xchg i16 *%src, i16 40000 seq_cst
ret i16 %res
; Check register exchange.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: cs %r2, %r4, 0(%r3)
; Check the high end of the aligned CS range.
define i32 @f2(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 4092(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 4092(%r3)
; CHECK: br %r14
; Check the next word up, which requires CSY.
define i32 @f3(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ly %r2, 4096(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, 4096(%r3)
; CHECK: br %r14
; Check the high end of the aligned CSY range.
define i32 @f4(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ly %r2, 524284(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, 524284(%r3)
; CHECK: br %r14
; Check the next word up, which needs separate address logic.
define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, 524288
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
; Check the high end of the negative aligned CSY range.
define i32 @f6(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ly %r2, -4(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, -4(%r3)
; CHECK: br %r14
; Check the low end of the CSY range.
define i32 @f7(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ly %r2, -524288(%r3)
; CHECK: csy %r2, {{%r[0-9]+}}, -524288(%r3)
; CHECK: br %r14
; Check the next word down, which needs separate address logic.
define i32 @f8(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524292
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
; Check that indexed addresses are not allowed.
define i32 @f9(i32 %dummy, i64 %base, i64 %index, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agr %r3, %r4
; CHECK: l %r2, 0(%r3)
; CHECK: cs %r2, {{%r[0-9]+}}, 0(%r3)
; Check exchange of a constant. We should force it into a register and
; use the sequence above.
define i32 @f10(i32 %dummy, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llill [[VALUE:%r[0-9+]]], 40000
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; Check register exchange.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; CHECK: csg %r2, %r4, 0(%r3)
; Check the high end of the aligned CSG range.
define i64 @f2(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 524280(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 524280(%r3)
; CHECK: br %r14
; Check the next doubleword up, which requires separate address logic.
define i64 @f3(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r3, 524288
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
; Check the low end of the CSG range.
define i64 @f4(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lg %r2, -524288(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, -524288(%r3)
; CHECK: br %r14
; Check the next doubleword down, which requires separate address logic.
define i64 @f5(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, -524296
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
; Check that indexed addresses are not allowed.
define i64 @f6(i64 %dummy, i64 %base, i64 %index, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agr %r3, %r4
; CHECK: lg %r2, 0(%r3)
; CHECK: csg %r2, {{%r[0-9]+}}, 0(%r3)
; Check exchange of a constant. We should force it into a register and
; use the sequence above.
define i64 @f7(i64 %dummy, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llilf [[VALUE:%r[0-9+]]], 3000000000
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^:]*]]:
; before being used. This shift is independent of the other loop prologue
; instructions.
define i8 @f1(i8 *%src, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 24
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
; Check the minimum signed value. We XOR the rotated word with 0x80000000.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 8([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 -128 seq_cst
ret i8 %res
; Check XORs of -1. We XOR the rotated word with 0xff000000.
define i8 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf [[ROT]], 4278190080
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 -1 seq_cst
ret i8 %res
; Check XORs of 1. We XOR the rotated word with 0x01000000.
define i8 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xilf [[ROT]], 16777216
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 1 seq_cst
ret i8 %res
; Check the maximum signed value. We XOR the rotated word with 0x7f000000.
define i8 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xilf [[ROT]], 2130706432
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 127 seq_cst
ret i8 %res
; Check XORs of a large unsigned value. We XOR the rotated word with
; 0xfd000000.
define i8 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xilf [[ROT]], 4244635648
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i8 *%src, i8 253 seq_cst
ret i8 %res
; before being used. This shift is independent of the other loop prologue
; instructions.
define i16 @f1(i16 *%src, i16 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f1:
+; CHECK-SHIFT1-LABEL: f1:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f1:
+; CHECK-SHIFT2-LABEL: f1:
; CHECK-SHIFT2: sll %r3, 16
; CHECK-SHIFT2: rll
; CHECK-SHIFT2: xr {{%r[0-9]+}}, %r3
; Check the minimum signed value. We XOR the rotated word with 0x80000000.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-DAG: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-DAG: risbg [[BASE:%r[1-9]+]], %r2, 0, 189, 0
; CHECK: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK: rll %r2, [[OLD]], 16([[SHIFT]])
; CHECK: br %r14
;
-; CHECK-SHIFT1: f2:
+; CHECK-SHIFT1-LABEL: f2:
; CHECK-SHIFT1: sllg [[SHIFT:%r[1-9]+]], %r2, 3
; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: rll
; CHECK-SHIFT1: br %r14
;
-; CHECK-SHIFT2: f2:
+; CHECK-SHIFT2-LABEL: f2:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 -32768 seq_cst
ret i16 %res
; Check XORs of -1. We XOR the rotated word with 0xffff0000.
define i16 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf [[ROT]], 4294901760
; CHECK: br %r14
;
-; CHECK-SHIFT1: f3:
+; CHECK-SHIFT1-LABEL: f3:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f3:
+; CHECK-SHIFT2-LABEL: f3:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 -1 seq_cst
ret i16 %res
; Check XORs of 1. We XOR the rotated word with 0x00010000.
define i16 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xilf [[ROT]], 65536
; CHECK: br %r14
;
-; CHECK-SHIFT1: f4:
+; CHECK-SHIFT1-LABEL: f4:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f4:
+; CHECK-SHIFT2-LABEL: f4:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 1 seq_cst
ret i16 %res
; Check the maximum signed value. We XOR the rotated word with 0x7fff0000.
define i16 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xilf [[ROT]], 2147418112
; CHECK: br %r14
;
-; CHECK-SHIFT1: f5:
+; CHECK-SHIFT1-LABEL: f5:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f5:
+; CHECK-SHIFT2-LABEL: f5:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 32767 seq_cst
ret i16 %res
; Check XORs of a large unsigned value. We XOR the rotated word with
; 0xfffd0000.
define i16 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xilf [[ROT]], 4294770688
; CHECK: br %r14
;
-; CHECK-SHIFT1: f6:
+; CHECK-SHIFT1-LABEL: f6:
; CHECK-SHIFT1: br %r14
-; CHECK-SHIFT2: f6:
+; CHECK-SHIFT2-LABEL: f6:
; CHECK-SHIFT2: br %r14
%res = atomicrmw xor i16 *%src, i16 65533 seq_cst
ret i16 %res
; Check XORs of a variable.
define i32 @f1(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
; Check the lowest useful constant.
define i32 @f2(i32 %dummy, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lr %r0, %r2
; Check an arbitrary constant.
define i32 @f3(i32 %dummy, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf %r0, 3000000000
; CHECK: br %r14
%res = atomicrmw xor i32 *%src, i32 3000000000 seq_cst
; Check bitwise negation.
define i32 @f4(i32 %dummy, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw xor i32 *%src, i32 -1 seq_cst
; Check XORs of a variable.
define i64 @f1(i64 %dummy, i64 *%src, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lgr %r0, %r2
; Check the lowest useful XILF value.
define i64 @f2(i64 %dummy, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 0(%r3)
; CHECK: [[LABEL:\.[^ ]*]]:
; CHECK: lgr %r0, %r2
; Check the high end of the XILF range.
define i64 @f3(i64 %dummy, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 4294967295 seq_cst
; Check the lowest useful XIHF value, which is one greater than above.
define i64 @f4(i64 %dummy, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xihf %r0, 1
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 4294967296 seq_cst
; Check the next value up, which must use a register. (We could use
; combinations of XIH* and XIL* instead, but that isn't implemented.)
define i64 @f5(i64 %dummy, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xgr
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 4294967297 seq_cst
; Check the high end of the XIHF range.
define i64 @f6(i64 %dummy, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xihf %r0, 4294967295
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 -4294967296 seq_cst
; Check the next value up, which must use a register.
define i64 @f7(i64 %dummy, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: xgr
; CHECK: br %r14
%res = atomicrmw xor i64 *%src, i64 -4294967295 seq_cst
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .L[[LABEL:.*]]:
; CHECK: mvi 0(%r2), 1
; CHECK: j .L[[LABEL]]
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
}
define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
}
define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
}
define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
}
define void @f5(i32 *%src, i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
}
define void @f6(i32 *%src, i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: c %r3, 0(%r2)
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(i32 *%src, i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: cl %r3, 0(%r2)
}
define void @f2(i32 *%src, i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: cl %r3, 0(%r2)
}
define void @f3(i32 *%src, i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: cl %r3, 0(%r2)
}
define void @f4(i32 *%src, i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: cl %r3, 0(%r2)
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define void @f1(float *%src, float %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f2(float *%src, float %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f3(float *%src, float %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f4(float *%src, float %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f5(float *%src, float %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f6(float *%src, float %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f7(float *%src, float %target) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f8(float *%src, float %target) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f9(float *%src, float %target) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f10(float *%src, float %target) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f11(float *%src, float %target) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
}
define void @f12(float *%src, float %target) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
; "jno" == "jump if no overflow", which corresponds to "jump if ordered"
; rather than "jump if not ordered" after a floating-point comparison.
define void @f13(float *%src, float %target) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
; "jo" == "jump if overflow", which corresponds to "jump if not ordered"
; rather than "jump if ordered" after a floating-point comparison.
define void @f14(float *%src, float %target) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: .cfi_startproc
; CHECK: .L[[LABEL:.*]]:
; CHECK: ceb %f0, 0(%r2)
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
define i32 @f1(i32 %x, i32 %y, i32 %op) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ahi %r4, -1
; CHECK: clfi %r4, 5
; CHECK-NEXT: jh
declare i32 @foo()
define void @f1(i32 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crje %r2, {{%r[0-9]+}}, .L[[LABEL]]
}
define void @f2(i32 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
}
define void @f3(i32 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
}
define void @f4(i32 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
}
define void @f5(i32 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
}
define void @f6(i32 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: crjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
; Test EQ.
define void @f1(i64 %target) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrje %r2, {{%r[0-9]+}}, .L[[LABEL]]
; Test NE.
define void @f2(i64 %target) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjlh %r2, {{%r[0-9]+}}, .L[[LABEL]]
; Test SLE.
define void @f3(i64 %target) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjle %r2, {{%r[0-9]+}}, .L[[LABEL]]
; Test SLT.
define void @f4(i64 %target) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjl %r2, {{%r[0-9]+}}, .L[[LABEL]]
; Test SGT.
define void @f5(i64 %target) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjh %r2, {{%r[0-9]+}}, .L[[LABEL]]
; Test SGE.
define void @f6(i64 %target) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: .cfi_def_cfa_offset
; CHECK: .L[[LABEL:.*]]:
; CHECK: cgrjhe %r2, {{%r[0-9]+}}, .L[[LABEL]]
; Test a vector of 0/-1 results for i32 EQ.
define i64 @f7(i64 %a, i64 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: crje {{%r[0-5]}}
; CHECK: lhi [[REG]], 0
; Test a vector of 0/-1 results for i32 NE.
define i64 @f8(i64 %a, i64 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lhi [[REG:%r[0-5]]], -1
; CHECK: crjlh {{%r[0-5]}}
; CHECK: lhi [[REG]], 0
; Test a vector of 0/-1 results for i64 EQ.
define void @f9(i64 %a, i64 %b, <2 x i64> *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lghi [[REG:%r[0-5]]], -1
; CHECK: crje {{%r[0-5]}}
; CHECK: lghi [[REG]], 0
; Test a vector of 0/-1 results for i64 NE.
define void @f10(i64 %a, i64 %b, <2 x i64> *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lghi [[REG:%r[0-5]]], -1
; CHECK: crjlh {{%r[0-5]}}
; CHECK: lghi [[REG]], 0
; Check 32-bit register-to-register byteswaps.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lrvr [[REGISTER:%r[0-5]]], %r2
; CHECK: br %r14
%swapped = call i32 @llvm.bswap.i32(i32 %a)
; Check 64-bit register-to-register byteswaps.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lrvgr %r2, %r2
; CHECK: br %r14
%swapped = call i64 @llvm.bswap.i64(i64 %a)
; Check LRV with no displacement.
define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lrv %r2, 0(%r2)
; CHECK: br %r14
%a = load i32 *%src
; Check the high end of the aligned LRV range.
define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lrv %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: lrv %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned LRV range.
define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lrv %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the LRV range.
define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lrv %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524292
; CHECK: lrv %r2, 0(%r2)
; CHECK: br %r14
; Check that LRV allows an index.
define i32 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lrv %r2, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that volatile accesses do not use LRV, which might access the
; storage multple times.
define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: l [[REG:%r[0-5]]], 0(%r2)
; CHECK: lrvr %r2, [[REG]]
; CHECK: br %r14
; Test a case where we spill the source of at least one LRVR. We want
; to use LRV if possible.
define void @f9(i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lrv {{%r[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 *%ptr
; Check LRVG with no displacement.
define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lrvg %r2, 0(%r2)
; CHECK: br %r14
%a = load i64 *%src
; Check the high end of the aligned LRVG range.
define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lrvg %r2, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: lrvg %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned LRVG range.
define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lrvg %r2, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the LRVG range.
define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lrvg %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524296
; CHECK: lrvg %r2, 0(%r2)
; CHECK: br %r14
; Check that LRVG allows an index.
define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lrvg %r2, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that volatile accesses do not use LRVG, which might access the
; storage multple times.
define i64 @f8(i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
; CHECK: lrvgr %r2, [[REG]]
; CHECK: br %r14
; Test a case where we spill the source of at least one LRVGR. We want
; to use LRVG if possible.
define void @f9(i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lrvg {{%r[0-9]+}}, 160(%r15)
; CHECK: br %r14
%val0 = load volatile i64 *%ptr
; Check STRV with no displacement.
define void @f1(i32 *%dst, i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: strv %r3, 0(%r2)
; CHECK: br %r14
%swapped = call i32 @llvm.bswap.i32(i32 %a)
; Check the high end of the aligned STRV range.
define void @f2(i32 *%dst, i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: strv %r3, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f3(i32 *%dst, i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: strv %r3, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned STRV range.
define void @f4(i32 *%dst, i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: strv %r3, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 -1
; Check the low end of the STRV range.
define void @f5(i32 *%dst, i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: strv %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i32 *%dst, i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524292
; CHECK: strv %r3, 0(%r2)
; CHECK: br %r14
; Check that STRV allows an index.
define void @f7(i64 %src, i64 %index, i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: strv %r4, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that volatile stores do not use STRV, which might access the
; storage multple times.
define void @f8(i32 *%dst, i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lrvr [[REG:%r[0-5]]], %r3
; CHECK: st [[REG]], 0(%r2)
; CHECK: br %r14
; Check STRVG with no displacement.
define void @f1(i64 *%dst, i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: strvg %r3, 0(%r2)
; CHECK: br %r14
%swapped = call i64 @llvm.bswap.i64(i64 %a)
; Check the high end of the aligned STRVG range.
define void @f2(i64 *%dst, i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: strvg %r3, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f3(i64 *%dst, i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: strvg %r3, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned STRVG range.
define void @f4(i64 *%dst, i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: strvg %r3, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 -1
; Check the low end of the STRVG range.
define void @f5(i64 *%dst, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: strvg %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i64 *%dst, i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524296
; CHECK: strvg %r3, 0(%r2)
; CHECK: br %r14
; Check that STRVG allows an index.
define void @f7(i64 %src, i64 %index, i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: strvg %r4, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that volatile stores do not use STRVG, which might access the
; storage multple times.
define void @f8(i64 *%dst, i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lrvgr [[REG:%r[0-5]]], %r3
; CHECK: stg [[REG]], 0(%r2)
; CHECK: br %r14
; We must allocate 160 bytes for the callee and save and restore %r14.
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK: aghi %r15, -160
; CHECK: brasl %r14, bar@PLT
; We must allocate 160 bytes for the callee and save and restore %r14.
define i64 @f1(i64() *%bar) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK: aghi %r15, -160
; CHECK: basr %r14, %r2
; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word).
define i8 @f1(i8 %dummy, i8 *%src, i8 %cmp, i8 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK-MAIN-NOT: %r2
; CHECK-MAIN: br %r14
;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT: rll
; Check compare and swap with constants. We should force the constants into
; registers and use the sequence above.
define i8 @f2(i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi [[CMP:%r[0-9]+]], 42
; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 55, 0
; CHECK: risbg
; CHECK: br %r14
;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
; CHECK-SHIFT: risbg
; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 55, 0
; being used in the RISBG (in contrast to things like atomic addition,
; which shift %r3 left so that %b is at the high end of the word).
define i16 @f1(i16 %dummy, i16 *%src, i16 %cmp, i16 %swap) {
-; CHECK-MAIN: f1:
+; CHECK-MAIN-LABEL: f1:
; CHECK-MAIN-DAG: sllg [[SHIFT:%r[1-9]+]], %r3, 3
; CHECK-MAIN-DAG: risbg [[BASE:%r[1-9]+]], %r3, 0, 189, 0
; CHECK-MAIN: l [[OLD:%r[0-9]+]], 0([[BASE]])
; CHECK-MAIN-NOT: %r2
; CHECK-MAIN: br %r14
;
-; CHECK-SHIFT: f1:
+; CHECK-SHIFT-LABEL: f1:
; CHECK-SHIFT: sllg [[SHIFT:%r[1-9]+]], %r3, 3
; CHECK-SHIFT: lcr [[NEGSHIFT:%r[1-9]+]], [[SHIFT]]
; CHECK-SHIFT: rll
; Check compare and swap with constants. We should force the constants into
; registers and use the sequence above.
define i16 @f2(i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi [[CMP:%r[0-9]+]], 42
; CHECK: risbg [[CMP]], {{%r[0-9]+}}, 32, 47, 0
; CHECK: risbg
; CHECK: br %r14
;
-; CHECK-SHIFT: f2:
+; CHECK-SHIFT-LABEL: f2:
; CHECK-SHIFT: lhi [[SWAP:%r[0-9]+]], 88
; CHECK-SHIFT: risbg
; CHECK-SHIFT: risbg [[SWAP]], {{%r[0-9]+}}, 32, 47, 0
; Check the low end of the CS range.
define i32 @f1(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
%val = cmpxchg i32 *%src, i32 %cmp, i32 %swap seq_cst
; Check the high end of the aligned CS range.
define i32 @f2(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cs %r2, %r3, 4092(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
; Check the next word up, which should use CSY instead of CS.
define i32 @f3(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: csy %r2, %r3, 4096(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
; Check the high end of the aligned CSY range.
define i32 @f4(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: csy %r2, %r3, 524284(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f5(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r4, 524288
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
; Check the high end of the negative aligned CSY range.
define i32 @f6(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: csy %r2, %r3, -4(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the CSY range.
define i32 @f7(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: csy %r2, %r3, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i32 %cmp, i32 %swap, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r4, -524292
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
; Check that CS does not allow an index.
define i32 @f9(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agr %r4, %r5
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
; Check that CSY does not allow an index.
define i32 @f10(i32 %cmp, i32 %swap, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agr %r4, %r5
; CHECK: csy %r2, %r3, 4096(%r4)
; CHECK: br %r14
; Check that a constant %cmp value is loaded into a register first.
define i32 @f11(i32 %dummy, i32 %swap, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: lhi %r2, 1001
; CHECK: cs %r2, %r3, 0(%r4)
; CHECK: br %r14
; Check that a constant %swap value is loaded into a register first.
define i32 @f12(i32 %cmp, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: lhi [[SWAP:%r[0-9]+]], 1002
; CHECK: cs %r2, [[SWAP]], 0(%r3)
; CHECK: br %r14
; Check CSG without a displacement.
define i64 @f1(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
%val = cmpxchg i64 *%src, i64 %cmp, i64 %swap seq_cst
; Check the high end of the aligned CSG range.
define i64 @f2(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: csg %r2, %r3, 524280(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f3(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r4, 524288
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
; Check the high end of the negative aligned CSG range.
define i64 @f4(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: csg %r2, %r3, -8(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the CSG range.
define i64 @f5(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: csg %r2, %r3, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i64 %cmp, i64 %swap, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r4, -524296
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
; Check that CSG does not allow an index.
define i64 @f7(i64 %cmp, i64 %swap, i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agr %r4, %r5
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
; Check that a constant %cmp value is loaded into a register first.
define i64 @f8(i64 %dummy, i64 %swap, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lghi %r2, 1001
; CHECK: csg %r2, %r3, 0(%r4)
; CHECK: br %r14
; Check that a constant %swap value is loaded into a register first.
define i64 @f9(i64 %cmp, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lghi [[SWAP:%r[0-9]+]], 1002
; CHECK: csg %r2, [[SWAP]], 0(%r3)
; CHECK: br %r14
; Test the simple case, with the loaded value first.
define void @f1(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f2(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly sign-extended to 32 bits, with the
; loaded value first.
define void @f3(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f4(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly zero-extended to 32 bits, with the
; loaded value first.
define void @f5(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f6(i8 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly sign-extended to 64 bits, with the
; loaded value first.
define void @f7(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f8(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly zero-extended to 64 bits, with the
; loaded value first.
define void @f9(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f10(i8 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the STC range.
define void @f11(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next byte up, which should use STCY instead of STC.
define void @f12(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the STCY range.
define void @f13(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f14(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the low end of the STCY range.
define void @f15(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f16(i8 *%base, i8 %alt, i32 %limit) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that STCY allows an index.
define void @f17(i64 %base, i64 %index, i8 %alt, i32 %limit) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that volatile loads are not matched.
define void @f18(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: lb {{%r[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores. In this case we should have a conditional load into %r3.
define void @f19(i8 *%ptr, i8 %alt, i32 %limit) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lb %r3, 0(%r2)
; CHECK: [[LABEL]]:
; to restrict the test to a stronger ordering.
define void @f20(i8 *%ptr, i8 %alt, i32 %limit) {
; FIXME: should use a normal load instead of CS.
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: cs {{%r[0-9]+}},
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores.
define void @f21(i8 *%ptr, i8 %alt, i32 %limit) {
; FIXME: should use a normal store instead of CS.
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lb %r3, 0(%r2)
; CHECK: [[LABEL]]:
; Try a frame index base.
define void @f22(i8 %alt, i32 %limit) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK: brasl %r14, foo@PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
; Test the simple case, with the loaded value first.
define void @f1(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f2(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly sign-extended to 32 bits, with the
; loaded value first.
define void @f3(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f4(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly zero-extended to 32 bits, with the
; loaded value first.
define void @f5(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f6(i16 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly sign-extended to 64 bits, with the
; loaded value first.
define void @f7(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f8(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly zero-extended to 64 bits, with the
; loaded value first.
define void @f9(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f10(i16 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned STH range.
define void @f11(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next halfword up, which should use STHY instead of STH.
define void @f12(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned STHY range.
define void @f13(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f14(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the low end of the STHY range.
define void @f15(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f16(i16 *%base, i16 %alt, i32 %limit) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that STHY allows an index.
define void @f17(i64 %base, i64 %index, i16 %alt, i32 %limit) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that volatile loads are not matched.
define void @f18(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: lh {{%r[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores. In this case we should have a conditional load into %r3.
define void @f19(i16 *%ptr, i16 %alt, i32 %limit) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lh %r3, 0(%r2)
; CHECK: [[LABEL]]:
; to restrict the test to a stronger ordering.
define void @f20(i16 *%ptr, i16 %alt, i32 %limit) {
; FIXME: should use a normal load instead of CS.
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: cs {{%r[0-9]+}},
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores.
define void @f21(i16 *%ptr, i16 %alt, i32 %limit) {
; FIXME: should use a normal store instead of CS.
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lh %r3, 0(%r2)
; CHECK: [[LABEL]]:
; Try a frame index base.
define void @f22(i16 %alt, i32 %limit) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK: brasl %r14, foo@PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
; Test the simple case, with the loaded value first.
define void @f1(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f2(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly sign-extended to 64 bits, with the
; loaded value first.
define void @f3(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f4(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Test cases where the value is explicitly zero-extended to 32 bits, with the
; loaded value first.
define void @f5(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f6(i32 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned ST range.
define void @f7(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next word up, which should use STY instead of ST.
define void @f8(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned STY range.
define void @f9(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f10(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the low end of the STY range.
define void @f11(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f12(i32 *%base, i32 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that STY allows an index.
define void @f13(i64 %base, i64 %index, i32 %alt, i32 %limit) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that volatile loads are not matched.
define void @f14(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: l {{%r[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores. In this case we should have a conditional load into %r3.
define void @f15(i32 *%ptr, i32 %alt, i32 %limit) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: l %r3, 0(%r2)
; CHECK: [[LABEL]]:
; to restrict the test to a stronger ordering.
define void @f16(i32 *%ptr, i32 %alt, i32 %limit) {
; FIXME: should use a normal load instead of CS.
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: cs {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores.
define void @f17(i32 *%ptr, i32 %alt, i32 %limit) {
; FIXME: should use a normal store instead of CS.
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: l %r3, 0(%r2)
; CHECK: [[LABEL]]:
; Try a frame index base.
define void @f18(i32 %alt, i32 %limit) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: brasl %r14, foo@PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
; Test with the loaded value first.
define void @f1(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f2(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned STG range.
define void @f3(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f4(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the low end of the STG range.
define void @f5(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i64 *%base, i64 %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that STG allows an index.
define void @f7(i64 %base, i64 %index, i64 %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that volatile loads are not matched.
define void @f8(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lg {{%r[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores. In this case we should have a conditional load into %r3.
define void @f9(i64 *%ptr, i64 %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lg %r3, 0(%r2)
; CHECK: [[LABEL]]:
; to restrict the test to a stronger ordering.
define void @f10(i64 *%ptr, i64 %alt, i32 %limit) {
; FIXME: should use a normal load instead of CSG.
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: csg {{%r[0-5]}}, {{%r[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores.
define void @f11(i64 *%ptr, i64 %alt, i32 %limit) {
; FIXME: should use a normal store instead of CSG.
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: lg %r3, 0(%r2)
; CHECK: [[LABEL]]:
; Try a frame index base.
define void @f12(i64 %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
; Test with the loaded value first.
define void @f1(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f2(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned STE range.
define void @f3(float *%base, float %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next word up, which should use STEY instead of STE.
define void @f4(float *%base, float %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned STEY range.
define void @f5(float *%base, float %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(float *%base, float %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the low end of the STEY range.
define void @f7(float *%base, float %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(float *%base, float %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that STEY allows an index.
define void @f9(i64 %base, i64 %index, float %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that volatile loads are not matched.
define void @f10(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: le {{%f[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores. In this case we should have a conditional load into %f0.
define void @f11(float *%ptr, float %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: le %f0, 0(%r2)
; CHECK: [[LABEL]]:
; Try a frame index base.
define void @f12(float %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
; Test with the loaded value first.
define void @f1(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; ...and with the loaded value second
define void @f2(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned STD range.
define void @f3(double *%base, double %alt, i32 %limit) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next doubleword up, which should use STDY instead of STD.
define void @f4(double *%base, double %alt, i32 %limit) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the high end of the aligned STDY range.
define void @f5(double *%base, double %alt, i32 %limit) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(double *%base, double %alt, i32 %limit) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the low end of the STDY range.
define void @f7(double *%base, double %alt, i32 %limit) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(double *%base, double %alt, i32 %limit) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that STDY allows an index.
define void @f9(i64 %base, i64 %index, double %alt, i32 %limit) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: %r2
; CHECK: jl [[LABEL:[^ ]*]]
; CHECK-NOT: %r2
; Check that volatile loads are not matched.
define void @f10(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ld {{%f[0-5]}}, 0(%r2)
; CHECK: {{jl|jnl}} [[LABEL:[^ ]*]]
; CHECK: [[LABEL]]:
; ...likewise stores. In this case we should have a conditional load into %f0.
define void @f11(double *%ptr, double %alt, i32 %limit) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: jnl [[LABEL:[^ ]*]]
; CHECK: ld %f0, 0(%r2)
; CHECK: [[LABEL]]:
; Try a frame index base.
define void @f12(double %alt, i32 %limit) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK-NOT: %r15
; CHECK: jl [[LABEL:[^ ]*]]
; Test f32.
declare float @llvm.fabs.f32(float %f)
define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lpebr %f0, %f0
; CHECK: br %r14
%res = call float @llvm.fabs.f32(float %f)
; Test f64.
declare double @llvm.fabs.f64(double %f)
define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lpdbr %f0, %f0
; CHECK: br %r14
%res = call double @llvm.fabs.f64(double %f)
; processing so that using FPRs is unequivocally better.
declare fp128 @llvm.fabs.f128(fp128 %f)
define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lpxbr
; CHECK: dxbr
; CHECK: br %r14
; Test f32.
declare float @llvm.fabs.f32(float %f)
define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lnebr %f0, %f0
; CHECK: br %r14
%abs = call float @llvm.fabs.f32(float %f)
; Test f64.
declare double @llvm.fabs.f64(double %f)
define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lndbr %f0, %f0
; CHECK: br %r14
%abs = call double @llvm.fabs.f64(double %f)
; extra processing so that using FPRs is unequivocally better.
declare fp128 @llvm.fabs.f128(fp128 %f)
define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lnxbr
; CHECK: dxbr
; CHECK: br %r14
; Check register addition.
define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: aebr %f0, %f2
; CHECK: br %r14
%res = fadd float %f1, %f2
; Check the low end of the AEB range.
define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aeb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load float *%ptr
; Check the high end of the aligned AEB range.
define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aeb %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%base, i64 1023
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: aeb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: aeb %f0, 0(%r2)
; CHECK: br %r14
; Check that AEB allows indices.
define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: aeb %f0, 400(%r1,%r2)
; CHECK: br %r14
; Check that additions of spilled values can use AEB rather than AEBR.
define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: aeb %f0, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check register addition.
define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: adbr %f0, %f2
; CHECK: br %r14
%res = fadd double %f1, %f2
; Check the low end of the ADB range.
define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: adb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load double *%ptr
; Check the high end of the aligned ADB range.
define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: adb %f0, 4088(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%base, i64 511
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: adb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -8
; CHECK: adb %f0, 0(%r2)
; CHECK: br %r14
; Check that ADB allows indices.
define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 3
; CHECK: adb %f0, 800(%r1,%r2)
; CHECK: br %r14
; Check that additions of spilled values can use ADB rather than ADBR.
define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: adb %f0, 160(%r15)
; CHECK: br %r14
; There is no memory form of 128-bit addition.
define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r2)
; CHECK: ld %f3, 8(%r2)
; Check comparison with registers.
define i64 @f1(i64 %a, i64 %b, float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cebr %f0, %f2
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; Check the low end of the CEB range.
define i64 @f2(i64 %a, i64 %b, float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ceb %f0, 0(%r4)
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; Check the high end of the aligned CEB range.
define i64 @f3(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ceb %f0, 4092(%r4)
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r4, 4096
; CHECK: ceb %f0, 0(%r4)
; CHECK-NEXT: je
; Check negative displacements, which also need separate address logic.
define i64 @f5(i64 %a, i64 %b, float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r4, -4
; CHECK: ceb %f0, 0(%r4)
; CHECK-NEXT: je
; Check that CEB allows indices.
define i64 @f6(i64 %a, i64 %b, float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r5, 2
; CHECK: ceb %f0, 400(%r1,%r4)
; CHECK-NEXT: je
; Check that comparisons of spilled values can use CEB rather than CEBR.
define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: ceb {{%f[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check comparison with registers.
define i64 @f1(i64 %a, i64 %b, double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cdbr %f0, %f2
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; Check the low end of the CDB range.
define i64 @f2(i64 %a, i64 %b, double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cdb %f0, 0(%r4)
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; Check the high end of the aligned CDB range.
define i64 @f3(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cdb %f0, 4088(%r4)
; CHECK-NEXT: je
; CHECK: lgr %r2, %r3
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r4, 4096
; CHECK: cdb %f0, 0(%r4)
; CHECK-NEXT: je
; Check negative displacements, which also need separate address logic.
define i64 @f5(i64 %a, i64 %b, double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r4, -8
; CHECK: cdb %f0, 0(%r4)
; CHECK-NEXT: je
; Check that CDB allows indices.
define i64 @f6(i64 %a, i64 %b, double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r5, 3
; CHECK: cdb %f0, 800(%r1,%r4)
; CHECK-NEXT: je
; Check that comparisons of spilled values can use CDB rather than CDBR.
define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: cdb {{%f[0-9]+}}, 160(%r15)
; CHECK: br %r14
; There is no memory form of 128-bit comparison.
define i64 @f1(i64 %a, i64 %b, fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r4)
; CHECK: ld %f3, 8(%r4)
; Test f32.
define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lzer %f0
; CHECK: br %r14
ret float 0.0
; Test f64.
define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lzdr %f0
; CHECK: br %r14
ret double 0.0
; Test f128.
define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lzxr %f0
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Test f32.
define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lzer [[REGISTER:%f[0-5]+]]
; CHECK: lcebr %f0, [[REGISTER]]
; CHECK: br %r14
; Test f64.
define double @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lzdr [[REGISTER:%f[0-5]+]]
; CHECK: lcdbr %f0, [[REGISTER]]
; CHECK: br %r14
; Test f128.
define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lzxr [[REGISTER:%f[0-5]+]]
; CHECK: lcxbr %f0, [[REGISTER]]
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
define float @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
; CHECK: le %f0, 0([[REGISTER]])
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
define double @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: larl [[REGISTER:%r[1-5]]], {{.*}}
; CHECK: ldeb %f0, 0([[REGISTER]])
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
; CHECK: lxeb %f0, 0([[REGISTER]])
; CHECK: std %f0, 0(%r2)
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
define double @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
; CHECK: ld %f0, 0([[REGISTER]])
; CHECK: br %r14
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
; CHECK: lxdb %f0, 0([[REGISTER]])
; CHECK: std %f0, 0(%r2)
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
; CHECK: ld %f0, 0([[REGISTER]])
; CHECK: ld %f2, 8([[REGISTER]])
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CONST
define void @f1(fp128 *%x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: larl [[REGISTER:%r[1-5]+]], {{.*}}
; CHECK: ld %f0, 0([[REGISTER]])
; CHECK: ld %f2, 8([[REGISTER]])
; Test f64->f32.
define float @f1(double %d1, double %d2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ledbr %f0, %f2
; CHECK: br %r14
%res = fptrunc double %d2 to float
; Test f128->f32.
define float @f2(fp128 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lexbr %f0, %f0
; CHECK: br %r14
%val = load fp128 *%ptr
; Make sure that we don't use %f0 as the destination of LEXBR when %f2
; is still live.
define void @f3(float *%dst, fp128 *%ptr, float %d1, float %d2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lexbr %f1, %f1
; CHECK: aebr %f1, %f2
; CHECK: ste %f1, 0(%r2)
; Test f128->f64.
define double @f4(fp128 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ldxbr %f0, %f0
; CHECK: br %r14
%val = load fp128 *%ptr
; Like f3, but for f128->f64.
define void @f5(double *%dst, fp128 *%ptr, double %d1, double %d2) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldxbr %f1, %f1
; CHECK: adbr %f1, %f2
; CHECK: std %f1, 0(%r2)
; Check register extension.
define double @f1(float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldebr %f0, %f0
; CHECK: br %r14
%res = fpext float %val to double
; Check the low end of the LDEB range.
define double @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldeb %f0, 0(%r2)
; CHECK: br %r14
%val = load float *%ptr
; Check the high end of the aligned LDEB range.
define double @f3(float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ldeb %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%base, i64 1023
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: ldeb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define double @f5(float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: ldeb %f0, 0(%r2)
; CHECK: br %r14
; Check that LDEB allows indices.
define double @f6(float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: ldeb %f0, 400(%r1,%r2)
; CHECK: br %r14
; Test a case where we spill the source of at least one LDEBR. We want
; to use LDEB if possible.
define void @f7(double *%ptr1, float *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ldeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
%val0 = load volatile float *%ptr2
; Check register extension.
define void @f1(fp128 *%dst, float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Check the low end of the LXEB range.
define void @f2(fp128 *%dst, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lxeb %f0, 0(%r3)
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Check the high end of the aligned LXEB range.
define void @f3(fp128 *%dst, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lxeb %f0, 4092(%r3)
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f4(fp128 *%dst, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r3, 4096
; CHECK: lxeb %f0, 0(%r3)
; CHECK: std %f0, 0(%r2)
; Check negative displacements, which also need separate address logic.
define void @f5(fp128 *%dst, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r3, -4
; CHECK: lxeb %f0, 0(%r3)
; CHECK: std %f0, 0(%r2)
; Check that LXEB allows indices.
define void @f6(fp128 *%dst, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r4, 2
; CHECK: lxeb %f0, 400(%r1,%r3)
; CHECK: std %f0, 0(%r2)
; Test a case where we spill the source of at least one LXEBR. We want
; to use LXEB if possible.
define void @f7(fp128 *%ptr1, float *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lxeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
%val0 = load volatile float *%ptr2
; Check register extension.
define void @f1(fp128 *%dst, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lxdbr %f0, %f0
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Check the low end of the LXDB range.
define void @f2(fp128 *%dst, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lxdb %f0, 0(%r3)
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Check the high end of the aligned LXDB range.
define void @f3(fp128 *%dst, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lxdb %f0, 4088(%r3)
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f4(fp128 *%dst, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r3, 4096
; CHECK: lxdb %f0, 0(%r3)
; CHECK: std %f0, 0(%r2)
; Check negative displacements, which also need separate address logic.
define void @f5(fp128 *%dst, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r3, -8
; CHECK: lxdb %f0, 0(%r3)
; CHECK: std %f0, 0(%r2)
; Check that LXDB allows indices.
define void @f6(fp128 *%dst, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r4, 3
; CHECK: lxdb %f0, 800(%r1,%r3)
; CHECK: std %f0, 0(%r2)
; Test a case where we spill the source of at least one LXDBR. We want
; to use LXDB if possible.
define void @f7(fp128 *%ptr1, double *%ptr2) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lxdb {{%f[0-9]+}}, 160(%r15)
; CHECK: br %r14
%val0 = load volatile double *%ptr2
; Check i32->f32.
define float @f1(i32 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cefbr %f0, %r2
; CHECK: br %r14
%conv = sitofp i32 %i to float
; Check i32->f64.
define double @f2(i32 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cdfbr %f0, %r2
; CHECK: br %r14
%conv = sitofp i32 %i to double
; Check i32->f128.
define void @f3(i32 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cxfbr %f0, %r2
; CHECK: std %f0, 0(%r3)
; CHECK: std %f2, 8(%r3)
; Check i32->f32. There is no native instruction, so we must promote
; to i64 first.
define float @f1(i32 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
; CHECK: cegbr %f0, [[REGISTER]]
; CHECK: br %r14
; Check i32->f64.
define double @f2(i32 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
; CHECK: cdgbr %f0, [[REGISTER]]
; CHECK: br %r14
; Check i32->f128.
define void @f3(i32 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llgfr [[REGISTER:%r[0-5]]], %r2
; CHECK: cxgbr %f0, [[REGISTER]]
; CHECK: std %f0, 0(%r3)
; Test i64->f32.
define float @f1(i64 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cegbr %f0, %r2
; CHECK: br %r14
%conv = sitofp i64 %i to float
; Test i64->f64.
define double @f2(i64 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cdgbr %f0, %r2
; CHECK: br %r14
%conv = sitofp i64 %i to double
; Test i64->f128.
define void @f3(i64 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cxgbr %f0, %r2
; CHECK: std %f0, 0(%r3)
; CHECK: std %f2, 8(%r3)
; Test i64->f32. There's no native support for unsigned i64-to-fp conversions,
; but we should be able to implement them using signed i64-to-fp conversions.
define float @f1(i64 %i) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cegbr
; CHECK: aebr
; CHECK: br %r14
; Test i64->f64.
define double @f2(i64 %i) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldgr
; CHECK: adbr
; CHECK: br %r14
; Test i64->f128.
define void @f3(i64 %i, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cxgbr
; CHECK: axbr
; CHECK: br %r14
; Test f32->i32.
define i32 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cfebr %r2, 5, %f0
; CHECK: br %r14
%conv = fptosi float %f to i32
; Test f64->i32.
define i32 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cfdbr %r2, 5, %f0
; CHECK: br %r14
%conv = fptosi double %f to i32
; Test f128->i32.
define i32 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ld %f0, 0(%r2)
; CHECK: ld %f2, 8(%r2)
; CHECK: cfxbr %r2, 5, %f0
; Test f32->i32.
define i32 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cebr
; CHECK: sebr
; CHECK: cfebr
; Test f64->i32.
define i32 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cdbr
; CHECK: sdbr
; CHECK: cfdbr
; Test f128->i32.
define i32 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cxbr
; CHECK: sxbr
; CHECK: cfxbr
; Test f32->i64.
define i64 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgebr %r2, 5, %f0
; CHECK: br %r14
%conv = fptosi float %f to i64
; Test f64->i64.
define i64 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cgdbr %r2, 5, %f0
; CHECK: br %r14
%conv = fptosi double %f to i64
; Test f128->i64.
define i64 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ld %f0, 0(%r2)
; CHECK: ld %f2, 8(%r2)
; CHECK: cgxbr %r2, 5, %f0
; Test f32->i64.
define i64 @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cebr
; CHECK: sebr
; CHECK: cgebr
; Test f64->i64.
define i64 @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cdbr
; CHECK: sdbr
; CHECK: cgdbr
; Test f128->i64.
define i64 @f3(fp128 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cxbr
; CHECK: sxbr
; CHECK: cgxbr
; Test f32 copies in which the sign comes from an f32.
define float @f1(float %a, float %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %f2
; CHECK: cpsdr %f0, %f0, %f2
; CHECK: br %r14
; Test f32 copies in which the sign comes from an f64.
define float @f2(float %a, double %bd) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %f2
; CHECK: cpsdr %f0, %f0, %f2
; CHECK: br %r14
; Test f32 copies in which the sign comes from an f128.
define float @f3(float %a, fp128 *%bptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2)
; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
; CHECK: cpsdr %f0, %f0, [[BHIGH]]
; Test f64 copies in which the sign comes from an f32.
define double @f4(double %a, float %bf) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %f2
; CHECK: cpsdr %f0, %f0, %f2
; CHECK: br %r14
; Test f64 copies in which the sign comes from an f64.
define double @f5(double %a, double %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %f2
; CHECK: cpsdr %f0, %f0, %f2
; CHECK: br %r14
; Test f64 copies in which the sign comes from an f128.
define double @f6(double %a, fp128 *%bptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r2)
; CHECK: ld [[BLOW:%f[0-7]]], 8(%r2)
; CHECK: cpsdr %f0, %f0, [[BHIGH]]
; need any register shuffling here; %a should be tied to %c, with CPSDR
; just changing the high register.
define void @f7(fp128 *%cptr, fp128 *%aptr, float %bf) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0
; As above, but the sign comes from an f64.
define void @f8(fp128 *%cptr, fp128 *%aptr, double %bd) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
; CHECK: cpsdr [[AHIGH]], [[AHIGH]], %f0
; As above, but the sign comes from an f128. Don't require the low part
; of %b to be loaded, since it isn't used.
define void @f9(fp128 *%cptr, fp128 *%aptr, fp128 *%bptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ld [[AHIGH:%f[0-7]]], 0(%r3)
; CHECK: ld [[ALOW:%f[0-7]]], 8(%r3)
; CHECK: ld [[BHIGH:%f[0-7]]], 0(%r4)
; Check register division.
define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: debr %f0, %f2
; CHECK: br %r14
%res = fdiv float %f1, %f2
; Check the low end of the DEB range.
define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: deb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load float *%ptr
; Check the high end of the aligned DEB range.
define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: deb %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%base, i64 1023
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: deb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: deb %f0, 0(%r2)
; CHECK: br %r14
; Check that DEB allows indices.
define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: deb %f0, 400(%r1,%r2)
; CHECK: br %r14
; Check that divisions of spilled values can use DEB rather than DEBR.
define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: deb %f0, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check register division.
define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ddbr %f0, %f2
; CHECK: br %r14
%res = fdiv double %f1, %f2
; Check the low end of the DDB range.
define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ddb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load double *%ptr
; Check the high end of the aligned DDB range.
define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ddb %f0, 4088(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%base, i64 511
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: ddb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -8
; CHECK: ddb %f0, 0(%r2)
; CHECK: br %r14
; Check that DDB allows indices.
define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 3
; CHECK: ddb %f0, 800(%r1,%r2)
; CHECK: br %r14
; Check that divisions of spilled values can use DDB rather than DDBR.
define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: ddb %f0, 160(%r15)
; CHECK: br %r14
; There is no memory form of 128-bit division.
define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r2)
; CHECK: ld %f3, 8(%r2)
; Test f32 moves.
define float @f1(float %a, float %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ler %f0, %f2
ret float %b
}
; Test f64 moves.
define double @f2(double %a, double %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldr %f0, %f2
ret double %b
}
; Test f128 moves. Since f128s are passed by reference, we need to force
; a copy by other means.
define void @f3(fp128 *%x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lxr
; CHECK: axbr
%val = load volatile fp128 *%x
; Test 32-bit moves from GPRs to FPRs. The GPR must be moved into the high
; 32 bits of the FPR.
define float @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sllg [[REGISTER:%r[0-5]]], %r2, 32
; CHECK: ldgr %f0, [[REGISTER]]
%res = bitcast i32 %a to float
; Like f1, but create a situation where the shift can be folded with
; surrounding code.
define float @f2(i64 %big) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 31
; CHECK: ldgr %f0, [[REGISTER]]
%shift = lshr i64 %big, 1
; Another example of the same thing.
define float @f3(i64 %big) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: risbg [[REGISTER:%r[0-5]]], %r2, 0, 159, 2
; CHECK: ldgr %f0, [[REGISTER]]
%shift = ashr i64 %big, 30
; Like f1, but the value to transfer is already in the high 32 bits.
define float @f4(i64 %big) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r2
; CHECK: risbg [[REG:%r[0-5]]], %r2, 0, 159, 0
; CHECK-NOT: [[REG]]
; Test 64-bit moves from GPRs to FPRs.
define double @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldgr %f0, %r2
%res = bitcast i64 %a to double
ret double %res
; so this goes through memory.
; FIXME: it would be better to use one MVC here.
define void @f6(fp128 *%a, i128 *%b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lg
; CHECK: mvc
; CHECK: stg
; Test 32-bit moves from FPRs to GPRs. The high 32 bits of the FPR should
; be moved into the low 32 bits of the GPR.
define i32 @f7(float %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgdr [[REGISTER:%r[0-5]]], %f0
; CHECK: srlg %r2, [[REGISTER]], 32
%res = bitcast float %a to i32
; Test 64-bit moves from FPRs to GPRs.
define i64 @f8(double %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lgdr %r2, %f0
%res = bitcast double %a to i64
ret i64 %res
; Test 128-bit moves from FPRs to GPRs, with the same restriction as f6.
define void @f9(fp128 *%a, i128 *%b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ld
; CHECK: ld
; CHECK: std
; Test cases where the destination of an LGDR needs to be spilled.
; We shouldn't have any integer stack stores or floating-point loads.
define void @f10(double %extra) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: dptr
; CHECK-NOT: stg {{.*}}(%r15)
; CHECK: %loop
; ...likewise LDGR, with the requirements the other way around.
define void @f11(i64 %mask) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: iptr
; CHECK-NOT: std {{.*}}(%r15)
; CHECK: %loop
; Test cases where the source of an LDGR needs to be spilled.
; We shouldn't have any integer stack stores or floating-point loads.
define void @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: %loop
; CHECK-NOT: std {{.*}}(%r15)
; CHECK: %exit
; ...likewise LGDR, with the requirements the other way around.
define void @f13() {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: %loop
; CHECK-NOT: stg {{.*}}(%r15)
; CHECK: %exit
; Test the low end of the LE range.
define float @f1(float *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: le %f0, 0(%r2)
; CHECK: br %r14
%val = load float *%src
; Test the high end of the LE range.
define float @f2(float *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: le %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 1023
; Check the next word up, which should use LEY instead of LE.
define float @f3(float *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ley %f0, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 1024
; Check the high end of the aligned LEY range.
define float @f4(float *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ley %f0, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define float @f5(float *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: le %f0, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned LEY range.
define float @f6(float *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ley %f0, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 -1
; Check the low end of the LEY range.
define float @f7(float *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ley %f0, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define float @f8(float *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524292
; CHECK: le %f0, 0(%r2)
; CHECK: br %r14
; Check that LE allows an index.
define float @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: le %f0, 4092({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that LEY allows an index.
define float @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ley %f0, 4096({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test the low end of the LD range.
define double @f1(double *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ld %f0, 0(%r2)
; CHECK: br %r14
%val = load double *%src
; Test the high end of the LD range.
define double @f2(double *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ld %f0, 4088(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 511
; Check the next doubleword up, which should use LDY instead of LD.
define double @f3(double *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ldy %f0, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 512
; Check the high end of the aligned LDY range.
define double @f4(double *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ldy %f0, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f5(double *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: ld %f0, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned LDY range.
define double @f6(double *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ldy %f0, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 -1
; Check the low end of the LDY range.
define double @f7(double *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ldy %f0, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f8(double *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524296
; CHECK: ld %f0, 0(%r2)
; CHECK: br %r14
; Check that LD allows an index.
define double @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ld %f0, 4095({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that LDY allows an index.
define double @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ldy %f0, 4096({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check loads with no offset.
define double @f1(i64 %src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ld %f0, 0(%r2)
; CHECK: ld %f2, 8(%r2)
; CHECK: br %r14
; Check the highest aligned offset that allows LD for both halves.
define double @f2(i64 %src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ld %f0, 4080(%r2)
; CHECK: ld %f2, 4088(%r2)
; CHECK: br %r14
; Check the next doubleword up, which requires a mixture of LD and LDY.
define double @f3(i64 %src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ld %f0, 4088(%r2)
; CHECK: ldy %f2, 4096(%r2)
; CHECK: br %r14
; Check the next doubleword after that, which requires LDY for both halves.
define double @f4(i64 %src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ldy %f0, 4096(%r2)
; CHECK: ldy %f2, 4104(%r2)
; CHECK: br %r14
; Check the highest aligned offset that allows LDY for both halves.
define double @f5(i64 %src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldy %f0, 524272(%r2)
; CHECK: ldy %f2, 524280(%r2)
; CHECK: br %r14
; Check the next doubleword up, which requires separate address logic.
; Other sequences besides this one would be OK.
define double @f6(i64 %src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lay %r1, 524280(%r2)
; CHECK: ld %f0, 0(%r1)
; CHECK: ld %f2, 8(%r1)
; Check the highest aligned negative offset, which needs a combination of
; LDY and LD.
define double @f7(i64 %src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ldy %f0, -8(%r2)
; CHECK: ld %f2, 0(%r2)
; CHECK: br %r14
; Check the next doubleword down, which requires LDY for both halves.
define double @f8(i64 %src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ldy %f0, -16(%r2)
; CHECK: ldy %f2, -8(%r2)
; CHECK: br %r14
; Check the lowest offset that allows LDY for both halves.
define double @f9(i64 %src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ldy %f0, -524288(%r2)
; CHECK: ldy %f2, -524280(%r2)
; CHECK: br %r14
; Check the next doubleword down, which requires separate address logic.
; Other sequences besides this one would be OK.
define double @f10(i64 %src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r2, -524296
; CHECK: ld %f0, 0(%r2)
; CHECK: ld %f2, 8(%r2)
; Check that indices are allowed.
define double @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: ld %f0, 4088({{%r2,%r3|%r3,%r2}})
; CHECK: ldy %f2, 4096({{%r2,%r3|%r3,%r2}})
; CHECK: br %r14
; Test the low end of the STE range.
define void @f1(float *%ptr, float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ste %f0, 0(%r2)
; CHECK: br %r14
store float %val, float *%ptr
; Test the high end of the STE range.
define void @f2(float *%src, float %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ste %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 1023
; Check the next word up, which should use STEY instead of STE.
define void @f3(float *%src, float %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: stey %f0, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 1024
; Check the high end of the aligned STEY range.
define void @f4(float *%src, float %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: stey %f0, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f5(float *%src, float %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: ste %f0, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned STEY range.
define void @f6(float *%src, float %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: stey %f0, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 -1
; Check the low end of the STEY range.
define void @f7(float *%src, float %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: stey %f0, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(float *%src, float %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524292
; CHECK: ste %f0, 0(%r2)
; CHECK: br %r14
; Check that STE allows an index.
define void @f9(i64 %src, i64 %index, float %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ste %f0, 4092({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that STEY allows an index.
define void @f10(i64 %src, i64 %index, float %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: stey %f0, 4096({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test the low end of the STD range.
define void @f1(double *%src, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: std %f0, 0(%r2)
; CHECK: br %r14
store double %val, double *%src
; Test the high end of the STD range.
define void @f2(double *%src, double %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: std %f0, 4088(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 511
; Check the next doubleword up, which should use STDY instead of STD.
define void @f3(double *%src, double %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: stdy %f0, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 512
; Check the high end of the aligned STDY range.
define void @f4(double *%src, double %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: stdy %f0, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f5(double *%src, double %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: std %f0, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned STDY range.
define void @f6(double *%src, double %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: stdy %f0, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 -1
; Check the low end of the STDY range.
define void @f7(double *%src, double %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: stdy %f0, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(double *%src, double %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524296
; CHECK: std %f0, 0(%r2)
; CHECK: br %r14
; Check that STD allows an index.
define void @f9(i64 %src, i64 %index, double %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: std %f0, 4095({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that STDY allows an index.
define void @f10(i64 %src, i64 %index, double %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: stdy %f0, 4096({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check stores with no offset.
define void @f1(i64 %src, double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; CHECK: br %r14
; Check the highest aligned offset that allows STD for both halves.
define void @f2(i64 %src, double %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: std %f0, 4080(%r2)
; CHECK: std %f2, 4088(%r2)
; CHECK: br %r14
; Check the next doubleword up, which requires a mixture of STD and STDY.
define void @f3(i64 %src, double %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: std %f0, 4088(%r2)
; CHECK: stdy %f2, 4096(%r2)
; CHECK: br %r14
; Check the next doubleword after that, which requires STDY for both halves.
define void @f4(i64 %src, double %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: stdy %f0, 4096(%r2)
; CHECK: stdy %f2, 4104(%r2)
; CHECK: br %r14
; Check the highest aligned offset that allows STDY for both halves.
define void @f5(i64 %src, double %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: stdy %f0, 524272(%r2)
; CHECK: stdy %f2, 524280(%r2)
; CHECK: br %r14
; Check the next doubleword up, which requires separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i64 %src, double %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lay %r1, 524280(%r2)
; CHECK: std %f0, 0(%r1)
; CHECK: std %f2, 8(%r1)
; Check the highest aligned negative offset, which needs a combination of
; STDY and STD.
define void @f7(i64 %src, double %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: stdy %f0, -8(%r2)
; CHECK: std %f2, 0(%r2)
; CHECK: br %r14
; Check the next doubleword down, which requires STDY for both halves.
define void @f8(i64 %src, double %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: stdy %f0, -16(%r2)
; CHECK: stdy %f2, -8(%r2)
; CHECK: br %r14
; Check the lowest offset that allows STDY for both halves.
define void @f9(i64 %src, double %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: stdy %f0, -524288(%r2)
; CHECK: stdy %f2, -524280(%r2)
; CHECK: br %r14
; Check the next doubleword down, which requires separate address logic.
; Other sequences besides this one would be OK.
define void @f10(i64 %src, double %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r2, -524296
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Check that indices are allowed.
define void @f11(i64 %src, i64 %index, double %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: std %f0, 4088({{%r2,%r3|%r3,%r2}})
; CHECK: stdy %f2, 4096({{%r2,%r3|%r3,%r2}})
; CHECK: br %r14
; Check register multiplication.
define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: meebr %f0, %f2
; CHECK: br %r14
%res = fmul float %f1, %f2
; Check the low end of the MEEB range.
define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: meeb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load float *%ptr
; Check the high end of the aligned MEEB range.
define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: meeb %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%base, i64 1023
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: meeb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: meeb %f0, 0(%r2)
; CHECK: br %r14
; Check that MEEB allows indices.
define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: meeb %f0, 400(%r1,%r2)
; CHECK: br %r14
; Check that multiplications of spilled values can use MEEB rather than MEEBR.
define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: meeb %f0, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check register multiplication.
define double @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mdebr %f0, %f2
; CHECK: br %r14
%f1x = fpext float %f1 to double
; Check the low end of the MDEB range.
define double @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mdeb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load float *%ptr
; Check the high end of the aligned MDEB range.
define double @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mdeb %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%base, i64 1023
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: mdeb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define double @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: mdeb %f0, 0(%r2)
; CHECK: br %r14
; Check that MDEB allows indices.
define double @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: mdeb %f0, 400(%r1,%r2)
; CHECK: br %r14
; Check that multiplications of spilled values can use MDEB rather than MDEBR.
define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: mdeb %f0, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check register multiplication.
define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mdbr %f0, %f2
; CHECK: br %r14
%res = fmul double %f1, %f2
; Check the low end of the MDB range.
define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mdb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load double *%ptr
; Check the high end of the aligned MDB range.
define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mdb %f0, 4088(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%base, i64 511
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: mdb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -8
; CHECK: mdb %f0, 0(%r2)
; CHECK: br %r14
; Check that MDB allows indices.
define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 3
; CHECK: mdb %f0, 800(%r1,%r2)
; CHECK: br %r14
; Check that multiplications of spilled values can use MDB rather than MDBR.
define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: mdb %f0, 160(%r15)
; CHECK: br %r14
; point of view, because %f2 is the low register of the FP128 %f0. Pass the
; multiplier in %f4 instead.
define void @f1(double %f1, double %dummy, double %f2, fp128 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mxdbr %f0, %f4
; CHECK: std %f0, 0(%r2)
; CHECK: std %f2, 8(%r2)
; Check the low end of the MXDB range.
define void @f2(double %f1, double *%ptr, fp128 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mxdb %f0, 0(%r2)
; CHECK: std %f0, 0(%r3)
; CHECK: std %f2, 8(%r3)
; Check the high end of the aligned MXDB range.
define void @f3(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mxdb %f0, 4088(%r2)
; CHECK: std %f0, 0(%r3)
; CHECK: std %f2, 8(%r3)
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f4(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: mxdb %f0, 0(%r2)
; CHECK: std %f0, 0(%r3)
; Check negative displacements, which also need separate address logic.
define void @f5(double %f1, double *%base, fp128 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -8
; CHECK: mxdb %f0, 0(%r2)
; CHECK: std %f0, 0(%r3)
; Check that MXDB allows indices.
define void @f6(double %f1, double *%base, i64 %index, fp128 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 3
; CHECK: mxdb %f0, 800(%r1,%r2)
; CHECK: std %f0, 0(%r4)
; Check that multiplications of spilled values can use MXDB rather than MXDBR.
define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: mxdb %f0, 160(%r15)
; CHECK: br %r14
; There is no memory form of 128-bit multiplication.
define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r2)
; CHECK: ld %f3, 8(%r2)
declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
define float @f1(float %f1, float %f2, float %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: maebr %f4, %f0, %f2
; CHECK: ler %f0, %f4
; CHECK: br %r14
}
define float @f2(float %f1, float *%ptr, float %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: maeb %f2, %f0, 0(%r2)
; CHECK: ler %f0, %f2
; CHECK: br %r14
}
define float @f3(float %f1, float *%base, float %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: maeb %f2, %f0, 4092(%r2)
; CHECK: ler %f0, %f2
; CHECK: br %r14
; The important thing here is that we don't generate an out-of-range
; displacement. Other sequences besides this one would be OK.
;
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: maeb %f2, %f0, 0(%r2)
; CHECK: ler %f0, %f2
; Here too the important thing is that we don't generate an out-of-range
; displacement. Other sequences besides this one would be OK.
;
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: maeb %f2, %f0, 0(%r2)
; CHECK: ler %f0, %f2
}
define float @f6(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: maeb %f2, %f0, 0(%r1,%r2)
; CHECK: ler %f0, %f2
}
define float @f7(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sllg %r1, %r3, 2
; CHECK: maeb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}})
; CHECK: ler %f0, %f2
}
define float @f8(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sllg %r1, %r3, 2
; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
; CHECK: maeb %f2, %f0, 0(%r1)
declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
define double @f1(double %f1, double %f2, double %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: madbr %f4, %f0, %f2
; CHECK: ldr %f0, %f4
; CHECK: br %r14
}
define double @f2(double %f1, double *%ptr, double %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: madb %f2, %f0, 0(%r2)
; CHECK: ldr %f0, %f2
; CHECK: br %r14
}
define double @f3(double %f1, double *%base, double %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: madb %f2, %f0, 4088(%r2)
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; The important thing here is that we don't generate an out-of-range
; displacement. Other sequences besides this one would be OK.
;
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: madb %f2, %f0, 0(%r2)
; CHECK: ldr %f0, %f2
; Here too the important thing is that we don't generate an out-of-range
; displacement. Other sequences besides this one would be OK.
;
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -8
; CHECK: madb %f2, %f0, 0(%r2)
; CHECK: ldr %f0, %f2
}
define double @f6(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 3
; CHECK: madb %f2, %f0, 0(%r1,%r2)
; CHECK: ldr %f0, %f2
}
define double @f7(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sllg %r1, %r3, 3
; CHECK: madb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}})
; CHECK: ldr %f0, %f2
}
define double @f8(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sllg %r1, %r3, 3
; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
; CHECK: madb %f2, %f0, 0(%r1)
declare float @llvm.fma.f32(float %f1, float %f2, float %f3)
define float @f1(float %f1, float %f2, float %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: msebr %f4, %f0, %f2
; CHECK: ler %f0, %f4
; CHECK: br %r14
}
define float @f2(float %f1, float *%ptr, float %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mseb %f2, %f0, 0(%r2)
; CHECK: ler %f0, %f2
; CHECK: br %r14
}
define float @f3(float %f1, float *%base, float %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mseb %f2, %f0, 4092(%r2)
; CHECK: ler %f0, %f2
; CHECK: br %r14
; The important thing here is that we don't generate an out-of-range
; displacement. Other sequences besides this one would be OK.
;
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: mseb %f2, %f0, 0(%r2)
; CHECK: ler %f0, %f2
; Here too the important thing is that we don't generate an out-of-range
; displacement. Other sequences besides this one would be OK.
;
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: mseb %f2, %f0, 0(%r2)
; CHECK: ler %f0, %f2
}
define float @f6(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: mseb %f2, %f0, 0(%r1,%r2)
; CHECK: ler %f0, %f2
}
define float @f7(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sllg %r1, %r3, 2
; CHECK: mseb %f2, %f0, 4092({{%r1,%r2|%r2,%r1}})
; CHECK: ler %f0, %f2
}
define float @f8(float %f1, float *%base, i64 %index, float %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sllg %r1, %r3, 2
; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
; CHECK: mseb %f2, %f0, 0(%r1)
declare double @llvm.fma.f64(double %f1, double %f2, double %f3)
define double @f1(double %f1, double %f2, double %acc) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: msdbr %f4, %f0, %f2
; CHECK: ldr %f0, %f4
; CHECK: br %r14
}
define double @f2(double %f1, double *%ptr, double %acc) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: msdb %f2, %f0, 0(%r2)
; CHECK: ldr %f0, %f2
; CHECK: br %r14
}
define double @f3(double %f1, double *%base, double %acc) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: msdb %f2, %f0, 4088(%r2)
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; The important thing here is that we don't generate an out-of-range
; displacement. Other sequences besides this one would be OK.
;
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: msdb %f2, %f0, 0(%r2)
; CHECK: ldr %f0, %f2
; Here too the important thing is that we don't generate an out-of-range
; displacement. Other sequences besides this one would be OK.
;
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -8
; CHECK: msdb %f2, %f0, 0(%r2)
; CHECK: ldr %f0, %f2
}
define double @f6(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 3
; CHECK: msdb %f2, %f0, 0(%r1,%r2)
; CHECK: ldr %f0, %f2
}
define double @f7(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sllg %r1, %r3, 3
; CHECK: msdb %f2, %f0, 4088({{%r1,%r2|%r2,%r1}})
; CHECK: ldr %f0, %f2
}
define double @f8(double %f1, double *%base, i64 %index, double %acc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sllg %r1, %r3, 3
; CHECK: lay %r1, 4096({{%r1,%r2|%r2,%r1}})
; CHECK: msdb %f2, %f0, 0(%r1)
; Test f32.
define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lcebr %f0, %f0
; CHECK: br %r14
%res = fsub float -0.0, %f
; Test f64.
define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lcdbr %f0, %f0
; CHECK: br %r14
%res = fsub double -0.0, %f
; be better implemented using an XI on the upper byte. Do some extra
; processing so that using FPRs is unequivocally better.
define void @f3(fp128 *%ptr, fp128 *%ptr2) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lcxbr
; CHECK: dxbr
; CHECK: br %r14
; Test f32.
declare float @llvm.rint.f32(float %f)
define float @f1(float %f) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: fiebr %f0, 0, %f0
; CHECK: br %r14
%res = call float @llvm.rint.f32(float %f)
; Test f64.
declare double @llvm.rint.f64(double %f)
define double @f2(double %f) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: fidbr %f0, 0, %f0
; CHECK: br %r14
%res = call double @llvm.rint.f64(double %f)
; Test f128.
declare fp128 @llvm.rint.f128(fp128 %f)
define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: fixbr %f0, 0, %f0
; CHECK: br %r14
%src = load fp128 *%ptr
; Check register square root.
define float @f1(float %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sqebr %f0, %f0
; CHECK: br %r14
%res = call float @llvm.sqrt.f32(float %val)
; Check the low end of the SQEB range.
define float @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sqeb %f0, 0(%r2)
; CHECK: br %r14
%val = load float *%ptr
; Check the high end of the aligned SQEB range.
define float @f3(float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sqeb %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%base, i64 1023
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define float @f4(float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: sqeb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define float @f5(float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: sqeb %f0, 0(%r2)
; CHECK: br %r14
; Check that SQEB allows indices.
define float @f6(float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: sqeb %f0, 400(%r1,%r2)
; CHECK: br %r14
; Test a case where we spill the source of at least one SQEBR. We want
; to use SQEB if possible.
define void @f7(float *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sqeb {{%f[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
%val0 = load volatile float *%ptr
; Check register square root.
define double @f1(double %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sqdbr %f0, %f0
; CHECK: br %r14
%res = call double @llvm.sqrt.f64(double %val)
; Check the low end of the SQDB range.
define double @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sqdb %f0, 0(%r2)
; CHECK: br %r14
%val = load double *%ptr
; Check the high end of the aligned SQDB range.
define double @f3(double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sqdb %f0, 4088(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%base, i64 511
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: sqdb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define double @f5(double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -8
; CHECK: sqdb %f0, 0(%r2)
; CHECK: br %r14
; Check that SQDB allows indices.
define double @f6(double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 3
; CHECK: sqdb %f0, 800(%r1,%r2)
; CHECK: br %r14
; Test a case where we spill the source of at least one SQDBR. We want
; to use SQDB if possible.
define void @f7(double *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sqdb {{%f[0-9]+}}, 160(%r15)
; CHECK: br %r14
%val0 = load volatile double *%ptr
; There's no memory form of SQXBR.
define void @f1(fp128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ld %f0, 0(%r2)
; CHECK: ld %f2, 8(%r2)
; CHECK: sqxbr %f0, %f0
; Check register subtraction.
define float @f1(float %f1, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sebr %f0, %f2
; CHECK: br %r14
%res = fsub float %f1, %f2
; Check the low end of the SEB range.
define float @f2(float %f1, float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: seb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load float *%ptr
; Check the high end of the aligned SEB range.
define float @f3(float %f1, float *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: seb %f0, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr float *%base, i64 1023
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define float @f4(float %f1, float *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: seb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define float @f5(float %f1, float *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -4
; CHECK: seb %f0, 0(%r2)
; CHECK: br %r14
; Check that SEB allows indices.
define float @f6(float %f1, float *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 2
; CHECK: seb %f0, 400(%r1,%r2)
; CHECK: br %r14
; Check that subtractions of spilled values can use SEB rather than SEBR.
define float @f7(float *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: seb %f0, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check register subtraction.
define double @f1(double %f1, double %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sdbr %f0, %f2
; CHECK: br %r14
%res = fsub double %f1, %f2
; Check the low end of the SDB range.
define double @f2(double %f1, double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sdb %f0, 0(%r2)
; CHECK: br %r14
%f2 = load double *%ptr
; Check the high end of the aligned SDB range.
define double @f3(double %f1, double *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sdb %f0, 4088(%r2)
; CHECK: br %r14
%ptr = getelementptr double *%base, i64 511
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(double %f1, double *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: sdb %f0, 0(%r2)
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define double @f5(double %f1, double *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -8
; CHECK: sdb %f0, 0(%r2)
; CHECK: br %r14
; Check that SDB allows indices.
define double @f6(double %f1, double *%base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r1, %r3, 3
; CHECK: sdb %f0, 800(%r1,%r2)
; CHECK: br %r14
; Check that subtractions of spilled values can use SDB rather than SDBR.
define double @f7(double *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: brasl %r14, foo@PLT
; CHECK: sdb %f0, 16{{[04]}}(%r15)
; CHECK: br %r14
; There is no memory form of 128-bit subtraction.
define void @f1(fp128 *%ptr, float %f2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lxebr %f0, %f0
; CHECK: ld %f1, 0(%r2)
; CHECK: ld %f3, 8(%r2)
; The CFA offset is 160 (the caller-allocated part of the frame) + 168.
define void @f1(i64 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: aghi %r15, -168
; CHECK: .cfi_def_cfa_offset 328
; CHECK: stg %r2, 160(%r15)
; 12-bit offsets that end up being out of range. Fill the remaining
; 32760 - 176 bytes by allocating (32760 - 176) / 8 = 4073 doublewords.
define void @f2(i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r15, -32760
; CHECK: .cfi_def_cfa_offset 32920
; CHECK: stg %r2, 176(%r15)
; Allocate one more doubleword. This is the one frame size that we can
; allocate using AGHI but must free using AGFI.
define void @f3(i64 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r15, -32768
; CHECK: .cfi_def_cfa_offset 32928
; CHECK: stg %r2, 176(%r15)
; Allocate another doubleword on top of that. The allocation and free
; must both use AGFI.
define void @f4(i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r15, -32776
; CHECK: .cfi_def_cfa_offset 32936
; CHECK: stg %r2, 176(%r15)
; The largest size that can be both allocated and freed using AGFI.
; At this point the frame is too big to represent properly in the CFI.
define void @f5(i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r15, -2147483640
; CHECK: stg %r2, 176(%r15)
; CHECK: agfi %r15, 2147483640
; The only frame size that can be allocated using a single AGFI but which
; must be freed using two instructions.
define void @f6(i64 %x) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r15, -2147483648
; CHECK: stg %r2, 176(%r15)
; CHECK: agfi %r15, 2147483640
; The smallest frame size that needs two instructions to both allocate
; and free the frame.
define void @f7(i64 %x) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r15, -2147483648
; CHECK: aghi %r15, -8
; CHECK: stg %r2, 176(%r15)
; Make sure that LA can be rematerialized.
define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: la %r2, 164(%r15)
; CHECK: brasl %r14, foo@PLT
; CHECK: la %r2, 164(%r15)
; should be exactly 160 + 8 * 8 = 224. The CFA offset is 160
; (the caller-allocated part of the frame) + 224.
define void @f1(float *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: aghi %r15, -224
; CHECK: .cfi_def_cfa_offset 384
; CHECK: std %f8, 216(%r15)
; Like f1, but requires one fewer FPR. We allocate in numerical order,
; so %f15 is the one that gets dropped.
define void @f2(float *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r15, -216
; CHECK: .cfi_def_cfa_offset 376
; CHECK: std %f8, 208(%r15)
; Like f1, but should require only one call-saved FPR.
define void @f3(float *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r15, -168
; CHECK: .cfi_def_cfa_offset 328
; CHECK: std %f8, 160(%r15)
; This function should use all call-clobbered FPRs but no call-saved ones.
; It shouldn't need to create a frame.
define void @f4(float *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r15
; CHECK-NOT: %f8
; CHECK-NOT: %f9
; should be exactly 160 + 8 * 8 = 224. The CFA offset is 160
; (the caller-allocated part of the frame) + 224.
define void @f1(double *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: aghi %r15, -224
; CHECK: .cfi_def_cfa_offset 384
; CHECK: std %f8, 216(%r15)
; Like f1, but requires one fewer FPR. We allocate in numerical order,
; so %f15 is the one that gets dropped.
define void @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r15, -216
; CHECK: .cfi_def_cfa_offset 376
; CHECK: std %f8, 208(%r15)
; Like f1, but should require only one call-saved FPR.
define void @f3(double *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r15, -168
; CHECK: .cfi_def_cfa_offset 328
; CHECK: std %f8, 160(%r15)
; This function should use all call-clobbered FPRs but no call-saved ones.
; It shouldn't need to create a frame.
define void @f4(double *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r15
; CHECK-NOT: %f8
; CHECK-NOT: %f9
; should be exactly 160 + 8 * 8 = 224. The CFA offset is 160
; (the caller-allocated part of the frame) + 224.
define void @f1(fp128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: aghi %r15, -224
; CHECK: .cfi_def_cfa_offset 384
; CHECK: std %f8, 216(%r15)
; Like f1, but requires one fewer FPR pair. We allocate in numerical order,
; so %f13+%f15 is the pair that gets dropped.
define void @f2(fp128 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r15, -208
; CHECK: .cfi_def_cfa_offset 368
; CHECK: std %f8, 200(%r15)
; Like f1, but requires only one call-saved FPR pair. We allocate in
; numerical order so the pair should be %f8+%f10.
define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r15, -176
; CHECK: .cfi_def_cfa_offset 336
; CHECK: std %f8, 168(%r15)
; This function should use all call-clobbered FPRs but no call-saved ones.
; It shouldn't need to create a frame.
define void @f4(fp128 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r15
; CHECK-NOT: %f8
; CHECK-NOT: %f9
; Use a different address for the final store, so that we can check that
; %r15 isn't referenced again until after that.
define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r6, %r15, 48(%r15)
; CHECK-NOT: %r15
; CHECK: .cfi_offset %r6, -112
; from %r14 down, so that the STMG/LMG sequences aren't any longer than
; they need to be.
define void @f2(i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: stmg %r7, %r15, 56(%r15)
; CHECK-NOT: %r15
; CHECK: .cfi_offset %r7, -104
; Like f1, but only needs one call-saved GPR, which ought to be %r14.
define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK-NOT: %r15
; CHECK: .cfi_offset %r14, -48
; This function should use all call-clobbered GPRs but no call-saved ones.
; It shouldn't need to touch the stack at all.
define void @f4(i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r15
; CHECK-NOT: %r6
; CHECK-NOT: %r7
; Use a different address for the final store, so that we can check that
; %r15 isn't referenced again until after that.
define void @f1(i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r6, %r15, 48(%r15)
; CHECK-NOT: %r15
; CHECK: .cfi_offset %r6, -112
; from %r14 down, so that the STMG/LMG sequences aren't any longer than
; they need to be.
define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: stmg %r7, %r15, 56(%r15)
; CHECK-NOT: %r15
; CHECK: .cfi_offset %r7, -104
; Like f1, but only needs one call-saved GPR, which ought to be %r14.
define void @f3(i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK-NOT: %r15
; CHECK: .cfi_offset %r14, -48
; This function should use all call-clobbered GPRs but no call-saved ones.
; It shouldn't need to touch the stack at all.
define void @f4(i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r15
; CHECK-NOT: %r6
; CHECK-NOT: %r7
; as well as the 8 FPR save slots. Get a frame of size 4128 by allocating
; (4128 - 176 - 8 * 8) / 8 = 486 extra doublewords.
define void @f1(double *%ptr, i64 %x) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
; CHECK-NOFP: aghi %r15, -4128
; CHECK-NOFP: .cfi_def_cfa_offset 4288
; CHECK-NOFP: stdy %f8, 4120(%r15)
; CHECK-NOFP: aghi %r15, 4128
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
; CHECK-FP: stmg %r11, %r15, 88(%r15)
; CHECK-FP: aghi %r15, -4128
; CHECK-FP: .cfi_def_cfa_offset 4288
; As above, get a frame of size 524320 by allocating
; (524320 - 176 - 8 * 8) / 8 = 65510 extra doublewords.
define void @f2(double *%ptr, i64 %x) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
; CHECK-NOFP: agfi %r15, -524320
; CHECK-NOFP: .cfi_def_cfa_offset 524480
; CHECK-NOFP: llilh [[INDEX:%r[1-5]]], 8
; CHECK-NOFP: agfi %r15, 524320
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
; CHECK-FP: stmg %r11, %r15, 88(%r15)
; CHECK-FP: agfi %r15, -524320
; CHECK-FP: .cfi_def_cfa_offset 524480
; so get a frame of size 524232 by allocating (524232 - 176) / 8 = 65507
; extra doublewords.
define void @f1(i32 *%ptr, i64 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r6, %r15, 48(%r15)
; CHECK: .cfi_offset %r6, -112
; CHECK: .cfi_offset %r7, -104
; so get a frame of size 524168 by allocating (524168 - 176) / 8 = 65499
; extra doublewords.
define void @f2(i32 *%ptr, i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK: .cfi_offset %r14, -48
; CHECK: .cfi_offset %r15, -40
; frame size that needs two instructions to perform the final LMG for
; %r6 and above.
define void @f3(i32 *%ptr, i64 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: stmg %r6, %r15, 48(%r15)
; CHECK: .cfi_offset %r6, -112
; CHECK: .cfi_offset %r7, -104
; frame size that needs two instructions to perform the final LMG for
; %r14 and %r15.
define void @f4(i32 *%ptr, i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK: .cfi_offset %r14, -48
; CHECK: .cfi_offset %r15, -40
; This is the largest frame size for which the prepatory increment for
; "lmg %r14, %r15, ..." can be done using AGHI.
define void @f5(i32 *%ptr, i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK: .cfi_offset %r14, -48
; CHECK: .cfi_offset %r15, -40
; This is the smallest frame size for which the prepatory increment for
; "lmg %r14, %r15, ..." needs to be done using AGFI.
define void @f6(i32 *%ptr, i64 %x) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: stmg %r14, %r15, 112(%r15)
; CHECK: .cfi_offset %r14, -48
; CHECK: .cfi_offset %r15, -40
; We don't need to allocate any more than the caller-provided 160-byte
; area though.
define i32 @f1(i32 %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r11, %r15, 88(%r15)
; CHECK: .cfi_offset %r11, -72
; CHECK: .cfi_offset %r15, -40
; Make sure that frame accesses after the initial allocation are relative
; to %r11 rather than %r15.
define void @f2(i64 %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: stmg %r11, %r15, 88(%r15)
; CHECK: .cfi_offset %r11, -72
; CHECK: .cfi_offset %r15, -40
; This function should require all GPRs but no other spill slots.
; It shouldn't need to allocate its own frame.
define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: stmg %r6, %r15, 48(%r15)
; CHECK-NOT: %r15
; CHECK-NOT: %r11
; emergency spill slots at 160(%r11), so create a frame of size 524192
; by allocating (524192 - 176) / 8 = 65502 doublewords.
define void @f4(i64 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: stmg %r11, %r15, 88(%r15)
; CHECK: .cfi_offset %r11, -72
; CHECK: .cfi_offset %r15, -40
; The next frame size larger than f4.
define void @f5(i64 %x) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: stmg %r11, %r15, 88(%r15)
; CHECK: .cfi_offset %r11, -72
; CHECK: .cfi_offset %r15, -40
declare i8 *@llvm.stacksave()
define void @f1(i8 **%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stg %r15, 0(%r2)
; CHECK: br %r14
%addr = call i8 *@llvm.stacksave()
; we should use a frame pointer and tear down the frame based on %r11
; rather than %r15.
define void @f1(i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r11, %r15, 88(%r15)
; CHECK: lgr %r11, %r15
; CHECK: lgr %r15, %r2
; in order to put another object at offset 4088 is (4088 - 176) / 4 = 978
; words.
define void @f1() {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
; CHECK-NOFP: mvhi 4092(%r15), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
; CHECK-FP: mvhi 4092(%r11), 42
; CHECK-FP: br %r14
%region1 = alloca [978 x i32], align 8
; Test the first out-of-range offset. We cannot use an index register here.
define void @f2() {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
; CHECK-NOFP: lay %r1, 4096(%r15)
; CHECK-NOFP: mvhi 0(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
; CHECK-FP: lay %r1, 4096(%r11)
; CHECK-FP: mvhi 0(%r1), 42
; CHECK-FP: br %r14
; Test the next offset after that.
define void @f3() {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
; CHECK-NOFP: lay %r1, 4096(%r15)
; CHECK-NOFP: mvhi 4(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
; CHECK-FP: lay %r1, 4096(%r11)
; CHECK-FP: mvhi 4(%r1), 42
; CHECK-FP: br %r14
; Add 4096 bytes (1024 words) to the size of each object and repeat.
define void @f4() {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
; CHECK-NOFP: lay %r1, 4096(%r15)
; CHECK-NOFP: mvhi 4092(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
; CHECK-FP: lay %r1, 4096(%r11)
; CHECK-FP: mvhi 4092(%r1), 42
; CHECK-FP: br %r14
; ...as above.
define void @f5() {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
; CHECK-NOFP: lay %r1, 8192(%r15)
; CHECK-NOFP: mvhi 0(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
; CHECK-FP: lay %r1, 8192(%r11)
; CHECK-FP: mvhi 0(%r1), 42
; CHECK-FP: br %r14
; ...as above.
define void @f6() {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
; CHECK-NOFP: lay %r1, 8192(%r15)
; CHECK-NOFP: mvhi 4(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
; CHECK-FP: lay %r1, 8192(%r11)
; CHECK-FP: mvhi 4(%r1), 42
; CHECK-FP: br %r14
; being at offset 8192. This time we need objects of (8192 - 176) / 4 = 2004
; words.
define void @f7() {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
; CHECK-NOFP: lay %r1, 8192(%r15)
; CHECK-NOFP: mvhi 4092(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
; CHECK-FP: lay %r1, 8192(%r11)
; CHECK-FP: mvhi 4092(%r1), 42
; CHECK-FP: br %r14
; Keep the object-relative offset the same but bump the size of the
; objects by one doubleword.
define void @f8() {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
; CHECK-NOFP: lay %r1, 12288(%r15)
; CHECK-NOFP: mvhi 4(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
; CHECK-FP: lay %r1, 12288(%r11)
; CHECK-FP: mvhi 4(%r1), 42
; CHECK-FP: br %r14
; should force an LAY from the outset. We don't yet do any kind of anchor
; optimization, so there should be no offset on the MVHI itself.
define void @f9() {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
; CHECK-NOFP: lay %r1, 12296(%r15)
; CHECK-NOFP: mvhi 0(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
; CHECK-FP: lay %r1, 12296(%r11)
; CHECK-FP: mvhi 0(%r1), 42
; CHECK-FP: br %r14
; call-clobbered registers are live and no call-saved ones have been
; allocated).
define void @f10(i32 *%vptr) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
; CHECK-NOFP: mvhi 0([[REGISTER]]), 42
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: lay [[REGISTER]], 4096(%r11)
; CHECK-FP: mvhi 0([[REGISTER]]), 42
; However, the FP case uses %r11 as the frame pointer and must therefore
; spill a second register. This leads to an extra displacement of 8.
define void @f11(i32 *%vptr) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
; CHECK-NOFP: stmg %r6, %r15,
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: lay [[REGISTER]], 4096(%r15)
; CHECK-NOFP: lmg %r6, %r15,
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
; CHECK-FP: stmg %r6, %r15,
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: lay [[REGISTER]], 4096(%r11)
; emergency spill slots at 160(%r15), the amount that we need to allocate
; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
define void @f1() {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
; CHECK-NOFP: mvi 4095(%r15), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
; CHECK-FP: mvi 4095(%r11), 42
; CHECK-FP: br %r14
%region1 = alloca [3912 x i8], align 8
; Test the first offset that is out-of-range of the 12-bit form.
define void @f2() {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
; CHECK-NOFP: mviy 4096(%r15), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
; CHECK-FP: mviy 4096(%r11), 42
; CHECK-FP: br %r14
%region1 = alloca [3912 x i8], align 8
; The last in-range doubleword offset is 524280, so by the same reasoning
; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
define void @f3() {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
; CHECK-NOFP: mviy 524287(%r15), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
; CHECK-FP: mviy 524287(%r11), 42
; CHECK-FP: br %r14
%region1 = alloca [524104 x i8], align 8
; and the offset is also out of LAY's range, so expect a constant load
; followed by an addition.
define void @f4() {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: agr %r1, %r15
; CHECK-NOFP: mvi 0(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: agr %r1, %r11
; CHECK-FP: mvi 0(%r1), 42
; Add 4095 to the previous offset, to test the other end of the MVI range.
; The instruction will actually be STCY before frame lowering.
define void @f5() {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: agr %r1, %r15
; CHECK-NOFP: mvi 4095(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: agr %r1, %r11
; CHECK-FP: mvi 4095(%r1), 42
; Test the next offset after that, which uses MVIY instead of MVI.
define void @f6() {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: agr %r1, %r15
; CHECK-NOFP: mviy 4096(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: agr %r1, %r11
; CHECK-FP: mviy 4096(%r1), 42
; anchors 0x10000 bytes apart, so that the high part can be loaded using
; LLILH while still using MVI in more cases than 0x40000 anchors would.
define void @f7() {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
; CHECK-NOFP: llilh %r1, 23
; CHECK-NOFP: agr %r1, %r15
; CHECK-NOFP: mviy 65535(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
; CHECK-FP: llilh %r1, 23
; CHECK-FP: agr %r1, %r11
; CHECK-FP: mviy 65535(%r1), 42
; Keep the object-relative offset the same but bump the size of the
; objects by one doubleword.
define void @f8() {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
; CHECK-NOFP: llilh %r1, 24
; CHECK-NOFP: agr %r1, %r15
; CHECK-NOFP: mvi 7(%r1), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
; CHECK-FP: llilh %r1, 24
; CHECK-FP: agr %r1, %r11
; CHECK-FP: mvi 7(%r1), 42
; The LA then gets lowered into the LLILH/LA form. The exact sequence
; isn't that important though.
define void @f9() {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
; CHECK-NOFP: agfi [[R2]], 524288
; CHECK-NOFP: mvi 0([[R2]]), 42
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
; CHECK-FP: llilh [[R1:%r[1-5]]], 16
; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
; CHECK-FP: agfi [[R2]], 524288
; call-clobbered registers are live and no call-saved ones have been
; allocated).
define void @f10(i32 *%vptr) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: llilh [[REGISTER]], 8
; CHECK-NOFP: agr [[REGISTER]], %r15
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: llilh [[REGISTER]], 8
; CHECK-FP: agr [[REGISTER]], %r11
; However, the FP case uses %r11 as the frame pointer and must therefore
; spill a second register. This leads to an extra displacement of 8.
define void @f11(i32 *%vptr) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
; CHECK-NOFP: stmg %r6, %r15,
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: llilh [[REGISTER]], 8
; CHECK-NOFP: lmg %r6, %r15,
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
; CHECK-FP: stmg %r6, %r15,
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: llilh [[REGISTER]], 8
; in order to put another object at offset 4088 is (4088 - 176) / 4 = 978
; words.
define void @f1(double *%dst) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r11)
; CHECK-FP: br %r14
%region1 = alloca [978 x float], align 8
; Test the first out-of-range offset.
define void @f2(double *%dst) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
; CHECK-NOFP: lghi %r1, 4096
; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
; CHECK-FP: lghi %r1, 4096
; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
; CHECK-FP: br %r14
; Test the next offset after that.
define void @f3(double *%dst) {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
; CHECK-NOFP: lghi %r1, 4096
; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
; CHECK-FP: lghi %r1, 4096
; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
; CHECK-FP: br %r14
; Add 4096 bytes (1024 words) to the size of each object and repeat.
define void @f4(double *%dst) {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
; CHECK-NOFP: lghi %r1, 4096
; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
; CHECK-FP: lghi %r1, 4096
; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
; CHECK-FP: br %r14
; ...as above.
define void @f5(double *%dst) {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
; CHECK-NOFP: lghi %r1, 8192
; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
; CHECK-FP: lghi %r1, 8192
; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1,%r11)
; CHECK-FP: br %r14
; ...as above.
define void @f6(double *%dst) {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
; CHECK-NOFP: lghi %r1, 8192
; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
; CHECK-FP: lghi %r1, 8192
; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
; CHECK-FP: br %r14
; being at offset 8192. This time we need objects of (8192 - 168) / 4 = 2004
; words.
define void @f7(double *%dst) {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
; CHECK-NOFP: lghi %r1, 8192
; CHECK-NOFP: ldeb {{%f[0-7]}}, 4092(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
; CHECK-FP: lghi %r1, 8192
; CHECK-FP: ldeb {{%f[0-7]}}, 4092(%r1,%r11)
; CHECK-FP: br %r14
; Keep the object-relative offset the same but bump the size of the
; objects by one doubleword.
define void @f8(double *%dst) {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
; CHECK-NOFP: lghi %r1, 12288
; CHECK-NOFP: ldeb {{%f[0-7]}}, 4(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
; CHECK-FP: lghi %r1, 12288
; CHECK-FP: ldeb {{%f[0-7]}}, 4(%r1,%r11)
; CHECK-FP: br %r14
; should force an LAY from the outset. We don't yet do any kind of anchor
; optimization, so there should be no offset on the LDEB itself.
define void @f9(double *%dst) {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
; CHECK-NOFP: lay %r1, 12296(%r15)
; CHECK-NOFP: ldeb {{%f[0-7]}}, 0(%r1)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
; CHECK-FP: lay %r1, 12296(%r11)
; CHECK-FP: ldeb {{%f[0-7]}}, 0(%r1)
; CHECK-FP: br %r14
; %vptr and %dst are copied to call-saved registers, freeing up %r2 and
; %r3 during the main test.
define void @f10(i32 *%vptr, double *%dst) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: lghi [[REGISTER]], 4096
; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r15)
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: lghi [[REGISTER]], 4096
; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r11)
; Repeat f2 in a case where the index register is already occupied.
define void @f11(double *%dst, i64 %index) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
; CHECK-NOFP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3
; CHECK-NOFP: lay %r1, 4096(%r15)
; CHECK-NOFP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
; CHECK-FP: lgr [[REGISTER:%r[1-9][0-5]?]], %r3
; CHECK-FP: lay %r1, 4096(%r11)
; CHECK-FP: ldeb {{%f[0-7]}}, 0([[REGISTER]],%r1)
; emergency spill slots at 160(%r15), the amount that we need to allocate
; in order to put another object at offset 4088 is 4088 - 176 = 3912 bytes.
define void @f1(i8 %byte) {
-; CHECK-NOFP: f1:
+; CHECK-NOFP-LABEL: f1:
; CHECK-NOFP: stc %r2, 4095(%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f1:
+; CHECK-FP-LABEL: f1:
; CHECK-FP: stc %r2, 4095(%r11)
; CHECK-FP: br %r14
%region1 = alloca [3912 x i8], align 8
; Test the first offset that is out-of-range of the 12-bit form.
define void @f2(i8 %byte) {
-; CHECK-NOFP: f2:
+; CHECK-NOFP-LABEL: f2:
; CHECK-NOFP: stcy %r2, 4096(%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f2:
+; CHECK-FP-LABEL: f2:
; CHECK-FP: stcy %r2, 4096(%r11)
; CHECK-FP: br %r14
%region1 = alloca [3912 x i8], align 8
; The last in-range doubleword offset is 524280, so by the same reasoning
; as above, we need to allocate objects of 524280 - 176 = 524104 bytes.
define void @f3(i8 %byte) {
-; CHECK-NOFP: f3:
+; CHECK-NOFP-LABEL: f3:
; CHECK-NOFP: stcy %r2, 524287(%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f3:
+; CHECK-FP-LABEL: f3:
; CHECK-FP: stcy %r2, 524287(%r11)
; CHECK-FP: br %r14
%region1 = alloca [524104 x i8], align 8
; and the offset is also out of LAY's range, so expect a constant load
; followed by an addition.
define void @f4(i8 %byte) {
-; CHECK-NOFP: f4:
+; CHECK-NOFP-LABEL: f4:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: stc %r2, 0(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f4:
+; CHECK-FP-LABEL: f4:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: stc %r2, 0(%r1,%r11)
; CHECK-FP: br %r14
; Add 4095 to the previous offset, to test the other end of the STC range.
; The instruction will actually be STCY before frame lowering.
define void @f5(i8 %byte) {
-; CHECK-NOFP: f5:
+; CHECK-NOFP-LABEL: f5:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: stc %r2, 4095(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f5:
+; CHECK-FP-LABEL: f5:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: stc %r2, 4095(%r1,%r11)
; CHECK-FP: br %r14
; Test the next offset after that, which uses STCY instead of STC.
define void @f6(i8 %byte) {
-; CHECK-NOFP: f6:
+; CHECK-NOFP-LABEL: f6:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: stcy %r2, 4096(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f6:
+; CHECK-FP-LABEL: f6:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: stcy %r2, 4096(%r1,%r11)
; CHECK-FP: br %r14
; anchors 0x10000 bytes apart, so that the high part can be loaded using
; LLILH while still using STC in more cases than 0x40000 anchors would.
define void @f7(i8 %byte) {
-; CHECK-NOFP: f7:
+; CHECK-NOFP-LABEL: f7:
; CHECK-NOFP: llilh %r1, 23
; CHECK-NOFP: stcy %r2, 65535(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f7:
+; CHECK-FP-LABEL: f7:
; CHECK-FP: llilh %r1, 23
; CHECK-FP: stcy %r2, 65535(%r1,%r11)
; CHECK-FP: br %r14
; Keep the object-relative offset the same but bump the size of the
; objects by one doubleword.
define void @f8(i8 %byte) {
-; CHECK-NOFP: f8:
+; CHECK-NOFP-LABEL: f8:
; CHECK-NOFP: llilh %r1, 24
; CHECK-NOFP: stc %r2, 7(%r1,%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f8:
+; CHECK-FP-LABEL: f8:
; CHECK-FP: llilh %r1, 24
; CHECK-FP: stc %r2, 7(%r1,%r11)
; CHECK-FP: br %r14
; The LA then gets lowered into the LLILH/LA form. The exact sequence
; isn't that important though.
define void @f9(i8 %byte) {
-; CHECK-NOFP: f9:
+; CHECK-NOFP-LABEL: f9:
; CHECK-NOFP: llilh [[R1:%r[1-5]]], 16
; CHECK-NOFP: la [[R2:%r[1-5]]], 8([[R1]],%r15)
; CHECK-NOFP: agfi [[R2]], 524288
; CHECK-NOFP: stc %r2, 0([[R2]])
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f9:
+; CHECK-FP-LABEL: f9:
; CHECK-FP: llilh [[R1:%r[1-5]]], 16
; CHECK-FP: la [[R2:%r[1-5]]], 8([[R1]],%r11)
; CHECK-FP: agfi [[R2]], 524288
; call-clobbered registers are live and no call-saved ones have been
; allocated).
define void @f10(i32 *%vptr, i8 %byte) {
-; CHECK-NOFP: f10:
+; CHECK-NOFP-LABEL: f10:
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: llilh [[REGISTER]], 8
; CHECK-NOFP: stc %r3, 0([[REGISTER]],%r15)
; CHECK-NOFP: lg [[REGISTER]], [[OFFSET]](%r15)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f10:
+; CHECK-FP-LABEL: f10:
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: llilh [[REGISTER]], 8
; CHECK-FP: stc %r3, 0([[REGISTER]],%r11)
; However, the FP case uses %r11 as the frame pointer and must therefore
; spill a second register. This leads to an extra displacement of 8.
define void @f11(i32 *%vptr, i8 %byte) {
-; CHECK-NOFP: f11:
+; CHECK-NOFP-LABEL: f11:
; CHECK-NOFP: stmg %r6, %r15,
; CHECK-NOFP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r15)
; CHECK-NOFP: llilh [[REGISTER]], 8
; CHECK-NOFP: lmg %r6, %r15,
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f11:
+; CHECK-FP-LABEL: f11:
; CHECK-FP: stmg %r6, %r15,
; CHECK-FP: stg [[REGISTER:%r[1-9][0-4]?]], [[OFFSET:160|168]](%r11)
; CHECK-FP: llilh [[REGISTER]], 8
; Repeat f4 in a case where the index register is already occupied.
define void @f12(i8 %byte, i64 %index) {
-; CHECK-NOFP: f12:
+; CHECK-NOFP-LABEL: f12:
; CHECK-NOFP: llilh %r1, 8
; CHECK-NOFP: agr %r1, %r15
; CHECK-NOFP: stc %r2, 0(%r3,%r1)
; CHECK-NOFP: br %r14
;
-; CHECK-FP: f12:
+; CHECK-FP-LABEL: f12:
; CHECK-FP: llilh %r1, 8
; CHECK-FP: agr %r1, %r11
; CHECK-FP: stc %r2, 0(%r3,%r1)
; 4-byte spill slot, rounded to 8 bytes. The frame size should be exactly
; 160 + 8 * 8 = 232.
define void @f1(float *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: aghi %r15, -232
; CHECK: std %f8, 224(%r15)
; CHECK: std %f9, 216(%r15)
; Same for doubles, except that the full spill slot is used.
define void @f2(double *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r15, -232
; CHECK: std %f8, 224(%r15)
; CHECK: std %f9, 216(%r15)
; The long double case needs a 16-byte spill slot.
define void @f3(fp128 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: aghi %r15, -240
; CHECK: std %f8, 232(%r15)
; CHECK: std %f9, 224(%r15)
; We need to allocate a 4-byte spill slot, rounded to 8 bytes. The frame
; size should be exactly 160 + 8 = 168.
define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg %r6, %r15, 48(%r15)
; CHECK: aghi %r15, -168
; CHECK-NOT: 160(%r15)
; Same for i64, except that the full spill slot is used.
define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: stmg %r6, %r15, 48(%r15)
; CHECK: aghi %r15, -168
; CHECK: stg [[REGISTER:%r[0-9]+]], 160(%r15)
; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
; The whole sequence can be performed by IC.
define i32 @f1(i32 %orig, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: ni
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Like f1, but with the operands reversed.
define i32 @f2(i32 %orig, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: ni
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check a case where more bits than lower 8 are masked out of the
; register value. We can use IC but must keep the original mask.
define i32 @f3(i32 %orig, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: risbg %r2, %r2, 32, 182, 0
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Like f3, but with the operands reversed.
define i32 @f4(i32 %orig, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r2, 32, 182, 0
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check a case where the low 8 bits are cleared by a shift left.
define i32 @f5(i32 %orig, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sll %r2, 8
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Like f5, but with the operands reversed.
define i32 @f6(i32 %orig, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sll %r2, 8
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check insertions into a constant.
define i32 @f7(i32 %orig, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lhi %r2, 256
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Like f7, but with the operands reversed.
define i32 @f8(i32 %orig, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lhi %r2, 256
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the IC range.
define i32 @f9(i32 %orig, i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ic %r2, 4095(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4095
; Check the next byte up, which should use ICY instead of IC.
define i32 @f10(i32 %orig, i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: icy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4096
; Check the high end of the ICY range.
define i32 @f11(i32 %orig, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: icy %r2, 524287(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f12(i32 %orig, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: agfi %r3, 524288
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative ICY range.
define i32 @f13(i32 %orig, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: icy %r2, -1(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the ICY range.
define i32 @f14(i32 %orig, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: icy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f15(i32 %orig, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: agfi %r3, -524289
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check that IC allows an index.
define i32 @f16(i32 %orig, i8 *%src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%ptr1 = getelementptr i8 *%src, i64 %index
; Check that ICY allows an index.
define i32 @f17(i32 %orig, i8 *%src, i64 %index) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%ptr1 = getelementptr i8 *%src, i64 %index
; Check a plain insertion with (or (and ... -0xff) (zext (load ....))).
; The whole sequence can be performed by IC.
define i64 @f1(i64 %orig, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: ni
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Like f1, but with the operands reversed.
define i64 @f2(i64 %orig, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: ni
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check a case where more bits than lower 8 are masked out of the
; register value. We can use IC but must keep the original mask.
define i64 @f3(i64 %orig, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: risbg %r2, %r2, 0, 182, 0
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Like f3, but with the operands reversed.
define i64 @f4(i64 %orig, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r2, 0, 182, 0
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check a case where the low 8 bits are cleared by a shift left.
define i64 @f5(i64 %orig, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sllg %r2, %r2, 8
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Like f5, but with the operands reversed.
define i64 @f6(i64 %orig, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r2, %r2, 8
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check insertions into a constant.
define i64 @f7(i64 %orig, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lghi %r2, 256
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Like f7, but with the operands reversed.
define i64 @f8(i64 %orig, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lghi %r2, 256
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the IC range.
define i64 @f9(i64 %orig, i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ic %r2, 4095(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4095
; Check the next byte up, which should use ICY instead of IC.
define i64 @f10(i64 %orig, i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: icy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4096
; Check the high end of the ICY range.
define i64 @f11(i64 %orig, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: icy %r2, 524287(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f12(i64 %orig, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: agfi %r3, 524288
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative ICY range.
define i64 @f13(i64 %orig, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: icy %r2, -1(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the ICY range.
define i64 @f14(i64 %orig, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: icy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f15(i64 %orig, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: agfi %r3, -524289
; CHECK: ic %r2, 0(%r3)
; CHECK: br %r14
; Check that IC allows an index.
define i64 @f16(i64 %orig, i8 *%src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: ic %r2, 4095({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%ptr1 = getelementptr i8 *%src, i64 %index
; Check that ICY allows an index.
define i64 @f17(i64 %orig, i8 *%src, i64 %index) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: icy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%ptr1 = getelementptr i8 *%src, i64 %index
; Check the lowest useful IILL value. (We use NILL rather than IILL
; to clear 16 bits.)
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: ni
; CHECK: iill %r2, 1
; CHECK: br %r14
; Check a middle value.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: ni
; CHECK: iill %r2, 32769
; CHECK: br %r14
; Check the highest useful IILL value. (We use OILL rather than IILL
; to set 16 bits.)
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: ni
; CHECK: iill %r2, 65534
; CHECK: br %r14
; Check the lowest useful IILH value.
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: ni
; CHECK: iilh %r2, 1
; CHECK: br %r14
; Check a middle value.
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: ni
; CHECK: iilh %r2, 32767
; CHECK: br %r14
; Check the highest useful IILH value.
define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: ni
; CHECK: iilh %r2, 65534
; CHECK: br %r14
; Check the lowest useful IILL value. (We use NILL rather than IILL
; to clear 16 bits.)
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: ni
; CHECK: iill %r2, 1
; CHECK: br %r14
; Check a middle value.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: ni
; CHECK: iill %r2, 32769
; CHECK: br %r14
; Check the highest useful IILL value. (We use OILL rather than IILL
; to set 16 bits.)
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: ni
; CHECK: iill %r2, 65534
; CHECK: br %r14
; Check the lowest useful IILH value.
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: ni
; CHECK: iilh %r2, 1
; CHECK: br %r14
; Check a middle value.
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: ni
; CHECK: iilh %r2, 32767
; CHECK: br %r14
; Check the highest useful IILH value.
define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: ni
; CHECK: iilh %r2, 65534
; CHECK: br %r14
; Check the lowest useful IIHL value.
define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: ni
; CHECK: iihl %r2, 1
; CHECK: br %r14
; Check a middle value.
define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: ni
; CHECK: iihl %r2, 32767
; CHECK: br %r14
; Check the highest useful IIHL value.
define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: ni
; CHECK: iihl %r2, 65534
; CHECK: br %r14
; Check the lowest useful IIHH value.
define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: ni
; CHECK: iihh %r2, 1
; CHECK: br %r14
; Check a middle value.
define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: ni
; CHECK: iihh %r2, 32767
; CHECK: br %r14
; Check the highest useful IIHH value.
define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: ni
; CHECK: iihh %r2, 65534
; CHECK: br %r14
; Prefer LHI over IILF for signed 16-bit constants.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: ni
; CHECK: lhi %r2, 1
; CHECK: br %r14
; Check the high end of the LHI range.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: ni
; CHECK: lhi %r2, 32767
; CHECK: br %r14
; Check the next value up, which should use IILF instead.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: ni
; CHECK: iilf %r2, 32768
; CHECK: br %r14
; Check a value in which the lower 16 bits are clear.
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: ni
; CHECK: iilf %r2, 65536
; CHECK: br %r14
; Check the highest useful IILF value (-0x8001).
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: ni
; CHECK: iilf %r2, 4294934527
; CHECK: br %r14
; Check the next value up, which should use LHI instead.
define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: ni
; CHECK: lhi %r2, -32768
; CHECK: br %r14
; Check the highest useful LHI value. (We use OILF for -1 instead, although
; LHI might be better there too.)
define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: ni
; CHECK: lhi %r2, -2
; CHECK: br %r14
; Check that SRLG is still used if some of the high bits are known to be 0
; (and so might be removed from the mask).
define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: srlg %r2, %r2, 1
; CHECK-NEXT: iilf %r2, 32768
; CHECK: br %r14
; Repeat f8 with addition, which is known to be equivalent to OR in this case.
define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: srlg %r2, %r2, 1
; CHECK-NEXT: iilf %r2, 32768
; CHECK: br %r14
; Repeat f8 with already-zero bits removed from the mask.
define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: srlg %r2, %r2, 1
; CHECK-NEXT: iilf %r2, 32768
; CHECK: br %r14
; Repeat f10 with addition, which is known to be equivalent to OR in this case.
define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: srlg %r2, %r2, 1
; CHECK-NEXT: iilf %r2, 32768
; CHECK: br %r14
; Check the lowest useful IIHF value.
define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: ni
; CHECK: iihf %r2, 1
; CHECK: br %r14
; Check a value in which the lower 16 bits are clear.
define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK-NOT: ni
; CHECK: iihf %r2, 2147483648
; CHECK: br %r14
; Check the highest useful IIHF value (0xfffffffe).
define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: ni
; CHECK: iihf %r2, 4294967294
; CHECK: br %r14
; Check a case in which some of the low 32 bits are known to be clear,
; and so could be removed from the AND mask.
define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: sllg %r2, %r2, 1
; CHECK-NEXT: iihf %r2, 1
; CHECK: br %r14
; Repeat f15 with the zero bits explicitly removed from the mask.
define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: sllg %r2, %r2, 1
; CHECK-NEXT: iihf %r2, 1
; CHECK: br %r14
; Check concatenation of two i32s.
define i64 @f17(i32 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: msr %r2, %r2
; CHECK-NEXT: iihf %r2, 1
; CHECK: br %r14
; Repeat f17 with the operands reversed.
define i64 @f18(i32 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: msr %r2, %r2
; CHECK-NEXT: iihf %r2, 1
; CHECK: br %r14
; The truncation here isn't free; we need an explicit zero extension.
define i64 @f19(i32 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: llgcr %r2, %r2
; CHECK: oihl %r2, 1
; CHECK: br %r14
; Insertion of an i32 can be done using LR.
define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: {{%r[23]}}
; CHECK: lr %r2, %r3
; CHECK: br %r14
; ... and again with the operands reversed.
define i64 @f2(i64 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: {{%r[23]}}
; CHECK: lr %r2, %r3
; CHECK: br %r14
; Like f1, but with "in register" zero extension.
define i64 @f3(i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: {{%r[23]}}
; CHECK: lr %r2, %r3
; CHECK: br %r14
; ... and again with the operands reversed.
define i64 @f4(i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: {{%r[23]}}
; CHECK: lr %r2, %r3
; CHECK: br %r14
; Unary operations can be done directly into the low half.
define i64 @f5(i64 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: {{%r[23]}}
; CHECK: lcr %r2, %r3
; CHECK: br %r14
; ...likewise three-operand binary operations like RLL.
define i64 @f6(i64 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: {{%r[23]}}
; CHECK: rll %r2, %r3, 1
; CHECK: br %r14
; Loads can be done directly into the low half. The range of L is checked
; in the move tests.
define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: {{%r[23]}}
; CHECK: l %r2, 0(%r3)
; CHECK: br %r14
; ...likewise extending loads.
define i64 @f8(i64 %a, i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: {{%r[23]}}
; CHECK: lb %r2, 0(%r3)
; CHECK: br %r14
; that the upper half of one OR operand and the lower half of the other are
; both clear.
define i64 @f9(i64 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: sllg %r2, %r2, 32
; CHECK: lr %r2, %r3
; CHECK: br %r14
; ...and again with the operands reversed.
define i64 @f10(i64 %a, i32 %b) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: sllg %r2, %r2, 32
; CHECK: lr %r2, %r3
; CHECK: br %r14
; Like f9, but with "in register" zero extension.
define i64 @f11(i64 %a, i64 %b) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: lr %r2, %r3
; CHECK: br %r14
%shift = shl i64 %a, 32
; ...and again with the operands reversed.
define i64 @f12(i64 %a, i64 %b) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: lr %r2, %r3
; CHECK: br %r14
%shift = shl i64 %a, 32
; Like f9, but for larger shifts than 32.
define i64 @f13(i64 %a, i32 %b) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: sllg %r2, %r2, 60
; CHECK: lr %r2, %r3
; CHECK: br %r14
; Check the low end of the AH range.
define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ah %r2, 0(%r3)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the aligned AH range.
define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ah %r2, 4094(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2047
; Check the next halfword up, which should use AHY instead of AH.
define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ahy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2048
; Check the high end of the aligned AHY range.
define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ahy %r2, 524286(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, 524288
; CHECK: ah %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned AHY range.
define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ahy %r2, -2(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the AHY range.
define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ahy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524290
; CHECK: ah %r2, 0(%r3)
; CHECK: br %r14
; Check that AH allows an index.
define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ah %r2, 4094({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that AHY allows an index.
define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ahy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check AR.
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ar %r2, %r3
; CHECK: br %r14
%add = add i32 %a, %b
; Check the low end of the A range.
define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: a %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned A range.
define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: a %r2, 4092(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
; Check the next word up, which should use AY instead of A.
define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ay %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
; Check the high end of the aligned AY range.
define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ay %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: a %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned AY range.
define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ay %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the AY range.
define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ay %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: a %r2, 0(%r3)
; CHECK: br %r14
; Check that A allows an index.
define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: a %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that AY allows an index.
define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: ay %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that additions of spilled values can use A rather than AR.
define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK: a %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check AGFR.
define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: agfr %r2, %r3
; CHECK: br %r14
%bext = sext i32 %b to i64
; Check AGF with no displacement.
define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: agf %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned AGF range.
define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agf %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: agf %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned AGF range.
define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agf %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the AGF range.
define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agf %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524292
; CHECK: agf %r2, 0(%r3)
; CHECK: br %r14
; Check that AGF allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agf %r2, 524284({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that additions of spilled values can use AGF rather than AGFR.
define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: agf %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check ALGFR.
define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: algfr %r2, %r3
; CHECK: br %r14
%bext = zext i32 %b to i64
; Check ALGF with no displacement.
define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: algf %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned ALGF range.
define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: algf %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: algf %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned ALGF range.
define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: algf %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the ALGF range.
define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: algf %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524292
; CHECK: algf %r2, 0(%r3)
; CHECK: br %r14
; Check that ALGF allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: algf %r2, 524284({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that additions of spilled values can use ALGF rather than ALGFR.
define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: algf %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check AGR.
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: agr %r2, %r3
; CHECK: br %r14
%add = add i64 %a, %b
; Check AG with no displacement.
define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ag %r2, 0(%r3)
; CHECK: br %r14
%b = load i64 *%src
; Check the high end of the aligned AG range.
define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ag %r2, 524280(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: ag %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned AG range.
define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ag %r2, -8(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the AG range.
define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ag %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: ag %r2, 0(%r3)
; CHECK: br %r14
; Check that AG allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: ag %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that additions of spilled values can use AG rather than AGR.
define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: ag %r2, 160(%r15)
; CHECK: br %r14
; Check additions of 1.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ahi %r2, 1
; CHECK: br %r14
%add = add i32 %a, 1
; Check the high end of the AHI range.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ahi %r2, 32767
; CHECK: br %r14
%add = add i32 %a, 32767
; Check the next value up, which must use AFI instead.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: afi %r2, 32768
; CHECK: br %r14
%add = add i32 %a, 32768
; Check the high end of the signed 32-bit range.
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: afi %r2, 2147483647
; CHECK: br %r14
%add = add i32 %a, 2147483647
; Check the next value up, which is treated as a negative value.
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: afi %r2, -2147483648
; CHECK: br %r14
%add = add i32 %a, 2147483648
; Check the high end of the negative AHI range.
define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ahi %r2, -1
; CHECK: br %r14
%add = add i32 %a, -1
; Check the low end of the AHI range.
define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ahi %r2, -32768
; CHECK: br %r14
%add = add i32 %a, -32768
; Check the next value down, which must use AFI instead.
define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: afi %r2, -32769
; CHECK: br %r14
%add = add i32 %a, -32769
; Check the low end of the signed 32-bit range.
define i32 @f9(i32 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: afi %r2, -2147483648
; CHECK: br %r14
%add = add i32 %a, -2147483648
; Check the next value down, which is treated as a positive value.
define i32 @f10(i32 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: afi %r2, 2147483647
; CHECK: br %r14
%add = add i32 %a, -2147483649
; Check additions of 1.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: {{aghi %r2, 1|la %r[0-5], 1\(%r2\)}}
; CHECK: br %r14
%add = add i64 %a, 1
; Check the high end of the AGHI range.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: aghi %r2, 32767
; CHECK: br %r14
%add = add i64 %a, 32767
; Check the next value up, which must use AGFI instead.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: {{agfi %r2, 32768|lay %r[0-5], 32768\(%r2\)}}
; CHECK: br %r14
%add = add i64 %a, 32768
; Check the high end of the AGFI range.
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r2, 2147483647
; CHECK: br %r14
%add = add i64 %a, 2147483647
; Check the next value up, which must use ALGFI instead.
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: algfi %r2, 2147483648
; CHECK: br %r14
%add = add i64 %a, 2147483648
; Check the high end of the ALGFI range.
define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: algfi %r2, 4294967295
; CHECK: br %r14
%add = add i64 %a, 4294967295
; Check the next value up, which must be loaded into a register first.
define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llihl %r0, 1
; CHECK: agr
; CHECK: br %r14
; Check the high end of the negative AGHI range.
define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r2, -1
; CHECK: br %r14
%add = add i64 %a, -1
; Check the low end of the AGHI range.
define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: aghi %r2, -32768
; CHECK: br %r14
%add = add i64 %a, -32768
; Check the next value down, which must use AGFI instead.
define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: {{agfi %r2, -32769|lay %r[0-5]+, -32769\(%r2\)}}
; CHECK: br %r14
%add = add i64 %a, -32769
; Check the low end of the AGFI range.
define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r2, -2147483648
; CHECK: br %r14
%add = add i64 %a, -2147483648
; Check the next value down, which must use SLGFI instead.
define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: slgfi %r2, 2147483649
; CHECK: br %r14
%add = add i64 %a, -2147483649
; Check the low end of the SLGFI range.
define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: slgfi %r2, 4294967295
; CHECK: br %r14
%add = add i64 %a, -4294967295
; Check the next value down, which must use register addition instead.
define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: llihf %r0, 4294967295
; CHECK: agr
; CHECK: br %r14
; Test register addition.
define void @f1(i128 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: algr
; CHECK: alcgr
; CHECK: br %r14
; Test memory addition with no offset. Making the load of %a volatile
; should force the memory operand to be %b.
define void @f2(i128 *%aptr, i64 %addr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: alg {{%r[0-5]}}, 8(%r3)
; CHECK: alcg {{%r[0-5]}}, 0(%r3)
; CHECK: br %r14
; Test the highest aligned offset that is in range of both ALG and ALCG.
define void @f3(i128 *%aptr, i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: alg {{%r[0-5]}}, 524280(%r3)
; CHECK: alcg {{%r[0-5]}}, 524272(%r3)
; CHECK: br %r14
; Test the next doubleword up, which requires separate address logic for ALG.
define void @f4(i128 *%aptr, i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lgr [[BASE:%r[1-5]]], %r3
; CHECK: agfi [[BASE]], 524288
; CHECK: alg {{%r[0-5]}}, 0([[BASE]])
; both instructions. It would be better to create an anchor at 524288
; that both instructions can use, but that isn't implemented yet.
define void @f5(i128 *%aptr, i64 %base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: alg {{%r[0-5]}}, 0({{%r[1-5]}})
; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
; CHECK: br %r14
; Test the lowest displacement that is in range of both ALG and ALCG.
define void @f6(i128 *%aptr, i64 %base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: alg {{%r[0-5]}}, -524280(%r3)
; CHECK: alcg {{%r[0-5]}}, -524288(%r3)
; CHECK: br %r14
; Test the next doubleword down, which is out of range of the ALCG.
define void @f7(i128 *%aptr, i64 %base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: alg {{%r[0-5]}}, -524288(%r3)
; CHECK: alcg {{%r[0-5]}}, 0({{%r[1-5]}})
; CHECK: br %r14
; Check that additions of spilled values can use ALG and ALCG rather than
; ALGR and ALCGR.
define void @f8(i128 *%ptr0) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: brasl %r14, foo@PLT
; CHECK: alg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
; CHECK: alcg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
; Check additions of 1. The XOR ensures that we don't instead load the
; constant into a register and use memory addition.
define void @f1(i128 *%aptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: algfi {{%r[0-5]}}, 1
; CHECK: alcgr
; CHECK: br %r14
; Check the high end of the ALGFI range.
define void @f2(i128 *%aptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: algfi {{%r[0-5]}}, 4294967295
; CHECK: alcgr
; CHECK: br %r14
; Check the next value up, which must use register addition.
define void @f3(i128 *%aptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: algr
; CHECK: alcgr
; CHECK: br %r14
; Check addition of -1, which must also use register addition.
define void @f4(i128 *%aptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: algr
; CHECK: alcgr
; CHECK: br %r14
; Check register additions. The XOR ensures that we don't instead zero-extend
; %b into a register and use memory addition.
define void @f1(i128 *%aptr, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: algfr {{%r[0-5]}}, %r3
; CHECK: alcgr
; CHECK: br %r14
; Like f1, but using an "in-register" extension.
define void @f2(i128 *%aptr, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: algfr {{%r[0-5]}}, %r3
; CHECK: alcgr
; CHECK: br %r14
; Test register addition in cases where the second operand is zero extended
; from i64 rather than i32, but is later masked to i32 range.
define void @f3(i128 *%aptr, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: algfr {{%r[0-5]}}, %r3
; CHECK: alcgr
; CHECK: br %r14
; Test ALGF with no offset.
define void @f4(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: algf {{%r[0-5]}}, 0(%r3)
; CHECK: alcgr
; CHECK: br %r14
; Check the high end of the ALGF range.
define void @f5(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: algf {{%r[0-5]}}, 524284(%r3)
; CHECK: alcgr
; CHECK: br %r14
; Check the next word up, which must use separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: algf {{%r[0-5]}}, 0(%r3)
; CHECK: alcgr
; Check the high end of the negative aligned ALGF range.
define void @f7(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: algf {{%r[0-5]}}, -4(%r3)
; CHECK: alcgr
; CHECK: br %r14
; Check the low end of the ALGF range.
define void @f8(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: algf {{%r[0-5]}}, -524288(%r3)
; CHECK: alcgr
; CHECK: br %r14
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f9(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: algf {{%r[0-5]}}, 0(%r3)
; CHECK: alcgr
; Check that ALGF allows an index.
define void @f10(i128 *%aptr, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: algf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%a = load i128 *%aptr
; Check additions of 1.
define void @f1(i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: asi 0(%r2), 1
; CHECK: br %r14
%val = load i32 *%ptr
; Check the high end of the constant range.
define void @f2(i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: asi 0(%r2), 127
; CHECK: br %r14
%val = load i32 *%ptr
; Check the next constant up, which must use an addition and a store.
; Both L/AHI and LHI/A would be OK.
define void @f3(i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: asi
; CHECK: st %r0, 0(%r2)
; CHECK: br %r14
; Check the low end of the constant range.
define void @f4(i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: asi 0(%r2), -128
; CHECK: br %r14
%val = load i32 *%ptr
; Check the next value down, with the same comment as f3.
define void @f5(i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: asi
; CHECK: st %r0, 0(%r2)
; CHECK: br %r14
; Check the high end of the aligned ASI range.
define void @f6(i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: asi 524284(%r2), 1
; CHECK: br %r14
%ptr = getelementptr i32 *%base, i64 131071
; Check the next word up, which must use separate address logic.
; Other sequences besides this one would be OK.
define void @f7(i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r2, 524288
; CHECK: asi 0(%r2), 1
; CHECK: br %r14
; Check the low end of the ASI range.
define void @f8(i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: asi -524288(%r2), 1
; CHECK: br %r14
%ptr = getelementptr i32 *%base, i64 -131072
; Check the next word down, which must use separate address logic.
; Other sequences besides this one would be OK.
define void @f9(i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524292
; CHECK: asi 0(%r2), 1
; CHECK: br %r14
; Check that ASI does not allow indices.
define void @f10(i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agr %r2, %r3
; CHECK: asi 4(%r2), 1
; CHECK: br %r14
; Check additions of 1.
define void @f1(i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: agsi 0(%r2), 1
; CHECK: br %r14
%val = load i64 *%ptr
; Check the high end of the constant range.
define void @f2(i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: agsi 0(%r2), 127
; CHECK: br %r14
%val = load i64 *%ptr
; Check the next constant up, which must use an addition and a store.
; Both LG/AGHI and LGHI/AG would be OK.
define void @f3(i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: agsi
; CHECK: stg %r0, 0(%r2)
; CHECK: br %r14
; Check the low end of the constant range.
define void @f4(i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agsi 0(%r2), -128
; CHECK: br %r14
%val = load i64 *%ptr
; Check the next value down, with the same comment as f3.
define void @f5(i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: agsi
; CHECK: stg %r0, 0(%r2)
; CHECK: br %r14
; Check the high end of the aligned AGSI range.
define void @f6(i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agsi 524280(%r2), 1
; CHECK: br %r14
%ptr = getelementptr i64 *%base, i64 65535
; Check the next doubleword up, which must use separate address logic.
; Other sequences besides this one would be OK.
define void @f7(i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r2, 524288
; CHECK: agsi 0(%r2), 1
; CHECK: br %r14
; Check the low end of the AGSI range.
define void @f8(i64 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agsi -524288(%r2), 1
; CHECK: br %r14
%ptr = getelementptr i64 *%base, i64 -65536
; Check the next doubleword down, which must use separate address logic.
; Other sequences besides this one would be OK.
define void @f9(i64 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524296
; CHECK: agsi 0(%r2), 1
; CHECK: br %r14
; Check that AGSI does not allow indices.
define void @f10(i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agr %r2, %r3
; CHECK: agsi 8(%r2), 1
; CHECK: br %r14
; Check the low end of the CH range.
define void @f1(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ch %r2, 0(%r3)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the aligned CH range.
define void @f2(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ch %r2, 4094(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2047
; Check the next halfword up, which should use CHY instead of CH.
define void @f3(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: chy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2048
; Check the high end of the aligned CHY range.
define void @f4(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: chy %r2, 524286(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f5(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, 524288
; CHECK: ch %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned CHY range.
define void @f6(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: chy %r2, -2(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the CHY range.
define void @f7(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: chy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(i32 %lhs, i16 *%src, i32 *%dst) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524290
; CHECK: ch %r2, 0(%r3)
; CHECK: br %r14
; Check that CH allows an index.
define void @f9(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ch %r2, 4094({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %base, %index
; Check that CHY allows an index.
define void @f10(i32 %lhs, i64 %base, i64 %index, i32 *%dst) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: chy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %base, %index
; Check register comparison.
define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: crjl %r2, %r3
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the low end of the C range.
define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: c %r2, 0(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the aligned C range.
define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: c %r2, 4092(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word up, which should use CY instead of C.
define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cy %r2, 4096(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the aligned CY range.
define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cy %r2, 524284(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: c %r2, 0(%r3)
; CHECK-NEXT: jl
; Check the high end of the negative aligned CY range.
define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cy %r2, -4(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CY range.
define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cy %r2, -524288(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: c %r2, 0(%r3)
; CHECK-NEXT: jl
; Check that C allows an index.
define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: c %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check that CY allows an index.
define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: cy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check register comparison.
define double @f1(double %a, double %b, i32 %i1, i32 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clr %r2, %r3
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CL range.
define double @f2(double %a, double %b, i32 %i1, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cl %r2, 0(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the aligned CL range.
define double @f3(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cl %r2, 4092(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word up, which should use CLY instead of CL.
define double @f4(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cly %r2, 4096(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the aligned CLY range.
define double @f5(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cly %r2, 524284(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f6(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: cl %r2, 0(%r3)
; CHECK-NEXT: jl
; Check the high end of the negative aligned CLY range.
define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cly %r2, -4(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CLY range.
define double @f8(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cly %r2, -524288(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f9(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: cl %r2, 0(%r3)
; CHECK-NEXT: jl
; Check that CL allows an index.
define double @f10(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cl %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check that CLY allows an index.
define double @f11(double %a, double %b, i32 %i1, i64 %base, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: cly %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check CGH with no displacement.
define void @f1(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgh %r2, 0(%r3)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the aligned CGH range.
define void @f2(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cgh %r2, 524286(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f3(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r3, 524288
; CHECK: cgh %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned CGH range.
define void @f4(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cgh %r2, -2(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the CGH range.
define void @f5(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cgh %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i64 %lhs, i16 *%src, i64 *%dst) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, -524290
; CHECK: cgh %r2, 0(%r3)
; CHECK: br %r14
; Check that CGH allows an index.
define void @f7(i64 %lhs, i64 %base, i64 %index, i64 *%dst) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cgh %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %base, %index
; Check signed register comparison.
define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgfr %r2, %r3
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check unsigned register comparison, which can't use CGFR.
define double @f2(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: cgfr
; CHECK: br %r14
%i2 = sext i32 %unext to i64
; Check register equality.
define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cgfr %r2, %r3
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check register inequality.
define double @f4(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cgfr %r2, %r3
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check signed comparisonn with memory.
define double @f5(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cgf %r2, 0(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check unsigned comparison with memory.
define double @f6(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: cgf
; CHECK: br %r14
%unext = load i32 *%ptr
; Check memory equality.
define double @f7(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cgf %r2, 0(%r3)
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check memory inequality.
define double @f8(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cgf %r2, 0(%r3)
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the high end of the aligned CGF range.
define double @f9(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cgf %r2, 524284(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f10(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r3, 524288
; CHECK: cgf %r2, 0(%r3)
; CHECK-NEXT: jl
; Check the high end of the negative aligned CGF range.
define double @f11(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: cgf %r2, -4(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CGF range.
define double @f12(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: cgf %r2, -524288(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: agfi %r3, -524292
; CHECK: cgf %r2, 0(%r3)
; CHECK-NEXT: jl
; Check that CGF allows an index.
define double @f14(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: cgf %r2, 524284({{%r4,%r3|%r3,%r4}})
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check that comparisons of spilled values can use CGF rather than CGFR.
define i64 @f15(i32 *%ptr0) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: brasl %r14, foo@PLT
; CHECK: cgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check unsigned register comparison.
define double @f1(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clgfr %r2, %r3
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; ...and again with a different representation.
define double @f2(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clgfr %r2, %r3
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check signed register comparison, which can't use CLGFR.
define double @f3(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: clgfr
; CHECK: br %r14
%i2 = zext i32 %unext to i64
; ...and again with a different representation
define double @f4(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: clgfr
; CHECK: br %r14
%i2 = and i64 %unext, 4294967295
; Check register equality.
define double @f5(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: clgfr %r2, %r3
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; ...and again with a different representation
define double @f6(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: clgfr %r2, %r3
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check register inequality.
define double @f7(double %a, double %b, i64 %i1, i32 %unext) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: clgfr %r2, %r3
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; ...and again with a different representation
define double @f8(double %a, double %b, i64 %i1, i64 %unext) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clgfr %r2, %r3
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check unsigned comparisonn with memory.
define double @f9(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: clgf %r2, 0(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check signed comparison with memory.
define double @f10(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: clgf
; CHECK: br %r14
%unext = load i32 *%ptr
; Check memory equality.
define double @f11(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: clgf %r2, 0(%r3)
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check memory inequality.
define double @f12(double %a, double %b, i64 %i1, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: clgf %r2, 0(%r3)
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the high end of the aligned CLGF range.
define double @f13(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: clgf %r2, 524284(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f14(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: agfi %r3, 524288
; CHECK: clgf %r2, 0(%r3)
; CHECK-NEXT: jl
; Check the high end of the negative aligned CLGF range.
define double @f15(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: clgf %r2, -4(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CLGF range.
define double @f16(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: clgf %r2, -524288(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f17(double %a, double %b, i64 %i1, i32 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: agfi %r3, -524292
; CHECK: clgf %r2, 0(%r3)
; CHECK-NEXT: jl
; Check that CLGF allows an index.
define double @f18(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: clgf %r2, 524284({{%r4,%r3|%r3,%r4}})
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check that comparisons of spilled values can use CLGF rather than CLGFR.
define i64 @f19(i32 *%ptr0) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: brasl %r14, foo@PLT
; CHECK: clgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check CGR.
define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgrjl %r2, %r3
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check CG with no displacement.
define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cg %r2, 0(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the aligned CG range.
define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cg %r2, 524280(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: cg %r2, 0(%r3)
; CHECK-NEXT: jl
; Check the high end of the negative aligned CG range.
define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cg %r2, -8(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CG range.
define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cg %r2, -524288(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: cg %r2, 0(%r3)
; CHECK-NEXT: jl
; Check that CG allows an index.
define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cg %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check CLGR.
define double @f1(double %a, double %b, i64 %i1, i64 %i2) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clgr %r2, %r3
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check CLG with no displacement.
define double @f2(double %a, double %b, i64 %i1, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clg %r2, 0(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the aligned CLG range.
define double @f3(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clg %r2, 524280(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f4(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: clg %r2, 0(%r3)
; CHECK-NEXT: jl
; Check the high end of the negative aligned CLG range.
define double @f5(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: clg %r2, -8(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CLG range.
define double @f6(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: clg %r2, -524288(%r3)
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: clg %r2, 0(%r3)
; CHECK-NEXT: jl
; Check that CLG allows an index.
define double @f8(double %a, double %b, i64 %i1, i64 %base, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clg %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check comparisons with 0.
define double @f1(double %a, double %b, i32 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cijl %r2, 0
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check comparisons with 1.
define double @f2(double %a, double %b, i32 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cijl %r2, 1
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the high end of the CIJ range.
define double @f3(double %a, double %b, i32 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cijl %r2, 127
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the next value up, which must use CHI instead.
define double @f4(double %a, double %b, i32 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: chi %r2, 128
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the CHI range.
define double @f5(double %a, double %b, i32 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: chi %r2, 32767
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value up, which must use CFI.
define double @f6(double %a, double %b, i32 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cfi %r2, 32768
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the signed 32-bit range.
define double @f7(double %a, double %b, i32 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cfi %r2, 2147483647
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value up, which should be treated as a negative value.
define double @f8(double %a, double %b, i32 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cfi %r2, -2147483648
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the high end of the negative CIJ range.
define double @f9(double %a, double %b, i32 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cijl %r2, -1
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the low end of the CIJ range.
define double @f10(double %a, double %b, i32 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cijl %r2, -128
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the next value down, which must use CHI instead.
define double @f11(double %a, double %b, i32 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: chi %r2, -129
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CHI range.
define double @f12(double %a, double %b, i32 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: chi %r2, -32768
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value down, which must use CFI instead.
define double @f13(double %a, double %b, i32 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: cfi %r2, -32769
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the signed 32-bit range.
define double @f14(double %a, double %b, i32 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: cfi %r2, -2147483648
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value down, which should be treated as a positive value.
define double @f15(double %a, double %b, i32 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: cfi %r2, 2147483647
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check a value near the low end of the range. We use CFI for comparisons
; with zero, or things that are equivalent to them.
define double @f1(double %a, double %b, i32 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clfi %r2, 1
; CHECK-NEXT: jh
; CHECK: ldr %f0, %f2
; Check a value near the high end of the range.
define double @f2(double %a, double %b, i32 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clfi %r2, 4294967280
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check comparisons with 0.
define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgijl %r2, 0
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check comparisons with 1.
define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cgijl %r2, 1
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the high end of the CGIJ range.
define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cgijl %r2, 127
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the next value up, which must use CGHI instead.
define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cghi %r2, 128
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the CGHI range.
define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cghi %r2, 32767
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value up, which must use CGFI.
define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cgfi %r2, 32768
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the CGFI range.
define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cgfi %r2, 2147483647
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value up, which must use register comparison.
define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cgrjl
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the high end of the negative CGIJ range.
define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cgijl %r2, -1
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the low end of the CGIJ range.
define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cgijl %r2, -128
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the next value down, which must use CGHI instead.
define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: cghi %r2, -129
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CGHI range.
define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: cghi %r2, -32768
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value down, which must use CGFI instead.
define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: cgfi %r2, -32769
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the low end of the CGFI range.
define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: cgfi %r2, -2147483648
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value down, which must use register comparison.
define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: cgrjl
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check a value near the low end of the range. We use CGFI for comparisons
; with zero, or things that are equivalent to them.
define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clgfi %r2, 1
; CHECK-NEXT: jh
; CHECK: ldr %f0, %f2
; Check the high end of the CLGFI range.
define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clgfi %r2, 4294967295
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value up, which must use a register comparison.
define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clgr %r2,
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check comparisons with 0.
define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgije %r2, 0
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the high end of the CGIJ range.
define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cgije %r2, 127
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the next value up, which must use CGHI instead.
define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cghi %r2, 128
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the high end of the CGHI range.
define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cghi %r2, 32767
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value up, which must use CGFI.
define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cgfi %r2, 32768
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the high end of the CGFI range.
define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cgfi %r2, 2147483647
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value up, which should use CLGFI instead.
define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: clgfi %r2, 2147483648
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the high end of the CLGFI range.
define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clgfi %r2, 4294967295
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value up, which must use a register comparison.
define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cgrje %r2,
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the high end of the negative CGIJ range.
define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cgije %r2, -1
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the low end of the CGIJ range.
define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: cgije %r2, -128
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the next value down, which must use CGHI instead.
define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: cghi %r2, -129
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the low end of the CGHI range.
define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: cghi %r2, -32768
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value down, which must use CGFI instead.
define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: cgfi %r2, -32769
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the low end of the CGFI range.
define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: cgfi %r2, -2147483648
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value down, which must use register comparison.
define double @f16(double %a, double %b, i64 %i1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: cgrje
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check comparisons with 0.
define double @f1(double %a, double %b, i64 %i1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgijlh %r2, 0
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the high end of the CGIJ range.
define double @f2(double %a, double %b, i64 %i1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cgijlh %r2, 127
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the next value up, which must use CGHI instead.
define double @f3(double %a, double %b, i64 %i1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cghi %r2, 128
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the high end of the CGHI range.
define double @f4(double %a, double %b, i64 %i1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cghi %r2, 32767
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the next value up, which must use CGFI.
define double @f5(double %a, double %b, i64 %i1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cgfi %r2, 32768
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the high end of the CGFI range.
define double @f6(double %a, double %b, i64 %i1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cgfi %r2, 2147483647
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the next value up, which should use CLGFI instead.
define double @f7(double %a, double %b, i64 %i1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: clgfi %r2, 2147483648
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the high end of the CLGFI range.
define double @f8(double %a, double %b, i64 %i1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clgfi %r2, 4294967295
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the next value up, which must use a register comparison.
define double @f9(double %a, double %b, i64 %i1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cgrjlh %r2,
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the high end of the negative CGIJ range.
define double @f10(double %a, double %b, i64 %i1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cgijlh %r2, -1
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the low end of the CGIJ range.
define double @f11(double %a, double %b, i64 %i1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: cgijlh %r2, -128
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check the next value down, which must use CGHI instead.
define double @f12(double %a, double %b, i64 %i1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: cghi %r2, -129
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the low end of the CGHI range.
define double @f13(double %a, double %b, i64 %i1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: cghi %r2, -32768
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the next value down, which must use CGFI instead.
define double @f14(double %a, double %b, i64 %i1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: cgfi %r2, -32769
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the low end of the CGFI range.
define double @f15(double %a, double %b, i64 %i1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: cgfi %r2, -2147483648
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the next value down, which must use register comparison.
define double @f16(double %a, double %b, i64 %i1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: cgrjlh
; CHECK: ldr %f0, %f2
; CHECK: br %r14
; Check ordered comparisons near the low end of the unsigned 8-bit range.
define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cli 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check ordered comparisons near the high end of the unsigned 8-bit range.
define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cli 0(%r2), 254
; CHECK-NEXT: jl
; CHECK: br %r14
; Check tests for negative bytes.
define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: jh
; CHECK: br %r14
; ...and an alternative form.
define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: jh
; CHECK: br %r14
; Check tests for non-negative bytes.
define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: jl
; CHECK: br %r14
; ...and an alternative form.
define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: jl
; CHECK: br %r14
; Check equality comparisons at the low end of the signed 8-bit range.
define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: je
; CHECK: br %r14
; Check equality comparisons at the low end of the unsigned 8-bit range.
define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check equality comparisons at the high end of the signed 8-bit range.
define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: je
; CHECK: br %r14
; Check equality comparisons at the high end of the unsigned 8-bit range.
define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the CLI range.
define double @f11(double %a, double %b, i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: cli 4095(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4095
; Check the next byte up, which should use CLIY instead of CLI.
define double @f12(double %a, double %b, i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: cliy 4096(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4096
; Check the high end of the CLIY range.
define double @f13(double %a, double %b, i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: cliy 524287(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f14(double %a, double %b, i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: agfi %r2, 524288
; CHECK: cli 0(%r2), 127
; CHECK: br %r14
; Check the high end of the negative CLIY range.
define double @f15(double %a, double %b, i8 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: cliy -1(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the CLIY range.
define double @f16(double %a, double %b, i8 *%src) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: cliy -524288(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define double @f17(double %a, double %b, i8 *%src) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: agfi %r2, -524289
; CHECK: cli 0(%r2), 127
; CHECK: br %r14
; Check that CLI does not allow an index
define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: agr %r2, %r3
; CHECK: cli 4095(%r2), 127
; CHECK: br %r14
; Check that CLIY does not allow an index
define double @f19(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: agr %r2, %r3
; CHECK: cliy 4096(%r2), 127
; CHECK: br %r14
; Check the low end of the 8-bit unsigned range, with zero extension.
define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the 8-bit unsigned range, with zero extension.
define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value up, with zero extension. The condition is always false.
define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with -1, with zero extension.
; This condition is also always false.
define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with 0, using sign extension.
define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the signed 8-bit range, using sign extension.
define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value up, using sign extension.
; The condition is always false.
define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with -1, using sign extension.
define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: je
; CHECK: br %r14
; Check the low end of the signed 8-bit range, using sign extension.
define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value down, using sign extension.
; The condition is always false.
define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check the low end of the 8-bit unsigned range, with zero extension.
define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the high end of the 8-bit unsigned range, with zero extension.
define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value up, with zero extension. The condition is always false.
define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with -1, with zero extension.
; This condition is also always false.
define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with 0, using sign extension.
define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the high end of the signed 8-bit range, using sign extension.
define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value up, using sign extension.
; The condition is always false.
define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with -1, using sign extension.
define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the low end of the signed 8-bit range, using sign extension.
define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value down, using sign extension.
; The condition is always false.
define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check the low end of the 8-bit unsigned range, with zero extension.
define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the 8-bit unsigned range, with zero extension.
define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value up, with zero extension. The condition is always false.
define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with -1, with zero extension.
; This condition is also always false.
define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with 0, using sign extension.
define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the signed 8-bit range, using sign extension.
define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value up, using sign extension.
; The condition is always false.
define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with -1, using sign extension.
define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: je
; CHECK: br %r14
; Check the low end of the signed 8-bit range, using sign extension.
define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value down, using sign extension.
; The condition is always false.
define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check the low end of the 8-bit unsigned range, with zero extension.
define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the high end of the 8-bit unsigned range, with zero extension.
define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value up, with zero extension. The condition is always false.
define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with -1, with zero extension.
; This condition is also always false.
define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with 0, using sign extension.
define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cli 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the high end of the signed 8-bit range, using sign extension.
define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value up, using sign extension.
; The condition is always false.
define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check comparisons with -1, using sign extension.
define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cli 0(%r2), 255
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the low end of the signed 8-bit range, using sign extension.
define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value down, using sign extension.
; The condition is always false.
define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check unsigned comparison near the low end of the CLI range, using zero
; extension.
define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cli 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the low end of the CLI range, using sign
; extension.
define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cli 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the high end of the CLI range, using zero
; extension.
define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cli 0(%r2), 254
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison near the high end of the CLI range, using sign
; extension.
define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cli 0(%r2), 254
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison above the high end of the CLI range, using zero
; extension. The condition is always true.
define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; unlikely to occur in practice, we don't bother optimizing the second case,
; and simply ignore CLI for this range. First check the low end of the range.
define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; ...and then the high end.
define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check signed comparison near the low end of the CLI range, using zero
; extension. This is equivalent to unsigned comparison.
define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cli 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check signed comparison near the low end of the CLI range, using sign
; extension. This cannot use CLI.
define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check signed comparison near the high end of the CLI range, using zero
; extension. This is equivalent to unsigned comparison.
define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cli 0(%r2), 254
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison near the high end of the CLI range, using sign
; extension. This cannot use CLI.
define double @f11(double %a, double %b, i8 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check signed comparison above the high end of the CLI range, using zero
; extension. The condition is always true.
define double @f12(double %a, double %b, i8 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check tests for nonnegative values.
define double @f13(double %a, double %b, i8 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: jl
; CHECK: br %r14
; ...and another form
define double @f14(double %a, double %b, i8 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: jl
; CHECK: br %r14
; Check tests for negative values.
define double @f15(double %a, double %b, i8 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: jh
; CHECK: br %r14
; ...and another form
define double @f16(double %a, double %b, i8 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the low end of the CLI range, using zero
; extension.
define double @f1(double %a, double %b, i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cli 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the low end of the CLI range, using sign
; extension.
define double @f2(double %a, double %b, i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cli 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the high end of the CLI range, using zero
; extension.
define double @f3(double %a, double %b, i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cli 0(%r2), 254
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison near the high end of the CLI range, using sign
; extension.
define double @f4(double %a, double %b, i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cli 0(%r2), 254
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison above the high end of the CLI range, using zero
; extension. The condition is always true.
define double @f5(double %a, double %b, i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; unlikely to occur in practice, we don't bother optimizing the second case,
; and simply ignore CLI for this range. First check the low end of the range.
define double @f6(double %a, double %b, i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; ...and then the high end.
define double @f7(double %a, double %b, i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check signed comparison near the low end of the CLI range, using zero
; extension. This is equivalent to unsigned comparison.
define double @f8(double %a, double %b, i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cli 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check signed comparison near the low end of the CLI range, using sign
; extension. This cannot use CLI.
define double @f9(double %a, double %b, i8 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check signed comparison near the high end of the CLI range, using zero
; extension. This is equivalent to unsigned comparison.
define double @f10(double %a, double %b, i8 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cli 0(%r2), 254
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison near the high end of the CLI range, using sign
; extension. This cannot use CLI.
define double @f11(double %a, double %b, i8 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check signed comparison above the high end of the CLI range, using zero
; extension. The condition is always true.
define double @f12(double %a, double %b, i8 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i8 *%ptr
; Check tests for nonnegative values.
define double @f13(double %a, double %b, i8 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: jl
; CHECK: br %r14
; ...and another form
define double @f14(double %a, double %b, i8 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: cli 0(%r2), 128
; CHECK-NEXT: jl
; CHECK: br %r14
; Check tests for negative values.
define double @f15(double %a, double %b, i8 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: jh
; CHECK: br %r14
; ...and another form
define double @f16(double %a, double %b, i8 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: cli 0(%r2), 127
; CHECK-NEXT: jh
; CHECK: br %r14
; Check comparisons with 0.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: chhsi 0(%r2), 0
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check comparisons with 1.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: chhsi 0(%r2), 1
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check a value near the high end of the signed 16-bit range.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: chhsi 0(%r2), 32766
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check comparisons with -1.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: chhsi 0(%r2), -1
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check a value near the low end of the 16-bit signed range.
define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: chhsi 0(%r2), -32766
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the CHHSI range.
define double @f6(double %a, double %b, i16 %i1, i16 *%base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: chhsi 4094(%r3), 0
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next halfword up, which needs separate address logic,
define double @f7(double %a, double %b, i16 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: aghi %r2, 4096
; CHECK: chhsi 0(%r2), 0
; CHECK-NEXT: jl
; Check negative offsets, which also need separate address logic.
define double @f8(double %a, double %b, i16 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r2, -2
; CHECK: chhsi 0(%r2), 0
; CHECK-NEXT: jl
; Check that CHHSI does not allow indices.
define double @f9(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agr {{%r2, %r3|%r3, %r2}}
; CHECK: chhsi 0({{%r[23]}}), 0
; CHECK-NEXT: jl
; Check a value near the low end of the unsigned 16-bit range.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: ldr %f0, %f2
; Check a value near the high end of the unsigned 16-bit range.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 65534
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the high end of the CLHHSI range.
define double @f3(double %a, double %b, i16 %i1, i16 *%base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clhhsi 4094(%r3), 1
; CHECK-NEXT: jh
; CHECK: ldr %f0, %f2
; Check the next halfword up, which needs separate address logic,
define double @f4(double %a, double %b, i16 *%base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: aghi %r2, 4096
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; Check negative offsets, which also need separate address logic.
define double @f5(double %a, double %b, i16 *%base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: aghi %r2, -2
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; Check that CLHHSI does not allow indices.
define double @f6(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agr {{%r2, %r3|%r3, %r2}}
; CHECK: clhhsi 0({{%r[23]}}), 1
; CHECK-NEXT: jh
; Check the low end of the unsigned 16-bit range.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the high end of the unsigned 16-bit range.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the low end of the signed 16-bit range.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clhhsi 0(%r2), 32768
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the high end of the signed 16-bit range.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clhhsi 0(%r2), 32767
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the low end of the unsigned 16-bit range.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the high end of the unsigned 16-bit range.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the low end of the signed 16-bit range.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clhhsi 0(%r2), 32768
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the high end of the signed 16-bit range.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clhhsi 0(%r2), 32767
; CHECK-NEXT: jlh
; CHECK: ldr %f0, %f2
; Check the low end of the 16-bit unsigned range, with zero extension.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the 16-bit unsigned range, with zero extension.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value up, with zero extension. The condition is always false.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with -1, with zero extension.
; This condition is also always false.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with 0, using sign extension.
define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the signed 16-bit range, using sign extension.
define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: clhhsi 0(%r2), 32767
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value up, using sign extension.
; The condition is always false.
define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with -1, using sign extension.
define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: je
; CHECK: br %r14
; Check the low end of the signed 16-bit range, using sign extension.
define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: clhhsi 0(%r2), 32768
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value down, using sign extension.
; The condition is always false.
define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check the low end of the 16-bit unsigned range, with zero extension.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the high end of the 16-bit unsigned range, with zero extension.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value up, with zero extension. The condition is always false.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with -1, with zero extension.
; This condition is also always false.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with 0, using sign extension.
define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the high end of the signed 16-bit range, using sign extension.
define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: clhhsi 0(%r2), 32767
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value up, using sign extension.
; The condition is always false.
define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with -1, using sign extension.
define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the low end of the signed 16-bit range, using sign extension.
define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: clhhsi 0(%r2), 32768
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value down, using sign extension.
; The condition is always false.
define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check the low end of the 16-bit unsigned range, with zero extension.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the 16-bit unsigned range, with zero extension.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value up, with zero extension. The condition is always false.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with -1, with zero extension.
; This condition is also always false.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with 0, using sign extension.
define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: je
; CHECK: br %r14
; Check the high end of the signed 16-bit range, using sign extension.
define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: clhhsi 0(%r2), 32767
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value up, using sign extension.
; The condition is always false.
define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with -1, using sign extension.
define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: je
; CHECK: br %r14
; Check the low end of the signed 16-bit range, using sign extension.
define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: clhhsi 0(%r2), 32768
; CHECK-NEXT: je
; CHECK: br %r14
; Check the next value down, using sign extension.
; The condition is always false.
define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check the low end of the 16-bit unsigned range, with zero extension.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the high end of the 16-bit unsigned range, with zero extension.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value up, with zero extension. The condition is always false.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with -1, with zero extension.
; This condition is also always false.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with 0, using sign extension.
define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: clhhsi 0(%r2), 0
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the high end of the signed 16-bit range, using sign extension.
define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: clhhsi 0(%r2), 32767
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value up, using sign extension.
; The condition is always false.
define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check comparisons with -1, using sign extension.
define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clhhsi 0(%r2), 65535
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the low end of the signed 16-bit range, using sign extension.
define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: clhhsi 0(%r2), 32768
; CHECK-NEXT: jlh
; CHECK: br %r14
; Check the next value down, using sign extension.
; The condition is always false.
define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check unsigned comparison near the low end of the CLHHSI range, using zero
; extension.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the low end of the CLHHSI range, using sign
; extension.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the high end of the CLHHSI range, using zero
; extension.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clhhsi 0(%r2), 65534
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison near the high end of the CLHHSI range, using sign
; extension.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clhhsi 0(%r2), 65534
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison above the high end of the CLHHSI range, using zero
; extension. The condition is always true.
define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; and simply ignore CLHHSI for this range. First check the low end of the
; range.
define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; ...and then the high end.
define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check signed comparison near the low end of the CLHHSI range, using zero
; extension. This is equivalent to unsigned comparison.
define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check signed comparison near the low end of the CLHHSI range, using sign
; extension. This should use CHHSI instead.
define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: chhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check signed comparison near the high end of the CLHHSI range, using zero
; extension. This is equivalent to unsigned comparison.
define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: clhhsi 0(%r2), 65534
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison near the high end of the CLHHSI range, using sign
; extension. This should use CHHSI instead.
define double @f11(double %a, double %b, i16 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: chhsi 0(%r2), -2
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison above the high end of the CLHHSI range, using zero
; extension. The condition is always true.
define double @f12(double %a, double %b, i16 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i16 *%ptr
; Check signed comparison near the high end of the CHHSI range, using sign
; extension.
define double @f13(double %a, double %b, i16 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: chhsi 0(%r2), 32766
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison above the high end of the CHHSI range, using sign
; extension. This condition is always true.
define double @f14(double %a, double %b, i16 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: chhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check signed comparison near the low end of the CHHSI range, using sign
; extension.
define double @f15(double %a, double %b, i16 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: chhsi 0(%r2), -32767
; CHECK-NEXT: jh
; CHECK: br %r14
; Check signed comparison below the low end of the CHHSI range, using sign
; extension. This condition is always true.
define double @f16(double %a, double %b, i16 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK-NOT: chhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check unsigned comparison near the low end of the CLHHSI range, using zero
; extension.
define double @f1(double %a, double %b, i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the low end of the CLHHSI range, using sign
; extension.
define double @f2(double %a, double %b, i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check unsigned comparison near the high end of the CLHHSI range, using zero
; extension.
define double @f3(double %a, double %b, i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clhhsi 0(%r2), 65534
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison near the high end of the CLHHSI range, using sign
; extension.
define double @f4(double %a, double %b, i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clhhsi 0(%r2), 65534
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison above the high end of the CLHHSI range, using zero
; extension. The condition is always true.
define double @f5(double %a, double %b, i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; and simply ignore CLHHSI for this range. First check the low end of the
; range.
define double @f6(double %a, double %b, i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; ...and then the high end.
define double @f7(double %a, double %b, i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: clhhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check signed comparison near the low end of the CLHHSI range, using zero
; extension. This is equivalent to unsigned comparison.
define double @f8(double %a, double %b, i16 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: clhhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check signed comparison near the low end of the CLHHSI range, using sign
; extension. This should use CHHSI instead.
define double @f9(double %a, double %b, i16 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: chhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: br %r14
; Check signed comparison near the high end of the CLHHSI range, using zero
; extension. This is equivalent to unsigned comparison.
define double @f10(double %a, double %b, i16 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: clhhsi 0(%r2), 65534
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison near the high end of the CLHHSI range, using sign
; extension. This should use CHHSI instead.
define double @f11(double %a, double %b, i16 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: chhsi 0(%r2), -2
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison above the high end of the CLHHSI range, using zero
; extension. The condition is always true.
define double @f12(double %a, double %b, i16 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: cli
; CHECK: br %r14
%val = load i16 *%ptr
; Check signed comparison near the high end of the CHHSI range, using sign
; extension.
define double @f13(double %a, double %b, i16 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: chhsi 0(%r2), 32766
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison above the high end of the CHHSI range, using sign
; extension. This condition is always true.
define double @f14(double %a, double %b, i16 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: chhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check signed comparison near the low end of the CHHSI range, using sign
; extension.
define double @f15(double %a, double %b, i16 *%ptr) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: chhsi 0(%r2), -32767
; CHECK-NEXT: jh
; CHECK: br %r14
; Check signed comparison below the low end of the CHHSI range, using sign
; extension. This condition is always true.
define double @f16(double %a, double %b, i16 *%ptr) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK-NOT: chhsi
; CHECK: br %r14
%val = load i16 *%ptr
; Check ordered comparisons with 0.
define double @f1(double %a, double %b, i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: chsi 0(%r2), 0
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check ordered comparisons with 1.
define double @f2(double %a, double %b, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: chsi 0(%r2), 1
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check ordered comparisons with the high end of the signed 16-bit range.
define double @f3(double %a, double %b, i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: chsi 0(%r2), 32767
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value up, which can't use CHSI.
define double @f4(double %a, double %b, i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: chsi
; CHECK: br %r14
%val = load i32 *%ptr
; Check ordered comparisons with -1.
define double @f5(double %a, double %b, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: chsi 0(%r2), -1
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check ordered comparisons with the low end of the 16-bit signed range.
define double @f6(double %a, double %b, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: chsi 0(%r2), -32768
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value down, which can't use CHSI.
define double @f7(double %a, double %b, i32 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: chsi
; CHECK: br %r14
%val = load i32 *%ptr
; Check equality comparisons with 0.
define double @f8(double %a, double %b, i32 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: chsi 0(%r2), 0
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check equality comparisons with 1.
define double @f9(double %a, double %b, i32 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: chsi 0(%r2), 1
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check equality comparisons with the high end of the signed 16-bit range.
define double @f10(double %a, double %b, i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: chsi 0(%r2), 32767
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value up, which can't use CHSI.
define double @f11(double %a, double %b, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: chsi
; CHECK: br %r14
%val = load i32 *%ptr
; Check equality comparisons with -1.
define double @f12(double %a, double %b, i32 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: chsi 0(%r2), -1
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check equality comparisons with the low end of the 16-bit signed range.
define double @f13(double %a, double %b, i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: chsi 0(%r2), -32768
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value down, which should be treated as a positive value.
define double @f14(double %a, double %b, i32 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: chsi
; CHECK: br %r14
%val = load i32 *%ptr
; Check the high end of the CHSI range.
define double @f15(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: chsi 4092(%r3), 0
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next word up, which needs separate address logic,
define double @f16(double %a, double %b, i32 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: aghi %r2, 4096
; CHECK: chsi 0(%r2), 0
; CHECK-NEXT: jl
; Check negative offsets, which also need separate address logic.
define double @f17(double %a, double %b, i32 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: aghi %r2, -4
; CHECK: chsi 0(%r2), 0
; CHECK-NEXT: jl
; Check that CHSI does not allow indices.
define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: agr {{%r2, %r3|%r3, %r2}}
; CHECK: chsi 0({{%r[23]}}), 0
; CHECK-NEXT: jl
; Check ordered comparisons with a constant near the low end of the unsigned
; 16-bit range.
define double @f1(double %a, double %b, i32 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clfhsi 0(%r2), 1
; CHECK-NEXT: jh
; CHECK: ldr %f0, %f2
; Check ordered comparisons with the high end of the unsigned 16-bit range.
define double @f2(double %a, double %b, i32 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clfhsi 0(%r2), 65535
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value up, which can't use CLFHSI.
define double @f3(double %a, double %b, i32 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: clfhsi
; CHECK: br %r14
%val = load i32 *%ptr
; Check equality comparisons with 32768, the lowest value for which
; we prefer CLFHSI to CHSI.
define double @f4(double %a, double %b, i32 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clfhsi 0(%r2), 32768
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check equality comparisons with the high end of the unsigned 16-bit range.
define double @f5(double %a, double %b, i32 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: clfhsi 0(%r2), 65535
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value up, which can't use CLFHSI.
define double @f6(double %a, double %b, i32 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: clfhsi
; CHECK: br %r14
%val = load i32 *%ptr
; Check the high end of the CLFHSI range.
define double @f7(double %a, double %b, i32 %i1, i32 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: clfhsi 4092(%r3), 1
; CHECK-NEXT: jh
; CHECK: ldr %f0, %f2
; Check the next word up, which needs separate address logic,
define double @f8(double %a, double %b, i32 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r2, 4096
; CHECK: clfhsi 0(%r2), 1
; CHECK-NEXT: jh
; Check negative offsets, which also need separate address logic.
define double @f9(double %a, double %b, i32 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: aghi %r2, -4
; CHECK: clfhsi 0(%r2), 1
; CHECK-NEXT: jh
; Check that CLFHSI does not allow indices.
define double @f10(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agr {{%r2, %r3|%r3, %r2}}
; CHECK: clfhsi 0({{%r[23]}}), 1
; CHECK-NEXT: jh
; Check ordered comparisons with 0.
define double @f1(double %a, double %b, i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cghsi 0(%r2), 0
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check ordered comparisons with 1.
define double @f2(double %a, double %b, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cghsi 0(%r2), 1
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check ordered comparisons with the high end of the signed 16-bit range.
define double @f3(double %a, double %b, i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cghsi 0(%r2), 32767
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value up, which can't use CGHSI.
define double @f4(double %a, double %b, i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: cghsi
; CHECK: br %r14
%val = load i64 *%ptr
; Check ordered comparisons with -1.
define double @f5(double %a, double %b, i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cghsi 0(%r2), -1
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check ordered comparisons with the low end of the 16-bit signed range.
define double @f6(double %a, double %b, i64 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cghsi 0(%r2), -32768
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value down, which should be treated as a positive value.
define double @f7(double %a, double %b, i64 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: cghsi
; CHECK: br %r14
%val = load i64 *%ptr
; Check equality comparisons with 0.
define double @f8(double %a, double %b, i64 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cghsi 0(%r2), 0
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check equality comparisons with 1.
define double @f9(double %a, double %b, i64 *%ptr) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cghsi 0(%r2), 1
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check equality comparisons with the high end of the signed 16-bit range.
define double @f10(double %a, double %b, i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: cghsi 0(%r2), 32767
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value up, which can't use CGHSI.
define double @f11(double %a, double %b, i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: cghsi
; CHECK: br %r14
%val = load i64 *%ptr
; Check equality comparisons with -1.
define double @f12(double %a, double %b, i64 *%ptr) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: cghsi 0(%r2), -1
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check equality comparisons with the low end of the 16-bit signed range.
define double @f13(double %a, double %b, i64 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: cghsi 0(%r2), -32768
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value down, which should be treated as a positive value.
define double @f14(double %a, double %b, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-NOT: cghsi
; CHECK: br %r14
%val = load i64 *%ptr
; Check the high end of the CGHSI range.
define double @f15(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: cghsi 4088(%r3), 0
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next doubleword up, which needs separate address logic,
define double @f16(double %a, double %b, i64 *%base) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: aghi %r2, 4096
; CHECK: cghsi 0(%r2), 0
; CHECK-NEXT: jl
; Check negative offsets, which also need separate address logic.
define double @f17(double %a, double %b, i64 *%base) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: aghi %r2, -8
; CHECK: cghsi 0(%r2), 0
; CHECK-NEXT: jl
; Check that CGHSI does not allow indices.
define double @f18(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: agr {{%r2, %r3|%r3, %r2}}
; CHECK: cghsi 0({{%r[23]}}), 0
; CHECK-NEXT: jl
; Check ordered comparisons with a constant near the low end of the unsigned
; 16-bit range.
define double @f1(double %a, double %b, i64 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clghsi 0(%r2), 2
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check ordered comparisons with the high end of the unsigned 16-bit range.
define double @f2(double %a, double %b, i64 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clghsi 0(%r2), 65535
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next value up, which can't use CLGHSI.
define double @f3(double %a, double %b, i64 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: clghsi
; CHECK: br %r14
%val = load i64 *%ptr
; Check equality comparisons with 32768, the lowest value for which
; we prefer CLGHSI to CGHSI.
define double @f4(double %a, double %b, i64 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clghsi 0(%r2), 32768
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check equality comparisons with the high end of the unsigned 16-bit range.
define double @f5(double %a, double %b, i64 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: clghsi 0(%r2), 65535
; CHECK-NEXT: je
; CHECK: ldr %f0, %f2
; Check the next value up, which can't use CLGHSI.
define double @f6(double %a, double %b, i64 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: clghsi
; CHECK: br %r14
%val = load i64 *%ptr
; Check the high end of the CLGHSI range.
define double @f7(double %a, double %b, i64 %i1, i64 *%base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: clghsi 4088(%r3), 2
; CHECK-NEXT: jl
; CHECK: ldr %f0, %f2
; Check the next doubleword up, which needs separate address logic,
define double @f8(double %a, double %b, i64 *%base) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r2, 4096
; CHECK: clghsi 0(%r2), 2
; CHECK-NEXT: jl
; Check negative offsets, which also need separate address logic.
define double @f9(double %a, double %b, i64 *%base) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: aghi %r2, -8
; CHECK: clghsi 0(%r2), 2
; CHECK-NEXT: jl
; Check that CLGHSI does not allow indices.
define double @f10(double %a, double %b, i64 %base, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agr {{%r2, %r3|%r3, %r2}}
; CHECK: clghsi 0({{%r[23]}}), 2
; CHECK-NEXT: jl
; Check signed comparison.
define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: chrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison, which cannot use CHRL.
define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: chrl
; CHECK: br %r14
entry:
; Check equality.
define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: chrl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
; Check inequality.
define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: chrl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
; Repeat f1 with an unaligned address.
define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
; CHECK: ch %r2, 0([[REG]])
; CHECK-NEXT: jl
; Check unsigned comparison.
define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clhrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison.
define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: clhrl
; CHECK: br %r14
entry:
; Check equality.
define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clhrl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
; Check inequality.
define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clhrl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
; Repeat f1 with an unaligned address.
define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
; CHECK: llh [[VAL:%r[0-5]]], 0([[REG]])
; CHECK: clr %r2, [[VAL]]
; Check signed comparisons.
define i32 @f1(i32 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: crl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparisons.
define i32 @f2(i32 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check equality, which can use CRL or CLRL.
define i32 @f3(i32 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: c{{l?}}rl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
; ...likewise inequality.
define i32 @f4(i32 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: c{{l?}}rl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
; Repeat f1 with an unaligned address.
define i32 @f5(i32 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: larl [[REG:%r[0-5]]], h
; CHECK: c %r2, 0([[REG]])
; CHECK-NEXT: jl
; Repeat f2 with an unaligned address.
define i32 @f6(i32 %src1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: larl [[REG:%r[0-5]]], h
; CHECK: cl %r2, 0([[REG]])
; CHECK-NEXT: jl
; Check signed comparison.
define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cghrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison, which cannot use CHRL.
define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: cghrl
; CHECK: br %r14
entry:
; Check equality.
define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cghrl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
; Check inequality.
define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cghrl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
; Repeat f1 with an unaligned address.
define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
; CHECK: cgh %r2, 0([[REG]])
; CHECK-NEXT: jl
; Check unsigned comparison.
define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clghrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison.
define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: clghrl
; CHECK: br %r14
entry:
; Check equality.
define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clghrl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
; Check inequality.
define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clghrl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
; Repeat f1 with an unaligned address.
define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
; CHECK: llgh [[VAL:%r[0-5]]], 0([[REG]])
; CHECK: clgr %r2, [[VAL]]
; Check signed comparison.
define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgfrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparison, which cannot use CHRL.
define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: cgfrl
; CHECK: br %r14
entry:
; Check equality.
define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cgfrl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
; Check inequality.
define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cgfrl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
; Repeat f1 with an unaligned address.
define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: larl [[REG:%r[0-5]]], h
; CHECK: cgf %r2, 0([[REG]])
; CHECK-NEXT: jl
; Check unsigned comparison.
define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clgfrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check signed comparison.
define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: clgfrl
; CHECK: br %r14
entry:
; Check equality.
define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: clgfrl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
; Check inequality.
define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: clgfrl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
; Repeat f1 with an unaligned address.
define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: larl [[REG:%r[0-5]]], h
; CHECK: clgf %r2, 0([[REG]])
; CHECK-NEXT: jl
; Check signed comparisons.
define i64 @f1(i64 %src1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cgrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check unsigned comparisons.
define i64 @f2(i64 %src1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: clgrl %r2, g
; CHECK-NEXT: jl
; CHECK: br %r14
; Check equality, which can use CRL or CLRL.
define i64 @f3(i64 %src1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: c{{l?}}grl %r2, g
; CHECK-NEXT: je
; CHECK: br %r14
; ...likewise inequality.
define i64 @f4(i64 %src1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: c{{l?}}grl %r2, g
; CHECK-NEXT: jlh
; CHECK: br %r14
; Repeat f1 with an unaligned address.
define i64 @f5(i64 %src1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: larl [[REG:%r[0-5]]], h
; CHECK: cg %r2, 0([[REG]])
; CHECK-NEXT: jl
; Check 0.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhi %r2, 0
; CHECK: br %r14
ret i32 0
; Check the high end of the LHI range.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhi %r2, 32767
; CHECK: br %r14
ret i32 32767
; Check the next value up, which must use LLILL instead.
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llill %r2, 32768
; CHECK: br %r14
ret i32 32768
; Check the high end of the LLILL range.
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llill %r2, 65535
; CHECK: br %r14
ret i32 65535
; Check the first useful LLILH value, which is the next one up.
define i32 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llilh %r2, 1
; CHECK: br %r14
ret i32 65536
; Check the first useful IILF value, which is the next one up again.
define i32 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: iilf %r2, 65537
; CHECK: br %r14
ret i32 65537
; Check the high end of the LLILH range.
define i32 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llilh %r2, 65535
; CHECK: br %r14
ret i32 -65536
; Check the next value up, which must use IILF.
define i32 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: iilf %r2, 4294901761
; CHECK: br %r14
ret i32 -65535
; Check the highest useful IILF value, 0xffff7fff
define i32 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: iilf %r2, 4294934527
; CHECK: br %r14
ret i32 -32769
; Check the next value up, which should use LHI.
define i32 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lhi %r2, -32768
; CHECK: br %r14
ret i32 -32768
; Check -1.
define i32 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: lhi %r2, -1
; CHECK: br %r14
ret i32 -1
; Check that constant loads are rematerialized.
define i32 @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-DAG: lhi %r2, 42
; CHECK-DAG: llill %r3, 32768
; CHECK-DAG: llilh %r4, 1
; Check 0.
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lghi %r2, 0
; CHECK-NEXT: br %r14
ret i64 0
; Check the high end of the LGHI range.
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lghi %r2, 32767
; CHECK-NEXT: br %r14
ret i64 32767
; Check the next value up, which must use LLILL instead.
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llill %r2, 32768
; CHECK-NEXT: br %r14
ret i64 32768
; Check the high end of the LLILL range.
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llill %r2, 65535
; CHECK-NEXT: br %r14
ret i64 65535
; Check the first useful LLILH value, which is the next one up.
define i64 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llilh %r2, 1
; CHECK-NEXT: br %r14
ret i64 65536
; Check the first useful LGFI value, which is the next one up again.
define i64 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgfi %r2, 65537
; CHECK-NEXT: br %r14
ret i64 65537
; Check the high end of the LGFI range.
define i64 @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgfi %r2, 2147483647
; CHECK-NEXT: br %r14
ret i64 2147483647
; Check the next value up, which should use LLILH instead.
define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llilh %r2, 32768
; CHECK-NEXT: br %r14
ret i64 2147483648
; Check the next value up again, which should use LLILF.
define i64 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: llilf %r2, 2147483649
; CHECK-NEXT: br %r14
ret i64 2147483649
; Check the high end of the LLILH range.
define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llilh %r2, 65535
; CHECK-NEXT: br %r14
ret i64 4294901760
; Check the next value up, which must use LLILF.
define i64 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: llilf %r2, 4294901761
; CHECK-NEXT: br %r14
ret i64 4294901761
; Check the high end of the LLILF range.
define i64 @f12() {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: llilf %r2, 4294967295
; CHECK-NEXT: br %r14
ret i64 4294967295
; Check the lowest useful LLIHL value, which is the next one up.
define i64 @f13() {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: llihl %r2, 1
; CHECK-NEXT: br %r14
ret i64 4294967296
; Check the next value up, which must use a combination of two instructions.
define i64 @f14() {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: llihl %r2, 1
; CHECK-NEXT: oill %r2, 1
; CHECK-NEXT: br %r14
; Check the high end of the OILL range.
define i64 @f15() {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: llihl %r2, 1
; CHECK-NEXT: oill %r2, 65535
; CHECK-NEXT: br %r14
; Check the next value up, which should use OILH instead.
define i64 @f16() {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: llihl %r2, 1
; CHECK-NEXT: oilh %r2, 1
; CHECK-NEXT: br %r14
; Check the next value up again, which should use OILF.
define i64 @f17() {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: llihl %r2, 1
; CHECK-NEXT: oilf %r2, 65537
; CHECK-NEXT: br %r14
; Check the high end of the OILH range.
define i64 @f18() {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: llihl %r2, 1
; CHECK-NEXT: oilh %r2, 65535
; CHECK-NEXT: br %r14
; Check the high end of the OILF range.
define i64 @f19() {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: llihl %r2, 1
; CHECK-NEXT: oilf %r2, 4294967295
; CHECK-NEXT: br %r14
; Check the high end of the LLIHL range.
define i64 @f20() {
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: llihl %r2, 65535
; CHECK-NEXT: br %r14
ret i64 281470681743360
; Check the lowest useful LLIHH value, which is 1<<32 greater than the above.
define i64 @f21() {
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK: llihh %r2, 1
; CHECK-NEXT: br %r14
ret i64 281474976710656
; Check the lowest useful LLIHF value, which is 1<<32 greater again.
define i64 @f22() {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK: llihf %r2, 65537
; CHECK-NEXT: br %r14
ret i64 281479271677952
; Check the highest end of the LLIHH range.
define i64 @f23() {
-; CHECK: f23:
+; CHECK-LABEL: f23:
; CHECK: llihh %r2, 65535
; CHECK-NEXT: br %r14
ret i64 -281474976710656
; Check the next value up, which must use OILL too.
define i64 @f24() {
-; CHECK: f24:
+; CHECK-LABEL: f24:
; CHECK: llihh %r2, 65535
; CHECK-NEXT: oill %r2, 1
; CHECK-NEXT: br %r14
; Check the high end of the LLIHF range.
define i64 @f25() {
-; CHECK: f25:
+; CHECK-LABEL: f25:
; CHECK: llihf %r2, 4294967295
; CHECK-NEXT: br %r14
ret i64 -4294967296
; Check -1.
define i64 @f26() {
-; CHECK: f26:
+; CHECK-LABEL: f26:
; CHECK: lghi %r2, -1
; CHECK-NEXT: br %r14
ret i64 -1
; Check the low end of the LGHI range.
define i64 @f27() {
-; CHECK: f27:
+; CHECK-LABEL: f27:
; CHECK: lghi %r2, -32768
; CHECK-NEXT: br %r14
ret i64 -32768
; Check the next value down, which must use LGFI instead.
define i64 @f28() {
-; CHECK: f28:
+; CHECK-LABEL: f28:
; CHECK: lgfi %r2, -32769
; CHECK-NEXT: br %r14
ret i64 -32769
; Check the low end of the LGFI range.
define i64 @f29() {
-; CHECK: f29:
+; CHECK-LABEL: f29:
; CHECK: lgfi %r2, -2147483648
; CHECK-NEXT: br %r14
ret i64 -2147483648
; Check the next value down, which needs a two-instruction sequence.
define i64 @f30() {
-; CHECK: f30:
+; CHECK-LABEL: f30:
; CHECK: llihf %r2, 4294967295
; CHECK-NEXT: oilf %r2, 2147483647
; CHECK-NEXT: br %r14
; Check that constant loads are rematerialized.
define i64 @f31() {
-; CHECK: f31:
+; CHECK-LABEL: f31:
; CHECK-DAG: lghi %r2, 42
; CHECK-DAG: lgfi %r3, 65537
; CHECK-DAG: llilf %r4, 2147483649
; Check the low end of the unsigned range.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mvi 0(%r2), 0
; CHECK: br %r14
store i8 0, i8 *%ptr
; Check the high end of the signed range.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mvi 0(%r2), 127
; CHECK: br %r14
store i8 127, i8 *%ptr
; Check the next value up.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvi 0(%r2), 128
; CHECK: br %r14
store i8 -128, i8 *%ptr
; Check the high end of the unsigned range.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvi 0(%r2), 255
; CHECK: br %r14
store i8 255, i8 *%ptr
; Check -1.
define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvi 0(%r2), 255
; CHECK: br %r14
store i8 -1, i8 *%ptr
; Check the low end of the signed range.
define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mvi 0(%r2), 128
; CHECK: br %r14
store i8 -128, i8 *%ptr
; Check the next value down.
define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: mvi 0(%r2), 127
; CHECK: br %r14
store i8 -129, i8 *%ptr
; Check the high end of the MVI range.
define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: mvi 4095(%r2), 42
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4095
; Check the next byte up, which should use MVIY instead of MVI.
define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: mviy 4096(%r2), 42
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4096
; Check the high end of the MVIY range.
define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: mviy 524287(%r2), 42
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r2, 524288
; CHECK: mvi 0(%r2), 42
; CHECK: br %r14
; Check the high end of the negative MVIY range.
define void @f12(i8 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: mviy -1(%r2), 42
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the MVIY range.
define void @f13(i8 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: mviy -524288(%r2), 42
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f14(i8 *%src) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: agfi %r2, -524289
; CHECK: mvi 0(%r2), 42
; CHECK: br %r14
; Check that MVI does not allow an index
define void @f15(i64 %src, i64 %index) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: agr %r2, %r3
; CHECK: mvi 4095(%r2), 42
; CHECK: br %r14
; Check that MVIY does not allow an index
define void @f16(i64 %src, i64 %index) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: agr %r2, %r3
; CHECK: mviy 4096(%r2), 42
; CHECK: br %r14
; Check the low end of the unsigned range.
define void @f1(i16 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mvhhi 0(%r2), 0
; CHECK: br %r14
store i16 0, i16 *%ptr
; Check the high end of the signed range.
define void @f2(i16 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mvhhi 0(%r2), 32767
; CHECK: br %r14
store i16 32767, i16 *%ptr
; Check the next value up.
define void @f3(i16 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvhhi 0(%r2), -32768
; CHECK: br %r14
store i16 -32768, i16 *%ptr
; Check the high end of the unsigned range.
define void @f4(i16 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvhhi 0(%r2), -1
; CHECK: br %r14
store i16 65535, i16 *%ptr
; Check -1.
define void @f5(i16 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvhhi 0(%r2), -1
; CHECK: br %r14
store i16 -1, i16 *%ptr
; Check the low end of the signed range.
define void @f6(i16 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mvhhi 0(%r2), -32768
; CHECK: br %r14
store i16 -32768, i16 *%ptr
; Check the next value down.
define void @f7(i16 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: mvhhi 0(%r2), 32767
; CHECK: br %r14
store i16 -32769, i16 *%ptr
; Check the high end of the MVHHI range.
define void @f8(i16 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: mvhhi 4094(%r2), 42
; CHECK: br %r14
%ptr = getelementptr i16 *%a, i64 2047
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f9(i16 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: aghi %r2, 4096
; CHECK: mvhhi 0(%r2), 42
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define void @f10(i16 *%a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: aghi %r2, -2
; CHECK: mvhhi 0(%r2), 42
; CHECK: br %r14
; Check that MVHHI does not allow an index
define void @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agr %r2, %r3
; CHECK: mvhhi 0(%r2), 42
; CHECK: br %r14
; Check moves of zero.
define void @f1(i32 *%a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mvhi 0(%r2), 0
; CHECK: br %r14
store i32 0, i32 *%a
; Check the high end of the signed 16-bit range.
define void @f2(i32 *%a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mvhi 0(%r2), 32767
; CHECK: br %r14
store i32 32767, i32 *%a
; Check the next value up, which can't use MVHI.
define void @f3(i32 *%a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: mvhi
; CHECK: br %r14
store i32 32768, i32 *%a
; Check moves of -1.
define void @f4(i32 *%a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvhi 0(%r2), -1
; CHECK: br %r14
store i32 -1, i32 *%a
; Check the low end of the MVHI range.
define void @f5(i32 *%a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvhi 0(%r2), -32768
; CHECK: br %r14
store i32 -32768, i32 *%a
; Check the next value down, which can't use MVHI.
define void @f6(i32 *%a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: mvhi
; CHECK: br %r14
store i32 -32769, i32 *%a
; Check the high end of the MVHI range.
define void @f7(i32 *%a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: mvhi 4092(%r2), 42
; CHECK: br %r14
%ptr = getelementptr i32 *%a, i64 1023
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(i32 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r2, 4096
; CHECK: mvhi 0(%r2), 42
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define void @f9(i32 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: aghi %r2, -4
; CHECK: mvhi 0(%r2), 42
; CHECK: br %r14
; Check that MVHI does not allow an index
define void @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agr %r2, %r3
; CHECK: mvhi 0(%r2), 42
; CHECK: br %r14
; Check moves of zero.
define void @f1(i64 *%a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mvghi 0(%r2), 0
; CHECK: br %r14
store i64 0, i64 *%a
; Check the high end of the signed 16-bit range.
define void @f2(i64 *%a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mvghi 0(%r2), 32767
; CHECK: br %r14
store i64 32767, i64 *%a
; Check the next value up, which can't use MVGHI.
define void @f3(i64 *%a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: mvghi
; CHECK: br %r14
store i64 32768, i64 *%a
; Check moves of -1.
define void @f4(i64 *%a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvghi 0(%r2), -1
; CHECK: br %r14
store i64 -1, i64 *%a
; Check the low end of the MVGHI range.
define void @f5(i64 *%a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvghi 0(%r2), -32768
; CHECK: br %r14
store i64 -32768, i64 *%a
; Check the next value down, which can't use MVGHI.
define void @f6(i64 *%a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: mvghi
; CHECK: br %r14
store i64 -32769, i64 *%a
; Check the high end of the MVGHI range.
define void @f7(i64 *%a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: mvghi 4088(%r2), 42
; CHECK: br %r14
%ptr = getelementptr i64 *%a, i64 511
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(i64 *%a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: aghi %r2, 4096
; CHECK: mvghi 0(%r2), 42
; CHECK: br %r14
; Check negative displacements, which also need separate address logic.
define void @f9(i64 *%a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: aghi %r2, -8
; CHECK: mvghi 0(%r2), 42
; CHECK: br %r14
; Check that MVGHI does not allow an index
define void @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agr %r2, %r3
; CHECK: mvghi 0(%r2), 42
; CHECK: br %r14
; Test register extension, starting with an i32.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lbr %r2, %r2
; CHECK: br %r14
%byte = trunc i32 %a to i8
; ...and again with an i64.
define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lbr %r2, %r2
; CHECK: br %r14
%byte = trunc i64 %a to i8
; Check LB with no displacement.
define i32 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lb %r2, 0(%r2)
; CHECK: br %r14
%byte = load i8 *%src
; Check the high end of the LB range.
define i32 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lb %r2, 524287(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: lb %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LB range.
define i32 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lb %r2, -1(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the LB range.
define i32 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lb %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524289
; CHECK: lb %r2, 0(%r2)
; CHECK: br %r14
; Check that LB allows an index
define i32 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lb %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LBR. We want
; to use LB if possible.
define void @f10(i32 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lb {{%r[0-9]+}}, 16{{[37]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 *%ptr
; Test register extension, starting with an i32.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: llcr %r2, %r2
; CHECK: br %r14
%byte = trunc i32 %a to i8
; ...and again with an i64.
define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llcr %r2, %r2
; CHECK: br %r14
%byte = trunc i64 %a to i8
; Check ANDs that are equivalent to zero extension.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llcr %r2, %r2
; CHECK: br %r14
%ext = and i32 %a, 255
; Check LLC with no displacement.
define i32 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llc %r2, 0(%r2)
; CHECK: br %r14
%byte = load i8 *%src
; Check the high end of the LLC range.
define i32 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llc %r2, 524287(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, 524288
; CHECK: llc %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LLC range.
define i32 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llc %r2, -1(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the LLC range.
define i32 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llc %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524289
; CHECK: llc %r2, 0(%r2)
; CHECK: br %r14
; Check that LLC allows an index
define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llc %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LLCR. We want
; to use LLC if possible.
define void @f11(i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: llc {{%r[0-9]+}}, 16{{[37]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 *%ptr
; Test register extension, starting with an i32.
define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lgbr %r2, %r2
; CHECK: br %r14
%byte = trunc i32 %a to i8
; ...and again with an i64.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lgbr %r2, %r2
; CHECK: br %r14
%byte = trunc i64 %a to i8
; Check LGB with no displacement.
define i64 @f3(i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lgb %r2, 0(%r2)
; CHECK: br %r14
%byte = load i8 *%src
; Check the high end of the LGB range.
define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lgb %r2, 524287(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: lgb %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LGB range.
define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgb %r2, -1(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the LGB range.
define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgb %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524289
; CHECK: lgb %r2, 0(%r2)
; CHECK: br %r14
; Check that LGB allows an index
define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lgb %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LGBR. We want
; to use LGB if possible.
define void @f10(i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lgb {{%r[0-9]+}}, 167(%r15)
; CHECK: br %r14
%val0 = load volatile i64 *%ptr
; Test register extension, starting with an i32.
define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: llgcr %r2, %r2
; CHECK: br %r14
%byte = trunc i32 %a to i8
; ...and again with an i64.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llgcr %r2, %r2
; CHECK: br %r14
%byte = trunc i64 %a to i8
; Check ANDs that are equivalent to zero extension.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llgcr %r2, %r2
; CHECK: br %r14
%ext = and i64 %a, 255
; Check LLGC with no displacement.
define i64 @f4(i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llgc %r2, 0(%r2)
; CHECK: br %r14
%byte = load i8 *%src
; Check the high end of the LLGC range.
define i64 @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llgc %r2, 524287(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, 524288
; CHECK: llgc %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LLGC range.
define i64 @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llgc %r2, -1(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the LLGC range.
define i64 @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llgc %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524289
; CHECK: llgc %r2, 0(%r2)
; CHECK: br %r14
; Check that LLGC allows an index
define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llgc %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LLGCR. We want
; to use LLGC if possible.
define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: llgc {{%r[0-9]+}}, 167(%r15)
; CHECK: br %r14
%val0 = load volatile i64 *%ptr
; Test register extension, starting with an i32.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhr %r2, %r2
; CHECK: br %r14
%half = trunc i32 %a to i16
; ...and again with an i64.
define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lhr %r2, %r2
; CHECK: br %r14
%half = trunc i64 %a to i16
; Check the low end of the LH range.
define i32 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lh %r2, 0(%r2)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the LH range.
define i32 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lh %r2, 4094(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2047
; Check the next halfword up, which needs LHY rather than LH.
define i32 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lhy %r2, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2048
; Check the high end of the LHY range.
define i32 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lhy %r2, 524286(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r2, 524288
; CHECK: lh %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LHY range.
define i32 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lhy %r2, -2(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the LHY range.
define i32 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lhy %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f10(i16 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r2, -524290
; CHECK: lh %r2, 0(%r2)
; CHECK: br %r14
; Check that LH allows an index
define i32 @f11(i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: lh %r2, 4094(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that LH allows an index
define i32 @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: lhy %r2, 4096(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LHR. We want
; to use LH if possible.
define void @f13(i32 *%ptr) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: lh {{%r[0-9]+}}, 16{{[26]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 *%ptr
; Test register extension, starting with an i32.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: llhr %r2, %r2
; CHECK: br %r14
%half = trunc i32 %a to i16
; ...and again with an i64.
define i32 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llhr %r2, %r2
; CHECK: br %r14
%half = trunc i64 %a to i16
; Check ANDs that are equivalent to zero extension.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llhr %r2, %r2
; CHECK: br %r14
%ext = and i32 %a, 65535
; Check LLH with no displacement.
define i32 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llh %r2, 0(%r2)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the LLH range.
define i32 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llh %r2, 524286(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, 524288
; CHECK: llh %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LLH range.
define i32 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llh %r2, -2(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the LLH range.
define i32 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llh %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524290
; CHECK: llh %r2, 0(%r2)
; CHECK: br %r14
; Check that LLH allows an index
define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llh %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LLHR. We want
; to use LLH if possible.
define void @f11(i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: llh {{%r[0-9]+}}, 16{{[26]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 *%ptr
; Test register extension, starting with an i32.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lghr %r2, %r2
; CHECK: br %r14
%half = trunc i64 %a to i16
; ...and again with an i64.
define i64 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lghr %r2, %r2
; CHECK: br %r14
%half = trunc i32 %a to i16
; Check LGH with no displacement.
define i64 @f3(i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lgh %r2, 0(%r2)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the LGH range.
define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lgh %r2, 524286(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: lgh %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LGH range.
define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgh %r2, -2(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the LGH range.
define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgh %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524290
; CHECK: lgh %r2, 0(%r2)
; CHECK: br %r14
; Check that LGH allows an index.
define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lgh %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LGHR. We want
; to use LGH if possible.
define void @f10(i64 *%ptr) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lgh {{%r[0-9]+}}, 166(%r15)
; CHECK: br %r14
%val0 = load volatile i64 *%ptr
; Test register extension, starting with an i32.
define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: llghr %r2, %r2
; CHECK: br %r14
%half = trunc i32 %a to i16
; ...and again with an i64.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llghr %r2, %r2
; CHECK: br %r14
%half = trunc i64 %a to i16
; Check ANDs that are equivalent to zero extension.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llghr %r2, %r2
; CHECK: br %r14
%ext = and i64 %a, 65535
; Check LLGH with no displacement.
define i64 @f4(i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llgh %r2, 0(%r2)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the LLGH range.
define i64 @f5(i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llgh %r2, 524286(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, 524288
; CHECK: llgh %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LLGH range.
define i64 @f7(i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llgh %r2, -2(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the LLGH range.
define i64 @f8(i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llgh %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f9(i16 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524290
; CHECK: llgh %r2, 0(%r2)
; CHECK: br %r14
; Check that LLGH allows an index
define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llgh %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LLGHR. We want
; to use LLGH if possible.
define void @f11(i64 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: llgh {{%r[0-9]+}}, 166(%r15)
; CHECK: br %r14
%val0 = load volatile i64 *%ptr
; Test register extension, starting with an i32.
define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lgfr %r2, %r2
; CHECK: br %r14
%ext = sext i32 %a to i64
; ...and again with an i64.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lgfr %r2, %r2
; CHECK: br %r14
%word = trunc i64 %a to i32
; Check LGF with no displacement.
define i64 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lgf %r2, 0(%r2)
; CHECK: br %r14
%word = load i32 *%src
; Check the high end of the LGF range.
define i64 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lgf %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: lgf %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LGF range.
define i64 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgf %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the LGF range.
define i64 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgf %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524292
; CHECK: lgf %r2, 0(%r2)
; CHECK: br %r14
; Check that LGF allows an index.
define i64 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lgf %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LGFR. We want
; to use LGF if possible.
define void @f10(i64 *%ptr1, i32 *%ptr2) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 *%ptr2
; Test register extension, starting with an i32.
define i64 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: llgfr %r2, %r2
; CHECK: br %r14
%ext = zext i32 %a to i64
; ...and again with an i64.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llgfr %r2, %r2
; CHECK: br %r14
%word = trunc i64 %a to i32
; Check ANDs that are equivalent to zero extension.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: llgfr %r2, %r2
; CHECK: br %r14
%ext = and i64 %a, 4294967295
; Check LLGF with no displacement.
define i64 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llgf %r2, 0(%r2)
; CHECK: br %r14
%word = load i32 *%src
; Check the high end of the LLGF range.
define i64 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: llgf %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, 524288
; CHECK: llgf %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative LLGF range.
define i64 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: llgf %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the LLGF range.
define i64 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: llgf %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f9(i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524292
; CHECK: llgf %r2, 0(%r2)
; CHECK: br %r14
; Check that LLGF allows an index.
define i64 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: llgf %r2, 524287(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test a case where we spill the source of at least one LLGFR. We want
; to use LLGF if possible.
define void @f11(i64 *%ptr1, i32 *%ptr2) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: llgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
%val0 = load volatile i32 *%ptr2
; Test register division. The result is in the second of the two registers.
define void @f1(i32 *%dest, i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lgfr %r1, %r3
; CHECK: dsgfr %r0, %r4
; CHECK: st %r1, 0(%r2)
; Test register remainder. The result is in the first of the two registers.
define void @f2(i32 *%dest, i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lgfr %r1, %r3
; CHECK: dsgfr %r0, %r4
; CHECK: st %r0, 0(%r2)
; Test that division and remainder use a single instruction.
define i32 @f3(i32 %dummy, i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r2
; CHECK: lgfr %r3, %r3
; CHECK-NOT: %r2
; Check that the sign extension of the dividend is elided when the argument
; is already sign-extended.
define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgfr %r2, %r4
; CHECK-NOT: dsgfr
; Test that memory dividends are loaded using sign extension (LGF).
define i32 @f5(i32 %dummy, i32 *%src, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r2
; CHECK: lgf %r3, 0(%r3)
; CHECK-NOT: %r2
; Test memory division with no displacement.
define void @f6(i32 *%dest, i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgfr %r1, %r3
; CHECK: dsgf %r0, 0(%r4)
; CHECK: st %r1, 0(%r2)
; Test memory remainder with no displacement.
define void @f7(i32 *%dest, i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgfr %r1, %r3
; CHECK: dsgf %r0, 0(%r4)
; CHECK: st %r0, 0(%r2)
; Test both memory division and memory remainder.
define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: %r2
; CHECK: lgfr %r3, %r3
; CHECK-NOT: %r2
; Check the high end of the DSGF range.
define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: dsgf %r2, 524284(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r4, 524288
; CHECK: dsgf %r2, 0(%r4)
; CHECK: br %r14
; Check the high end of the negative aligned DSGF range.
define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: dsgf %r2, -4(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the DSGF range.
define i32 @f12(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: dsgf %r2, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f13(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: agfi %r4, -524292
; CHECK: dsgf %r2, 0(%r4)
; CHECK: br %r14
; Check that DSGF allows an index.
define i32 @f14(i32 %dummy, i32 %a, i64 %src, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: dsgf %r2, 524287(%r5,%r4)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Make sure that we still use DSGFR rather than DSGR in cases where
; a load and division cannot be combined.
define void @f15(i32 *%dest, i32 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: l [[B:%r[0-9]+]], 0(%r3)
; CHECK: brasl %r14, foo@PLT
; CHECK: lgfr %r1, %r2
; Check that divisions of spilled values can use DSGF rather than DSGFR.
define i32 @f16(i32 *%ptr0) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: brasl %r14, foo@PLT
; CHECK: dsgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
; Test register division. The result is in the second of the two registers.
define void @f1(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r3
; CHECK: {{llill|lhi}} %r2, 0
; CHECK-NOT: %r3
; Test register remainder. The result is in the first of the two registers.
define void @f2(i32 %dummy, i32 %a, i32 %b, i32 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r3
; CHECK: {{llill|lhi}} %r2, 0
; CHECK-NOT: %r3
; Test that division and remainder use a single instruction.
define i32 @f3(i32 %dummy1, i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r3
; CHECK: {{llill|lhi}} %r2, 0
; CHECK-NOT: %r3
; Test memory division with no displacement.
define void @f4(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r3
; CHECK: {{llill|lhi}} %r2, 0
; CHECK-NOT: %r3
; Test memory remainder with no displacement.
define void @f5(i32 %dummy, i32 %a, i32 *%src, i32 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r3
; CHECK: {{llill|lhi}} %r2, 0
; CHECK-NOT: %r3
; Test both memory division and memory remainder.
define i32 @f6(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r3
; CHECK: {{llill|lhi}} %r2, 0
; CHECK-NOT: %r3
; Check the high end of the DL range.
define i32 @f7(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: dl %r2, 524284(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r4, 524288
; CHECK: dl %r2, 0(%r4)
; CHECK: br %r14
; Check the high end of the negative aligned DL range.
define i32 @f9(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: dl %r2, -4(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the DL range.
define i32 @f10(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: dl %r2, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f11(i32 %dummy, i32 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r4, -524292
; CHECK: dl %r2, 0(%r4)
; CHECK: br %r14
; Check that DL allows an index.
define i32 @f12(i32 %dummy, i32 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: dl %r2, 524287(%r5,%r4)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that divisions of spilled values can use DL rather than DLR.
define i32 @f13(i32 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: brasl %r14, foo@PLT
; CHECK: dl {{%r[0-9]+}}, 16{{[04]}}(%r15)
; CHECK: br %r14
; Test register division. The result is in the second of the two registers.
define void @f1(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgfr %r2, %r4
; CHECK: stg %r3, 0(%r5)
; Test register remainder. The result is in the first of the two registers.
define void @f2(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgfr %r2, %r4
; CHECK: stg %r2, 0(%r5)
; Test that division and remainder use a single instruction.
define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgfr %r2, %r4
; CHECK: ogr %r2, %r3
; Test register division when the dividend is zero rather than sign extended.
; We can't use dsgfr here
define void @f4(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: dsgfr
; CHECK: br %r14
%bext = zext i32 %b to i64
; ...likewise remainder.
define void @f5(i64 %dummy, i64 %a, i32 %b, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: dsgfr
; CHECK: br %r14
%bext = zext i32 %b to i64
; Test memory division with no displacement.
define void @f6(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgf %r2, 0(%r4)
; CHECK: stg %r3, 0(%r5)
; Test memory remainder with no displacement.
define void @f7(i64 %dummy, i64 %a, i32 *%src, i64 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgf %r2, 0(%r4)
; CHECK: stg %r2, 0(%r5)
; Test both memory division and memory remainder.
define i64 @f8(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgf %r2, 0(%r4)
; CHECK-NOT: {{dsgf|dsgfr}}
; Check the high end of the DSGF range.
define i64 @f9(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: dsgf %r2, 524284(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f10(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r4, 524288
; CHECK: dsgf %r2, 0(%r4)
; CHECK: br %r14
; Check the high end of the negative aligned DSGF range.
define i64 @f11(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: dsgf %r2, -4(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the DSGF range.
define i64 @f12(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: dsgf %r2, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f13(i64 %dummy, i64 %a, i32 *%src) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: agfi %r4, -524292
; CHECK: dsgf %r2, 0(%r4)
; CHECK: br %r14
; Check that DSGF allows an index.
define i64 @f14(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: dsgf %r2, 524287(%r5,%r4)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Make sure that we still use DSGFR rather than DSGR in cases where
; a load and division cannot be combined.
define void @f15(i64 *%dest, i32 *%src) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: l [[B:%r[0-9]+]], 0(%r3)
; CHECK: brasl %r14, foo@PLT
; CHECK: lgr %r1, %r2
; Testg register division. The result is in the second of the two registers.
define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgr %r2, %r4
; CHECK: stg %r3, 0(%r5)
; Testg register remainder. The result is in the first of the two registers.
define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgr %r2, %r4
; CHECK: stg %r2, 0(%r5)
; Testg that division and remainder use a single instruction.
define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgr %r2, %r4
; CHECK-NOT: dsgr
; Testg memory division with no displacement.
define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsg %r2, 0(%r4)
; CHECK: stg %r3, 0(%r5)
; Testg memory remainder with no displacement.
define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsg %r2, 0(%r4)
; CHECK: stg %r2, 0(%r5)
; Testg both memory division and memory remainder.
define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsg %r2, 0(%r4)
; CHECK-NOT: {{dsg|dsgr}}
; Check the high end of the DSG range.
define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: dsg %r2, 524280(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r4, 524288
; CHECK: dsg %r2, 0(%r4)
; CHECK: br %r14
; Check the high end of the negative aligned DSG range.
define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: dsg %r2, -8(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the DSG range.
define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: dsg %r2, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r4, -524296
; CHECK: dsg %r2, 0(%r4)
; CHECK: br %r14
; Check that DSG allows an index.
define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: dsg %r2, 524287(%r5,%r4)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that divisions of spilled values can use DSG rather than DSGR.
define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: brasl %r14, foo@PLT
; CHECK: dsg {{%r[0-9]+}}, 160(%r15)
; CHECK: br %r14
; Testg register division. The result is in the second of the two registers.
define void @f1(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r3
; CHECK: {{llill|lghi}} %r2, 0
; CHECK-NOT: %r3
; Testg register remainder. The result is in the first of the two registers.
define void @f2(i64 %dummy, i64 %a, i64 %b, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r3
; CHECK: {{llill|lghi}} %r2, 0
; CHECK-NOT: %r3
; Testg that division and remainder use a single instruction.
define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: %r3
; CHECK: {{llill|lghi}} %r2, 0
; CHECK-NOT: %r3
; Testg memory division with no displacement.
define void @f4(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: %r3
; CHECK: {{llill|lghi}} %r2, 0
; CHECK-NOT: %r3
; Testg memory remainder with no displacement.
define void @f5(i64 %dummy, i64 %a, i64 *%src, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NOT: %r3
; CHECK: {{llill|lghi}} %r2, 0
; CHECK-NOT: %r3
; Testg both memory division and memory remainder.
define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: %r3
; CHECK: {{llill|lghi}} %r2, 0
; CHECK-NOT: %r3
; Check the high end of the DLG range.
define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: dlg %r2, 524280(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r4, 524288
; CHECK: dlg %r2, 0(%r4)
; CHECK: br %r14
; Check the high end of the negative aligned DLG range.
define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: dlg %r2, -8(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the DLG range.
define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: dlg %r2, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f11(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r4, -524296
; CHECK: dlg %r2, 0(%r4)
; CHECK: br %r14
; Check that DLG allows an index.
define i64 @f12(i64 %dummy, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: dlg %r2, 524287(%r5,%r4)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that divisions of spilled values can use DLG rather than DLGR.
define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: brasl %r14, foo@PLT
; CHECK: dlg {{%r[0-9]+}}, 160(%r15)
; CHECK: br %r14
; Test 8-bit moves, which should get promoted to i32.
define i8 @f1(i8 %a, i8 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lr %r2, %r3
; CHECK: br %r14
ret i8 %b
; Test 16-bit moves, which again should get promoted to i32.
define i16 @f2(i16 %a, i16 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lr %r2, %r3
; CHECK: br %r14
ret i16 %b
; Test 32-bit moves.
define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lr %r2, %r3
; CHECK: br %r14
ret i32 %b
; Test 64-bit moves.
define i64 @f4(i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lgr %r2, %r3
; CHECK: br %r14
ret i64 %b
; Check the low end of the L range.
define i32 @f1(i32 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: l %r2, 0(%r2)
; CHECK: br %r14
%val = load i32 *%src
; Check the high end of the aligned L range.
define i32 @f2(i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: l %r2, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
; Check the next word up, which should use LY instead of L.
define i32 @f3(i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ly %r2, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
; Check the high end of the aligned LY range.
define i32 @f4(i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ly %r2, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f5(i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r2, 524288
; CHECK: l %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned LY range.
define i32 @f6(i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ly %r2, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the LY range.
define i32 @f7(i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: ly %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, -524292
; CHECK: l %r2, 0(%r2)
; CHECK: br %r14
; Check that L allows an index.
define i32 @f9(i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: l %r2, 4095({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that LY allows an index.
define i32 @f10(i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ly %r2, 4096({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check LG with no displacement.
define i64 @f1(i64 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lg %r2, 0(%r2)
; CHECK: br %r14
%val = load i64 *%src
; Check the high end of the aligned LG range.
define i64 @f2(i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lg %r2, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f3(i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: lg %r2, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned LG range.
define i64 @f4(i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lg %r2, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the LG range.
define i64 @f5(i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lg %r2, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f6(i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524296
; CHECK: lg %r2, 0(%r2)
; CHECK: br %r14
; Check that LG allows an index.
define i64 @f7(i64 %src, i64 %index) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lg %r2, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Test an i8 store, which should get converted into an i32 truncation.
define void @f1(i8 *%dst, i8 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stc %r3, 0(%r2)
; CHECK: br %r14
store i8 %val, i8 *%dst
; Test an i32 truncating store.
define void @f2(i8 *%dst, i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: stc %r3, 0(%r2)
; CHECK: br %r14
%trunc = trunc i32 %val to i8
; Test an i64 truncating store.
define void @f3(i8 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: stc %r3, 0(%r2)
; CHECK: br %r14
%trunc = trunc i64 %val to i8
; Check the high end of the STC range.
define void @f4(i8 *%dst, i8 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: stc %r3, 4095(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%dst, i64 4095
; Check the next byte up, which should use STCY instead of STC.
define void @f5(i8 *%dst, i8 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: stcy %r3, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%dst, i64 4096
; Check the high end of the STCY range.
define void @f6(i8 *%dst, i8 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: stcy %r3, 524287(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%dst, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f7(i8 *%dst, i8 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r2, 524288
; CHECK: stc %r3, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative STCY range.
define void @f8(i8 *%dst, i8 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: stcy %r3, -1(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%dst, i64 -1
; Check the low end of the STCY range.
define void @f9(i8 *%dst, i8 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: stcy %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i8 *%dst, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f10(i8 *%dst, i8 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r2, -524289
; CHECK: stc %r3, 0(%r2)
; CHECK: br %r14
; Check that STC allows an index.
define void @f11(i64 %dst, i64 %index, i8 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: stc %r4, 4095(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %dst, %index
; Check that STCY allows an index.
define void @f12(i64 %dst, i64 %index, i8 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: stcy %r4, 4096(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %dst, %index
; Test an i16 store, which should get converted into an i32 truncation.
define void @f1(i16 *%dst, i16 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sth %r3, 0(%r2)
; CHECK: br %r14
store i16 %val, i16 *%dst
; Test an i32 truncating store.
define void @f2(i16 *%dst, i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sth %r3, 0(%r2)
; CHECK: br %r14
%trunc = trunc i32 %val to i16
; Test an i64 truncating store.
define void @f3(i16 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sth %r3, 0(%r2)
; CHECK: br %r14
%trunc = trunc i64 %val to i16
; Check the high end of the STH range.
define void @f4(i16 *%dst, i16 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: sth %r3, 4094(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%dst, i64 2047
; Check the next halfword up, which should use STHY instead of STH.
define void @f5(i16 *%dst, i16 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sthy %r3, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%dst, i64 2048
; Check the high end of the aligned STHY range.
define void @f6(i16 *%dst, i16 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sthy %r3, 524286(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%dst, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f7(i16 *%dst, i16 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r2, 524288
; CHECK: sth %r3, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned STHY range.
define void @f8(i16 *%dst, i16 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sthy %r3, -2(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%dst, i64 -1
; Check the low end of the STHY range.
define void @f9(i16 *%dst, i16 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: sthy %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i16 *%dst, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f10(i16 *%dst, i16 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: agfi %r2, -524290
; CHECK: sth %r3, 0(%r2)
; CHECK: br %r14
; Check that STH allows an index.
define void @f11(i64 %dst, i64 %index, i16 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: sth %r4, 4094({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %dst, %index
; Check that STHY allows an index.
define void @f12(i64 %dst, i64 %index, i16 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: sthy %r4, 4096({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %dst, %index
; Test an i32 store.
define void @f1(i32 *%dst, i32 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: st %r3, 0(%r2)
; CHECK: br %r14
store i32 %val, i32 *%dst
; Check the high end of the aligned ST range.
define void @f3(i32 *%dst, i32 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: st %r3, 4092(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 1023
; Check the next word up, which should use STY instead of ST.
define void @f4(i32 *%dst, i32 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: sty %r3, 4096(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 1024
; Check the high end of the aligned STY range.
define void @f5(i32 *%dst, i32 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sty %r3, 524284(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i32 *%dst, i32 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, 524288
; CHECK: st %r3, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned STY range.
define void @f7(i32 *%dst, i32 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sty %r3, -4(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 -1
; Check the low end of the STY range.
define void @f8(i32 *%dst, i32 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sty %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i32 *%dst, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f9(i32 *%dst, i32 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r2, -524292
; CHECK: st %r3, 0(%r2)
; CHECK: br %r14
; Check that ST allows an index.
define void @f10(i64 %dst, i64 %index, i32 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: st %r4, 4095(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %dst, %index
; Check that STY allows an index.
define void @f11(i64 %dst, i64 %index, i32 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: sty %r4, 4096(%r3,%r2)
; CHECK: br %r14
%add1 = add i64 %dst, %index
; Check STG with no displacement.
define void @f1(i64 *%dst, i64 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stg %r3, 0(%r2)
; CHECK: br %r14
store i64 %val, i64 *%dst
; Check the high end of the aligned STG range.
define void @f2(i64 *%dst, i64 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: stg %r3, 524280(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f3(i64 *%dst, i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: agfi %r2, 524288
; CHECK: stg %r3, 0(%r2)
; CHECK: br %r14
; Check the high end of the negative aligned STG range.
define void @f4(i64 *%dst, i64 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: stg %r3, -8(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 -1
; Check the low end of the STG range.
define void @f5(i64 *%dst, i64 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: stg %r3, -524288(%r2)
; CHECK: br %r14
%ptr = getelementptr i64 *%dst, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i64 *%dst, i64 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r2, -524296
; CHECK: stg %r3, 0(%r2)
; CHECK: br %r14
; Check that STG allows an index.
define void @f7(i64 %dst, i64 %index, i64 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: stg %r4, 524287({{%r3,%r2|%r2,%r3}})
; CHECK: br %r14
%add1 = add i64 %dst, %index
; Check sign-extending loads from i16.
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lhrl %r2, gsrc16
; CHECK: br %r14
%val = load i16 *@gsrc16
; Check zero-extending loads from i16.
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llhrl %r2, gsrc16
; CHECK: br %r14
%val = load i16 *@gsrc16
; Check truncating 16-bit stores.
define void @f3(i32 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sthrl %r2, gdst16
; CHECK: br %r14
%half = trunc i32 %val to i16
; Check plain loads and stores.
define void @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lrl %r0, gsrc32
; CHECK: strl %r0, gdst32
; CHECK: br %r14
; Repeat f1 with an unaligned variable.
define i32 @f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
; CHECK: lh %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f2 with an unaligned variable.
define i32 @f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u
; CHECK: llh %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f3 with an unaligned variable.
define void @f7(i32 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgrl [[REG:%r[0-5]]], gdst16u
; CHECK: sth %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f4 with unaligned variables.
define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: larl [[REG:%r[0-5]]], gsrc32u
; CHECK: l [[VAL:%r[0-5]]], 0([[REG]])
; CHECK: larl [[REG:%r[0-5]]], gdst32u
; Check sign-extending loads from i16.
define i64 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lghrl %r2, gsrc16
; CHECK: br %r14
%val = load i16 *@gsrc16
; Check zero-extending loads from i16.
define i64 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: llghrl %r2, gsrc16
; CHECK: br %r14
%val = load i16 *@gsrc16
; Check sign-extending loads from i32.
define i64 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lgfrl %r2, gsrc32
; CHECK: br %r14
%val = load i32 *@gsrc32
; Check zero-extending loads from i32.
define i64 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: llgfrl %r2, gsrc32
; CHECK: br %r14
%val = load i32 *@gsrc32
; Check truncating 16-bit stores.
define void @f5(i64 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sthrl %r2, gdst16
; CHECK: br %r14
%half = trunc i64 %val to i16
; Check truncating 32-bit stores.
define void @f6(i64 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: strl %r2, gdst32
; CHECK: br %r14
%word = trunc i64 %val to i32
; Check plain loads and stores.
define void @f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgrl %r0, gsrc64
; CHECK: stgrl %r0, gdst64
; CHECK: br %r14
; Repeat f1 with an unaligned variable.
define i64 @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
; CHECK: lgh %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f2 with an unaligned variable.
define i64 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lgrl [[REG:%r[0-5]]], gsrc16u@GOT
; CHECK: llgh %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f3 with an unaligned variable.
define i64 @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: larl [[REG:%r[0-5]]], gsrc32u
; CHECK: lgf %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f4 with an unaligned variable.
define i64 @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: larl [[REG:%r[0-5]]], gsrc32u
; CHECK: llgf %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f5 with an unaligned variable.
define void @f12(i64 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: lgrl [[REG:%r[0-5]]], gdst16u@GOT
; CHECK: sth %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f6 with an unaligned variable.
define void @f13(i64 %val) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: larl [[REG:%r[0-5]]], gdst32u
; CHECK: st %r2, 0([[REG]])
; CHECK: br %r14
; Repeat f7 with unaligned variables.
define void @f14() {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: larl [[REG:%r[0-5]]], gsrc64u
; CHECK: lg [[VAL:%r[0-5]]], 0([[REG]])
; CHECK: larl [[REG:%r[0-5]]], gdst64u
; Check the low end of the MH range.
define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mh %r2, 0(%r3)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the aligned MH range.
define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mh %r2, 4094(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2047
; Check the next halfword up, which should use MHY instead of MH.
define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mhy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2048
; Check the high end of the aligned MHY range.
define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mhy %r2, 524286(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, 524288
; CHECK: mh %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned MHY range.
define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mhy %r2, -2(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the MHY range.
define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: mhy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524290
; CHECK: mh %r2, 0(%r3)
; CHECK: br %r14
; Check that MH allows an index.
define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: mh %r2, 4094({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that MHY allows an index.
define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: mhy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check MSR.
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: msr %r2, %r3
; CHECK: br %r14
%mul = mul i32 %a, %b
; Check the low end of the MS range.
define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ms %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned MS range.
define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ms %r2, 4092(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
; Check the next word up, which should use MSY instead of MS.
define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: msy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
; Check the high end of the aligned MSY range.
define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: msy %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: ms %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned MSY range.
define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: msy %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the MSY range.
define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: msy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: ms %r2, 0(%r3)
; CHECK: br %r14
; Check that MS allows an index.
define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ms %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that MSY allows an index.
define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: msy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that multiplications of spilled values can use MS rather than MSR.
define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK: ms %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check MSGFR.
define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: msgfr %r2, %r3
; CHECK: br %r14
%bext = sext i32 %b to i64
; Check MSGF with no displacement.
define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: msgf %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned MSGF range.
define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: msgf %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: msgf %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned MSGF range.
define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: msgf %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the MSGF range.
define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: msgf %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524292
; CHECK: msgf %r2, 0(%r3)
; CHECK: br %r14
; Check that MSGF allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: msgf %r2, 524284({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that multiplications of spilled values can use MSGF rather than MSGFR.
define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: msgf %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check MSGR.
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: msgr %r2, %r3
; CHECK: br %r14
%mul = mul i64 %a, %b
; Check MSG with no displacement.
define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: msg %r2, 0(%r3)
; CHECK: br %r14
%b = load i64 *%src
; Check the high end of the aligned MSG range.
define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: msg %r2, 524280(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: msg %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned MSG range.
define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: msg %r2, -8(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the MSG range.
define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: msg %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: msg %r2, 0(%r3)
; CHECK: br %r14
; Check that MSG allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: msg %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that multiplications of spilled values can use MSG rather than MSGR.
define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: msg %r2, 160(%r15)
; CHECK: br %r14
; Check multiplication by 2, which should use shifts.
define i32 @f1(i32 %a, i32 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sll %r2, 1
; CHECK: br %r14
%mul = mul i32 %a, 2
; Check multiplication by 3.
define i32 @f2(i32 %a, i32 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mhi %r2, 3
; CHECK: br %r14
%mul = mul i32 %a, 3
; Check the high end of the MHI range.
define i32 @f3(i32 %a, i32 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mhi %r2, 32767
; CHECK: br %r14
%mul = mul i32 %a, 32767
; Check the next value up, which should use shifts.
define i32 @f4(i32 %a, i32 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: sll %r2, 15
; CHECK: br %r14
%mul = mul i32 %a, 32768
; Check the next value up again, which can use MSFI.
define i32 @f5(i32 %a, i32 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: msfi %r2, 32769
; CHECK: br %r14
%mul = mul i32 %a, 32769
; Check the high end of the MSFI range.
define i32 @f6(i32 %a, i32 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: msfi %r2, 2147483647
; CHECK: br %r14
%mul = mul i32 %a, 2147483647
; Check the next value up, which should use shifts.
define i32 @f7(i32 %a, i32 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sll %r2, 31
; CHECK: br %r14
%mul = mul i32 %a, 2147483648
; Check the next value up again, which is treated as a negative value.
define i32 @f8(i32 %a, i32 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: msfi %r2, -2147483647
; CHECK: br %r14
%mul = mul i32 %a, 2147483649
; Check multiplication by -1, which is a negation.
define i32 @f9(i32 %a, i32 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lcr %r2, %r2
; CHECK: br %r14
%mul = mul i32 %a, -1
; Check multiplication by -2, which should use shifts.
define i32 @f10(i32 %a, i32 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: sll %r2, 1
; CHECK: lcr %r2, %r2
; CHECK: br %r14
; Check multiplication by -3.
define i32 @f11(i32 %a, i32 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: mhi %r2, -3
; CHECK: br %r14
%mul = mul i32 %a, -3
; Check the lowest useful MHI value.
define i32 @f12(i32 %a, i32 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: mhi %r2, -32767
; CHECK: br %r14
%mul = mul i32 %a, -32767
; Check the next value down, which should use shifts.
define i32 @f13(i32 %a, i32 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: sll %r2, 15
; CHECK: lcr %r2, %r2
; CHECK: br %r14
; Check the next value down again, which can use MSFI.
define i32 @f14(i32 %a, i32 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: msfi %r2, -32769
; CHECK: br %r14
%mul = mul i32 %a, -32769
; Check the lowest useful MSFI value.
define i32 @f15(i32 %a, i32 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: msfi %r2, -2147483647
; CHECK: br %r14
%mul = mul i32 %a, -2147483647
; Check the next value down, which should use shifts.
define i32 @f16(i32 %a, i32 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: sll %r2, 31
; CHECK-NOT: lcr
; CHECK: br %r14
; Check the next value down again, which is treated as a positive value.
define i32 @f17(i32 %a, i32 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: msfi %r2, 2147483647
; CHECK: br %r14
%mul = mul i32 %a, -2147483649
; Check multiplication by 2, which should use shifts.
define i64 @f1(i64 %a, i64 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sllg %r2, %r2, 1
; CHECK: br %r14
%mul = mul i64 %a, 2
; Check multiplication by 3.
define i64 @f2(i64 %a, i64 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mghi %r2, 3
; CHECK: br %r14
%mul = mul i64 %a, 3
; Check the high end of the MGHI range.
define i64 @f3(i64 %a, i64 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mghi %r2, 32767
; CHECK: br %r14
%mul = mul i64 %a, 32767
; Check the next value up, which should use shifts.
define i64 @f4(i64 %a, i64 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: sllg %r2, %r2, 15
; CHECK: br %r14
%mul = mul i64 %a, 32768
; Check the next value up again, which can use MSGFI.
define i64 @f5(i64 %a, i64 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: msgfi %r2, 32769
; CHECK: br %r14
%mul = mul i64 %a, 32769
; Check the high end of the MSGFI range.
define i64 @f6(i64 %a, i64 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: msgfi %r2, 2147483647
; CHECK: br %r14
%mul = mul i64 %a, 2147483647
; Check the next value up, which should use shifts.
define i64 @f7(i64 %a, i64 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sllg %r2, %r2, 31
; CHECK: br %r14
%mul = mul i64 %a, 2147483648
; Check the next value up again, which cannot use a constant multiplicatoin.
define i64 @f8(i64 %a, i64 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: msgfi
; CHECK: br %r14
%mul = mul i64 %a, 2147483649
; Check multiplication by -1, which is a negation.
define i64 @f9(i64 %a, i64 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: lcgr {{%r[0-5]}}, %r2
; CHECK: br %r14
%mul = mul i64 %a, -1
; Check multiplication by -2, which should use shifts.
define i64 @f10(i64 %a, i64 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 1
; CHECK: lcgr %r2, [[SHIFTED]]
; CHECK: br %r14
; Check multiplication by -3.
define i64 @f11(i64 %a, i64 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: mghi %r2, -3
; CHECK: br %r14
%mul = mul i64 %a, -3
; Check the lowest useful MGHI value.
define i64 @f12(i64 %a, i64 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: mghi %r2, -32767
; CHECK: br %r14
%mul = mul i64 %a, -32767
; Check the next value down, which should use shifts.
define i64 @f13(i64 %a, i64 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 15
; CHECK: lcgr %r2, [[SHIFTED]]
; CHECK: br %r14
; Check the next value down again, which can use MSGFI.
define i64 @f14(i64 %a, i64 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: msgfi %r2, -32769
; CHECK: br %r14
%mul = mul i64 %a, -32769
; Check the lowest useful MSGFI value.
define i64 @f15(i64 %a, i64 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: msgfi %r2, -2147483647
; CHECK: br %r14
%mul = mul i64 %a, -2147483647
; Check the next value down, which should use shifts.
define i64 @f16(i64 %a, i64 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: sllg [[SHIFTED:%r[0-5]]], %r2, 31
; CHECK: lcgr %r2, [[SHIFTED]]
; CHECK: br %r14
; Check the next value down again, which cannot use constant multiplication
define i64 @f17(i64 %a, i64 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK-NOT: msgfi
; CHECK: br %r14
%mul = mul i64 %a, -2147483649
; Check zero-extended multiplication in which only the high part is used.
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: msgr
; CHECK: br %r14
%ax = zext i32 %a to i64
; Check sign-extended multiplication in which only the high part is used.
define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: msgfr
; CHECK: br %r14
%ax = sext i32 %a to i64
; Check zero-extended multiplication in which the result is split into
; high and low halves.
define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: msgr
; CHECK: br %r14
%ax = zext i32 %a to i64
; Check sign-extended multiplication in which the result is split into
; high and low halves.
define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: msgfr
; CHECK: br %r14
%ax = sext i32 %a to i64
; Check zero-extended multiplication in which only the high part is used.
define i64 @f1(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: {{%r[234]}}
; CHECK: mlgr %r2, %r4
; CHECK: br %r14
; Check sign-extended multiplication in which only the high part is used.
; This needs a rather convoluted sequence.
define i64 @f2(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mlgr
; CHECK: agr
; CHECK: agr
; Check zero-extended multiplication in which only part of the high half
; is used.
define i64 @f3(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: {{%r[234]}}
; CHECK: mlgr %r2, %r4
; CHECK: srlg %r2, %r2, 3
; Check zero-extended multiplication in which the result is split into
; high and low halves.
define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: {{%r[234]}}
; CHECK: mlgr %r2, %r4
; CHECK: ogr %r2, %r3
; Check division by a constant, which should use multiplication instead.
define i64 @f5(i64 %dummy, i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mlgr %r2,
; CHECK: srlg %r2, %r2,
; CHECK: br %r14
; Check MLG with no displacement.
define i64 @f6(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: {{%r[234]}}
; CHECK: mlg %r2, 0(%r4)
; CHECK: br %r14
; Check the high end of the aligned MLG range.
define i64 @f7(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: mlg %r2, 524280(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which requires separate address logic.
; Other sequences besides this one would be OK.
define i64 @f8(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r4, 524288
; CHECK: mlg %r2, 0(%r4)
; CHECK: br %r14
; Check the high end of the negative aligned MLG range.
define i64 @f9(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: mlg %r2, -8(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the MLG range.
define i64 @f10(i64 %dummy, i64 %a, i64 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: mlg %r2, -524288(%r4)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f11(i64 *%dest, i64 %a, i64 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r4, -524296
; CHECK: mlg %r2, 0(%r4)
; CHECK: br %r14
; Check that MLG allows an index.
define i64 @f12(i64 *%dest, i64 %a, i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: mlg %r2, 524287(%r5,%r4)
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that multiplications of spilled values can use MLG rather than MLGR.
define i64 @f13(i64 *%ptr0) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: brasl %r14, foo@PLT
; CHECK: mlg {{%r[0-9]+}}, 160(%r15)
; CHECK: br %r14
; Test i32->i32 negation.
define i32 @f1(i32 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lcr %r2, %r2
; CHECK: br %r14
%neg = sub i32 0, %val
; Test i32->i64 negation.
define i64 @f2(i32 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lcgfr %r2, %r2
; CHECK: br %r14
%ext = sext i32 %val to i64
; Test i32->i64 negation that uses an "in-register" form of sign extension.
define i64 @f3(i64 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lcgfr %r2, %r2
; CHECK: br %r14
%trunc = trunc i64 %val to i32
; Test i64 negation.
define i64 @f4(i64 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lcgr %r2, %r2
; CHECK: br %r14
%neg = sub i64 0, %val
; Check SR.
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sr %r2, %r3
; CHECK: br %r14
%sub = sub i32 %a, %b
; Check the low end of the S range.
define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: s %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned S range.
define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: s %r2, 4092(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
; Check the next word up, which should use SY instead of S.
define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: sy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
; Check the high end of the aligned SY range.
define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sy %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: s %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned SY range.
define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sy %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the SY range.
define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: s %r2, 0(%r3)
; CHECK: br %r14
; Check that S allows an index.
define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: s %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that SY allows an index.
define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: sy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that subtractions of spilled values can use S rather than SR.
define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK: s %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check SGFR.
define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sgfr %r2, %r3
; CHECK: br %r14
%bext = sext i32 %b to i64
; Check SGF with no displacement.
define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sgf %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned SGF range.
define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sgf %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: sgf %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned SGF range.
define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sgf %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the SGF range.
define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sgf %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524292
; CHECK: sgf %r2, 0(%r3)
; CHECK: br %r14
; Check that SGF allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sgf %r2, 524284({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that subtractions of spilled values can use SGF rather than SGFR.
define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: sgf %r2, 160(%r15)
; CHECK: br %r14
; Check SLGFR.
define i64 @f1(i64 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: slgfr %r2, %r3
; CHECK: br %r14
%bext = zext i32 %b to i64
; Check SLGF with no displacement.
define i64 @f2(i64 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: slgf %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned SLGF range.
define i64 @f3(i64 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: slgf %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: slgf %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned SLGF range.
define i64 @f5(i64 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: slgf %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the SLGF range.
define i64 @f6(i64 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: slgf %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524292
; CHECK: slgf %r2, 0(%r3)
; CHECK: br %r14
; Check that SLGF allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: slgf %r2, 524284({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that subtractions of spilled values can use SLGF rather than SLGFR.
define i64 @f9(i32 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: slgf %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check SGR.
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sgr %r2, %r3
; CHECK: br %r14
%sub = sub i64 %a, %b
; Check SG with no displacement.
define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sg %r2, 0(%r3)
; CHECK: br %r14
%b = load i64 *%src
; Check the high end of the aligned SG range.
define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sg %r2, 524280(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: sg %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned SG range.
define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sg %r2, -8(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the SG range.
define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sg %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: sg %r2, 0(%r3)
; CHECK: br %r14
; Check that SG allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sg %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that subtractions of spilled values can use SG rather than SGR.
define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: sg %r2, 160(%r15)
; CHECK: br %r14
; Test register addition.
define void @f1(i128 *%ptr, i64 %high, i64 %low) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: slgr {{%r[0-5]}}, %r4
; CHECK: slbgr {{%r[0-5]}}, %r3
; CHECK: br %r14
; Test memory addition with no offset.
define void @f2(i64 %addr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: slg {{%r[0-5]}}, 8(%r2)
; CHECK: slbg {{%r[0-5]}}, 0(%r2)
; CHECK: br %r14
; Test the highest aligned offset that is in range of both SLG and SLBG.
define void @f3(i64 %base) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: slg {{%r[0-5]}}, 524280(%r2)
; CHECK: slbg {{%r[0-5]}}, 524272(%r2)
; CHECK: br %r14
; Test the next doubleword up, which requires separate address logic for SLG.
define void @f4(i64 %base) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lgr [[BASE:%r[1-5]]], %r2
; CHECK: agfi [[BASE]], 524288
; CHECK: slg {{%r[0-5]}}, 0([[BASE]])
; both instructions. It would be better to create an anchor at 524288
; that both instructions can use, but that isn't implemented yet.
define void @f5(i64 %base) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: slg {{%r[0-5]}}, 0({{%r[1-5]}})
; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}})
; CHECK: br %r14
; Test the lowest displacement that is in range of both SLG and SLBG.
define void @f6(i64 %base) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: slg {{%r[0-5]}}, -524280(%r2)
; CHECK: slbg {{%r[0-5]}}, -524288(%r2)
; CHECK: br %r14
; Test the next doubleword down, which is out of range of the SLBG.
define void @f7(i64 %base) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: slg {{%r[0-5]}}, -524288(%r2)
; CHECK: slbg {{%r[0-5]}}, 0({{%r[1-5]}})
; CHECK: br %r14
; Check that subtractions of spilled values can use SLG and SLBG rather than
; SLGR and SLBGR.
define void @f8(i128 *%ptr0) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: brasl %r14, foo@PLT
; CHECK: slg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
; CHECK: slbg {{%r[0-9]+}}, {{[0-9]+}}(%r15)
; Check register additions. The XOR ensures that we don't instead zero-extend
; %b into a register and use memory addition.
define void @f1(i128 *%aptr, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: slgfr {{%r[0-5]}}, %r3
; CHECK: slbgr
; CHECK: br %r14
; Like f1, but using an "in-register" extension.
define void @f2(i128 *%aptr, i64 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: slgfr {{%r[0-5]}}, %r3
; CHECK: slbgr
; CHECK: br %r14
; Test register addition in cases where the second operand is zero extended
; from i64 rather than i32, but is later masked to i32 range.
define void @f3(i128 *%aptr, i64 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: slgfr {{%r[0-5]}}, %r3
; CHECK: slbgr
; CHECK: br %r14
; Test SLGF with no offset.
define void @f4(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: slgf {{%r[0-5]}}, 0(%r3)
; CHECK: slbgr
; CHECK: br %r14
; Check the high end of the SLGF range.
define void @f5(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: slgf {{%r[0-5]}}, 524284(%r3)
; CHECK: slbgr
; CHECK: br %r14
; Check the next word up, which must use separate address logic.
; Other sequences besides this one would be OK.
define void @f6(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: slgf {{%r[0-5]}}, 0(%r3)
; CHECK: slbgr
; Check the high end of the negative aligned SLGF range.
define void @f7(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: slgf {{%r[0-5]}}, -4(%r3)
; CHECK: slbgr
; CHECK: br %r14
; Check the low end of the SLGF range.
define void @f8(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: slgf {{%r[0-5]}}, -524288(%r3)
; CHECK: slbgr
; CHECK: br %r14
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f9(i128 *%aptr, i32 *%bsrc) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: slgf {{%r[0-5]}}, 0(%r3)
; CHECK: slbgr
; Check that SLGF allows an index.
define void @f10(i128 *%aptr, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%a = load i128 *%aptr
; Check the low end of the SH range.
define i32 @f1(i32 %lhs, i16 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sh %r2, 0(%r3)
; CHECK: br %r14
%half = load i16 *%src
; Check the high end of the aligned SH range.
define i32 @f2(i32 %lhs, i16 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sh %r2, 4094(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2047
; Check the next halfword up, which should use SHY instead of SH.
define i32 @f3(i32 %lhs, i16 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: shy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 2048
; Check the high end of the aligned SHY range.
define i32 @f4(i32 %lhs, i16 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: shy %r2, 524286(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 262143
; Check the next halfword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f5(i32 %lhs, i16 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: agfi %r3, 524288
; CHECK: sh %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned SHY range.
define i32 @f6(i32 %lhs, i16 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: shy %r2, -2(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -1
; Check the low end of the SHY range.
define i32 @f7(i32 %lhs, i16 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: shy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i16 *%src, i64 -262144
; Check the next halfword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f8(i32 %lhs, i16 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r3, -524290
; CHECK: sh %r2, 0(%r3)
; CHECK: br %r14
; Check that SH allows an index.
define i32 @f9(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: sh %r2, 4094({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%sub1 = add i64 %src, %index
; Check that SHY allows an index.
define i32 @f10(i32 %lhs, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: shy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%sub1 = add i64 %src, %index
; Test a load of a fully-aligned external variable.
define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: larl %r2, e4
; CHECK-NEXT: br %r14
ret i32 *@e4
; Test a load of a fully-aligned local variable.
define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: larl %r2, d4
; CHECK-NEXT: br %r14
ret i32 *@d4
; Test a load of a 2-byte-aligned external variable.
define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: larl %r2, e2
; CHECK-NEXT: br %r14
ret i32 *@e2
; Test a load of a 2-byte-aligned local variable.
define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: larl %r2, d2
; CHECK-NEXT: br %r14
ret i32 *@d2
; Test a load of an unaligned external variable, which must go via the GOT.
define i32 *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lgrl %r2, e1@GOT
; CHECK-NEXT: br %r14
ret i32 *@e1
; Test a load of an unaligned local variable, which must go via the GOT.
define i32 *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgrl %r2, d1@GOT
; CHECK-NEXT: br %r14
ret i32 *@d1
; Test a load of an external function.
define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: larl %r2, ef
; CHECK-NEXT: br %r14
ret void() *@ef
; Test a load of a local function.
define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: larl %r2, df
; CHECK-NEXT: br %r14
ret void() *@df
; Test that LARL can be rematerialized.
define i32 @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: larl %r2, d2
; CHECK: brasl %r14, foo@PLT
; CHECK: larl %r2, d2
; Test loads of external variables. There is no guarantee that the
; variable will be in range of LARL.
define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lgrl %r2, ev@GOT
; CHECK: br %r14
ret i32 *@ev
; ...likewise locally-defined normal-visibility variables.
define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lgrl %r2, dv@GOT
; CHECK: br %r14
ret i32 *@dv
; ...likewise protected variables.
define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: lgrl %r2, pv@GOT
; CHECK: br %r14
ret i32 *@pv
; ...likewise hidden variables.
define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lgrl %r2, hv@GOT
; CHECK: br %r14
ret i32 *@hv
; Check loads of external functions. This could use LARL, but we don't have
; code to detect that yet.
define void() *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lgrl %r2, ef@GOT
; CHECK: br %r14
ret void() *@ef
; ...likewise locally-defined normal-visibility functions.
define void() *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgrl %r2, df@GOT
; CHECK: br %r14
ret void() *@df
; ...likewise protected functions.
define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lgrl %r2, pf@GOT
; CHECK: br %r14
ret void() *@pf
; ...likewise hidden functions.
define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: lgrl %r2, hf@GOT
; CHECK: br %r14
ret void() *@hf
; Test loads of external variables, which must go via the GOT.
define i32 *@f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lgrl %r2, ev@GOT
; CHECK: br %r14
ret i32 *@ev
; Check loads of locally-defined normal-visibility variables, which might
; be overridden. The load must go via the GOT.
define i32 *@f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lgrl %r2, dv@GOT
; CHECK: br %r14
ret i32 *@dv
; Check loads of protected variables, which in the small code model
; must be in range of LARL.
define i32 *@f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: larl %r2, pv
; CHECK: br %r14
ret i32 *@pv
; ...likewise hidden variables.
define i32 *@f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: larl %r2, hv
; CHECK: br %r14
ret i32 *@hv
; Like f1, but for functions.
define void() *@f5() {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: lgrl %r2, ef@GOT
; CHECK: br %r14
ret void() *@ef
; Like f2, but for functions.
define void() *@f6() {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: lgrl %r2, df@GOT
; CHECK: br %r14
ret void() *@df
; Like f3, but for functions.
define void() *@f7() {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: larl %r2, pf
; CHECK: br %r14
ret void() *@pf
; Like f4, but for functions.
define void() *@f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: larl %r2, hf
; CHECK: br %r14
ret void() *@hf
; Do some arbitrary work and return the address of the following label.
define i8 *@f1(i8 *%addr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mvi 0(%r2), 1
; CHECK: [[LABEL:\.L.*]]:
; CHECK: larl %r2, [[LABEL]]
declare void @llvm.memcpy.p0i8.p0i8.i64(i8 *nocapture, i8 *nocapture, i64, i32, i1) nounwind
define void @f1(i8 *%dest, i8 *%src) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK-NOT: %r3
; CHECK: br %r14
}
define void @f2(i8 *%dest, i8 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK-NOT: %r3
; CHECK: br %r14
}
define void @f3(i8 *%dest, i8 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvc 0(1,%r2), 0(%r3)
; CHECK: br %r14
call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 1, i32 1,
}
define void @f4(i8 *%dest, i8 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvc 0(1,%r2), 0(%r3)
; CHECK: br %r14
call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 1, i32 1,
}
define void @f5(i8 *%dest, i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvc 0(256,%r2), 0(%r3)
; CHECK: br %r14
call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 256, i32 1,
}
define void @f6(i8 *%dest, i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mvc 0(256,%r2), 0(%r3)
; CHECK: br %r14
call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 256, i32 1,
; 257 bytes is too big for a single MVC. For now expect none, so that
; the test fails and gets updated when large copies are implemented.
define void @f7(i8 *%dest, i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memcpy.p0i8.p0i8.i32(i8 *%dest, i8 *%src, i32 257, i32 1,
}
define void @f8(i8 *%dest, i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memcpy.p0i8.p0i8.i64(i8 *%dest, i8 *%src, i64 257, i32 1,
; Test the simple i8 case.
define void @f1(i8 *%ptr1) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mvc 1(1,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i8 *%ptr1, i64 1
; Test i8 cases where the value is zero-extended to 32 bits.
define void @f2(i8 *%ptr1) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mvc 1(1,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i8 *%ptr1, i64 1
; Test i8 cases where the value is zero-extended to 64 bits.
define void @f3(i8 *%ptr1) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvc 1(1,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i8 *%ptr1, i64 1
; Test i8 cases where the value is sign-extended to 32 bits.
define void @f4(i8 *%ptr1) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvc 1(1,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i8 *%ptr1, i64 1
; Test i8 cases where the value is sign-extended to 64 bits.
define void @f5(i8 *%ptr1) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvc 1(1,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i8 *%ptr1, i64 1
; Test the simple i16 case.
define void @f6(i16 *%ptr1) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mvc 2(2,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i16 *%ptr1, i64 1
; Test i16 cases where the value is zero-extended to 32 bits.
define void @f7(i16 *%ptr1) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: mvc 2(2,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i16 *%ptr1, i64 1
; Test i16 cases where the value is zero-extended to 64 bits.
define void @f8(i16 *%ptr1) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: mvc 2(2,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i16 *%ptr1, i64 1
; Test i16 cases where the value is sign-extended to 32 bits.
define void @f9(i16 *%ptr1) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: mvc 2(2,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i16 *%ptr1, i64 1
; Test i16 cases where the value is sign-extended to 64 bits.
define void @f10(i16 *%ptr1) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: mvc 2(2,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i16 *%ptr1, i64 1
; Test the simple i32 case.
define void @f11(i32 *%ptr1) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: mvc 4(4,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i32 *%ptr1, i64 1
; Test i32 cases where the value is zero-extended to 64 bits.
define void @f12(i32 *%ptr1) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: mvc 4(4,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i32 *%ptr1, i64 1
; Test i32 cases where the value is sign-extended to 64 bits.
define void @f13(i32 *%ptr1) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: mvc 4(4,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i32 *%ptr1, i64 1
; Test the i64 case.
define void @f14(i64 *%ptr1) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: mvc 8(8,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i64 *%ptr1, i64 1
; Test the f32 case.
define void @f15(float *%ptr1) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: mvc 4(4,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr float *%ptr1, i64 1
; Test the f64 case.
define void @f16(double *%ptr1) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: mvc 8(8,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr double *%ptr1, i64 1
; Test the f128 case.
define void @f17(fp128 *%ptr1) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: mvc 16(16,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr fp128 *%ptr1, i64 1
; Make sure that we don't use MVC if the load is volatile.
define void @f18(i64 *%ptr1) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK-NOT: mvc
; CHECK: br %r14
%ptr2 = getelementptr i64 *%ptr1, i64 1
; ...likewise the store.
define void @f19(i64 *%ptr1) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK-NOT: mvc
; CHECK: br %r14
%ptr2 = getelementptr i64 *%ptr1, i64 1
; Test that MVC is used for aligned loads and stores, even if there is
; no way of telling whether they alias.
define void @f20(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: mvc 0(8,%r3), 0(%r2)
; CHECK: br %r14
%val = load i64 *%ptr1
; ...but if the loads aren't aligned, we can't be sure.
define void @f21(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK-NOT: mvc
; CHECK: br %r14
%val = load i64 *%ptr1, align 2
; Test a case where there is definite overlap.
define void @f22(i64 %base) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK-NOT: mvc
; CHECK: br %r14
%add = add i64 %base, 1
; Test that we can use MVC for global addresses for i8.
define void @f23(i8 *%ptr) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
; CHECK: larl [[REG:%r[0-5]]], g1
; CHECK: mvc 0(1,%r2), 0([[REG]])
; CHECK: br %r14
; ...and again with the global on the store.
define void @f24(i8 *%ptr) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
; CHECK: larl [[REG:%r[0-5]]], g1
; CHECK: mvc 0(1,[[REG]]), 0(%r2)
; CHECK: br %r14
; Test that we use LHRL for i16.
define void @f25(i16 *%ptr) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
; CHECK: lhrl [[REG:%r[0-5]]], g2
; CHECK: sth [[REG]], 0(%r2)
; CHECK: br %r14
; ...likewise STHRL.
define void @f26(i16 *%ptr) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
; CHECK: lh [[REG:%r[0-5]]], 0(%r2)
; CHECK: sthrl [[REG]], g2
; CHECK: br %r14
; Test that we use LRL for i32.
define void @f27(i32 *%ptr) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
; CHECK: lrl [[REG:%r[0-5]]], g3
; CHECK: st [[REG]], 0(%r2)
; CHECK: br %r14
; ...likewise STRL.
define void @f28(i32 *%ptr) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
; CHECK: l [[REG:%r[0-5]]], 0(%r2)
; CHECK: strl [[REG]], g3
; CHECK: br %r14
; Test that we use LGRL for i64.
define void @f29(i64 *%ptr) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
; CHECK: lgrl [[REG:%r[0-5]]], g4
; CHECK: stg [[REG]], 0(%r2)
; CHECK: br %r14
; ...likewise STGRL.
define void @f30(i64 *%ptr) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
; CHECK: lg [[REG:%r[0-5]]], 0(%r2)
; CHECK: stgrl [[REG]], g4
; CHECK: br %r14
; Test that we can use MVC for global addresses for fp128.
define void @f31(fp128 *%ptr) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
; CHECK: larl [[REG:%r[0-5]]], g5
; CHECK: mvc 0(16,%r2), 0([[REG]])
; CHECK: br %r14
; ...and again with the global on the store.
define void @f32(fp128 *%ptr) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
; CHECK: larl [[REG:%r[0-5]]], g5
; CHECK: mvc 0(16,[[REG]]), 0(%r2)
; CHECK: br %r14
; Test a case where offset disambiguation is enough.
define void @f33(i64 *%ptr1) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
; CHECK: mvc 8(8,%r2), 0(%r2)
; CHECK: br %r14
%ptr2 = getelementptr i64 *%ptr1, i64 1
; Test f21 in cases where TBAA tells us there is no alias.
define void @f34(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
; CHECK: mvc 0(8,%r3), 0(%r2)
; CHECK: br %r14
%val = load i64 *%ptr1, align 2, !tbaa !1
; Test f21 in cases where TBAA is present but doesn't help.
define void @f35(i64 *%ptr1, i64 *%ptr2) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
; CHECK-NOT: mvc
; CHECK: br %r14
%val = load i64 *%ptr1, align 2, !tbaa !1
; No bytes, i32 version.
define void @f1(i8 *%dest, i8 %val) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK-NOT: %r3
; CHECK: br %r14
; No bytes, i64 version.
define void @f2(i8 *%dest, i8 %val) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK-NOT: %r3
; CHECK: br %r14
; 1 byte, i32 version.
define void @f3(i8 *%dest, i8 %val) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: stc %r3, 0(%r2)
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 1, i32 1, i1 false)
; 1 byte, i64 version.
define void @f4(i8 *%dest, i8 %val) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: stc %r3, 0(%r2)
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 1, i32 1, i1 false)
; 2 bytes, i32 version.
define void @f5(i8 *%dest, i8 %val) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-DAG: stc %r3, 0(%r2)
; CHECK-DAG: stc %r3, 1(%r2)
; CHECK: br %r14
; 2 bytes, i64 version.
define void @f6(i8 *%dest, i8 %val) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-DAG: stc %r3, 0(%r2)
; CHECK-DAG: stc %r3, 1(%r2)
; CHECK: br %r14
; 3 bytes, i32 version.
define void @f7(i8 *%dest, i8 %val) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: stc %r3, 0(%r2)
; CHECK: mvc 1(2,%r2), 0(%r2)
; CHECK: br %r14
; 3 bytes, i64 version.
define void @f8(i8 *%dest, i8 %val) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: stc %r3, 0(%r2)
; CHECK: mvc 1(2,%r2), 0(%r2)
; CHECK: br %r14
; 257 bytes, i32 version.
define void @f9(i8 *%dest, i8 %val) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: stc %r3, 0(%r2)
; CHECK: mvc 1(256,%r2), 0(%r2)
; CHECK: br %r14
; 257 bytes, i64 version.
define void @f10(i8 *%dest, i8 %val) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: stc %r3, 0(%r2)
; CHECK: mvc 1(256,%r2), 0(%r2)
; CHECK: br %r14
; For now expect none, so that the test fails and gets updated when
; large copies are implemented.
define void @f11(i8 *%dest, i8 %val) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 %val, i32 258, i32 1, i1 false)
; 258 bytes, i64 version, with the same comments as above.
define void @f12(i8 *%dest, i8 %val) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 %val, i64 258, i32 1, i1 false)
; No bytes, i32 version.
define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 0, i32 1, i1 false)
; No bytes, i64 version.
define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 0, i32 1, i1 false)
; 1 byte, i32 version.
define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvi 0(%r2), 128
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 1, i32 1, i1 false)
; 1 byte, i64 version.
define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvi 0(%r2), 128
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 1, i32 1, i1 false)
; 2 bytes, i32 version.
define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvhhi 0(%r2), -32640
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 2, i32 1, i1 false)
; 2 bytes, i64 version.
define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mvhhi 0(%r2), -32640
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 2, i32 1, i1 false)
; 3 bytes, i32 version.
define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-DAG: mvhhi 0(%r2), -32640
; CHECK-DAG: mvi 2(%r2), 128
; CHECK: br %r14
; 3 bytes, i64 version.
define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-DAG: mvhhi 0(%r2), -32640
; CHECK-DAG: mvi 2(%r2), 128
; CHECK: br %r14
; 4 bytes, i32 version.
define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: iilf [[REG:%r[0-5]]], 2155905152
; CHECK: st [[REG]], 0(%r2)
; CHECK: br %r14
; 4 bytes, i64 version.
define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: iilf [[REG:%r[0-5]]], 2155905152
; CHECK: st [[REG]], 0(%r2)
; CHECK: br %r14
; 5 bytes, i32 version.
define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: mvi 0(%r2), 128
; CHECK: mvc 1(4,%r2), 0(%r2)
; CHECK: br %r14
; 5 bytes, i64 version.
define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: mvi 0(%r2), 128
; CHECK: mvc 1(4,%r2), 0(%r2)
; CHECK: br %r14
; 257 bytes, i32 version.
define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: mvi 0(%r2), 128
; CHECK: mvc 1(256,%r2), 0(%r2)
; CHECK: br %r14
; 257 bytes, i64 version.
define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: mvi 0(%r2), 128
; CHECK: mvc 1(256,%r2), 0(%r2)
; CHECK: br %r14
; For now expect none, so that the test fails and gets updated when
; large copies are implemented.
define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 128, i32 258, i32 1, i1 false)
; 258 bytes, i64 version, with the same comments as above.
define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 128, i64 258, i32 1, i1 false)
; No bytes, i32 version.
define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 0, i32 1, i1 false)
; No bytes, i64 version.
define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 0, i32 1, i1 false)
; 1 byte, i32 version.
define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvi 0(%r2), 0
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 1, i32 1, i1 false)
; 1 byte, i64 version.
define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvi 0(%r2), 0
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 1, i32 1, i1 false)
; 2 bytes, i32 version.
define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvhhi 0(%r2), 0
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 2, i32 1, i1 false)
; 2 bytes, i64 version.
define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mvhhi 0(%r2), 0
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 2, i32 1, i1 false)
; 3 bytes, i32 version.
define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-DAG: mvhhi 0(%r2), 0
; CHECK-DAG: mvi 2(%r2), 0
; CHECK: br %r14
; 3 bytes, i64 version.
define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-DAG: mvhhi 0(%r2), 0
; CHECK-DAG: mvi 2(%r2), 0
; CHECK: br %r14
; 4 bytes, i32 version.
define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: mvhi 0(%r2), 0
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 4, i32 1, i1 false)
; 4 bytes, i64 version.
define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: mvhi 0(%r2), 0
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 4, i32 1, i1 false)
; 5 bytes, i32 version.
define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-DAG: mvhi 0(%r2), 0
; CHECK-DAG: mvi 4(%r2), 0
; CHECK: br %r14
; 5 bytes, i64 version.
define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-DAG: mvhi 0(%r2), 0
; CHECK-DAG: mvi 4(%r2), 0
; CHECK: br %r14
; 6 bytes, i32 version.
define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK-DAG: mvhi 0(%r2), 0
; CHECK-DAG: mvhhi 4(%r2), 0
; CHECK: br %r14
; 6 bytes, i64 version.
define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-DAG: mvhi 0(%r2), 0
; CHECK-DAG: mvhhi 4(%r2), 0
; CHECK: br %r14
; 7 bytes, i32 version.
define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(6,%r2), 0(%r2)
; CHECK: br %r14
; 7 bytes, i64 version.
define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(6,%r2), 0(%r2)
; CHECK: br %r14
; 8 bytes, i32 version.
define void @f17(i8 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: mvghi 0(%r2), 0
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 8, i32 1, i1 false)
; 8 bytes, i64 version.
define void @f18(i8 *%dest) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: mvghi 0(%r2), 0
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 8, i32 1, i1 false)
; 9 bytes, i32 version.
define void @f19(i8 *%dest) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK-DAG: mvghi 0(%r2), 0
; CHECK-DAG: mvi 8(%r2), 0
; CHECK: br %r14
; 9 bytes, i64 version.
define void @f20(i8 *%dest) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK-DAG: mvghi 0(%r2), 0
; CHECK-DAG: mvi 8(%r2), 0
; CHECK: br %r14
; 10 bytes, i32 version.
define void @f21(i8 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK-DAG: mvghi 0(%r2), 0
; CHECK-DAG: mvhhi 8(%r2), 0
; CHECK: br %r14
; 10 bytes, i64 version.
define void @f22(i8 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK-DAG: mvghi 0(%r2), 0
; CHECK-DAG: mvhhi 8(%r2), 0
; CHECK: br %r14
; 11 bytes, i32 version.
define void @f23(i8 *%dest) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(10,%r2), 0(%r2)
; CHECK: br %r14
; 11 bytes, i64 version.
define void @f24(i8 *%dest) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(10,%r2), 0(%r2)
; CHECK: br %r14
; 12 bytes, i32 version.
define void @f25(i8 *%dest) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
; CHECK-DAG: mvghi 0(%r2), 0
; CHECK-DAG: mvhi 8(%r2), 0
; CHECK: br %r14
; 12 bytes, i64 version.
define void @f26(i8 *%dest) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
; CHECK-DAG: mvghi 0(%r2), 0
; CHECK-DAG: mvhi 8(%r2), 0
; CHECK: br %r14
; 13 bytes, i32 version.
define void @f27(i8 *%dest) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(12,%r2), 0(%r2)
; CHECK: br %r14
; 13 bytes, i64 version.
define void @f28(i8 *%dest) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(12,%r2), 0(%r2)
; CHECK: br %r14
; 14 bytes, i32 version.
define void @f29(i8 *%dest) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(13,%r2), 0(%r2)
; CHECK: br %r14
; 14 bytes, i64 version.
define void @f30(i8 *%dest) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(13,%r2), 0(%r2)
; CHECK: br %r14
; 15 bytes, i32 version.
define void @f31(i8 *%dest) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(14,%r2), 0(%r2)
; CHECK: br %r14
; 15 bytes, i64 version.
define void @f32(i8 *%dest) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(14,%r2), 0(%r2)
; CHECK: br %r14
; 16 bytes, i32 version.
define void @f33(i8 *%dest) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
; CHECK-DAG: mvghi 0(%r2), 0
; CHECK-DAG: mvghi 8(%r2), 0
; CHECK: br %r14
; 16 bytes, i64 version.
define void @f34(i8 *%dest) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
; CHECK-DAG: mvghi 0(%r2), 0
; CHECK-DAG: mvghi 8(%r2), 0
; CHECK: br %r14
; 17 bytes, i32 version.
define void @f35(i8 *%dest) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(16,%r2), 0(%r2)
; CHECK: br %r14
; 17 bytes, i64 version.
define void @f36(i8 *%dest) {
-; CHECK: f36:
+; CHECK-LABEL: f36:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(16,%r2), 0(%r2)
; CHECK: br %r14
; 257 bytes, i32 version.
define void @f37(i8 *%dest) {
-; CHECK: f37:
+; CHECK-LABEL: f37:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(256,%r2), 0(%r2)
; CHECK: br %r14
; 257 bytes, i64 version.
define void @f38(i8 *%dest) {
-; CHECK: f38:
+; CHECK-LABEL: f38:
; CHECK: mvi 0(%r2), 0
; CHECK: mvc 1(256,%r2), 0(%r2)
; CHECK: br %r14
; For now expect none, so that the test fails and gets updated when
; large copies are implemented.
define void @f39(i8 *%dest) {
-; CHECK: f39:
+; CHECK-LABEL: f39:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 0, i32 258, i32 1, i1 false)
; 258 bytes, i64 version, with the same comments as above.
define void @f40(i8 *%dest) {
-; CHECK: f40:
+; CHECK-LABEL: f40:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 0, i64 258, i32 1, i1 false)
; No bytes, i32 version.
define void @f1(i8 *%dest) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NOT: %r2
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 0, i32 1, i1 false)
; No bytes, i64 version.
define void @f2(i8 *%dest) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: %r2
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 0, i32 1, i1 false)
; 1 byte, i32 version.
define void @f3(i8 *%dest) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvi 0(%r2), 255
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 1, i32 1, i1 false)
; 1 byte, i64 version.
define void @f4(i8 *%dest) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvi 0(%r2), 255
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 1, i32 1, i1 false)
; 2 bytes, i32 version.
define void @f5(i8 *%dest) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvhhi 0(%r2), -1
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 2, i32 1, i1 false)
; 2 bytes, i64 version.
define void @f6(i8 *%dest) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mvhhi 0(%r2), -1
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 2, i32 1, i1 false)
; 3 bytes, i32 version.
define void @f7(i8 *%dest) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-DAG: mvhhi 0(%r2), -1
; CHECK-DAG: mvi 2(%r2), 255
; CHECK: br %r14
; 3 bytes, i64 version.
define void @f8(i8 *%dest) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-DAG: mvhhi 0(%r2), -1
; CHECK-DAG: mvi 2(%r2), 255
; CHECK: br %r14
; 4 bytes, i32 version.
define void @f9(i8 *%dest) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: mvhi 0(%r2), -1
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 4, i32 1, i1 false)
; 4 bytes, i64 version.
define void @f10(i8 *%dest) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: mvhi 0(%r2), -1
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 4, i32 1, i1 false)
; 5 bytes, i32 version.
define void @f11(i8 *%dest) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-DAG: mvhi 0(%r2), -1
; CHECK-DAG: mvi 4(%r2), 255
; CHECK: br %r14
; 5 bytes, i64 version.
define void @f12(i8 *%dest) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK-DAG: mvhi 0(%r2), -1
; CHECK-DAG: mvi 4(%r2), 255
; CHECK: br %r14
; 6 bytes, i32 version.
define void @f13(i8 *%dest) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK-DAG: mvhi 0(%r2), -1
; CHECK-DAG: mvhhi 4(%r2), -1
; CHECK: br %r14
; 6 bytes, i64 version.
define void @f14(i8 *%dest) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK-DAG: mvhi 0(%r2), -1
; CHECK-DAG: mvhhi 4(%r2), -1
; CHECK: br %r14
; 7 bytes, i32 version.
define void @f15(i8 *%dest) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(6,%r2), 0(%r2)
; CHECK: br %r14
; 7 bytes, i64 version.
define void @f16(i8 *%dest) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(6,%r2), 0(%r2)
; CHECK: br %r14
; 8 bytes, i32 version.
define void @f17(i8 *%dest) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: mvghi 0(%r2), -1
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 8, i32 1, i1 false)
; 8 bytes, i64 version.
define void @f18(i8 *%dest) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: mvghi 0(%r2), -1
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 8, i32 1, i1 false)
; 9 bytes, i32 version.
define void @f19(i8 *%dest) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK-DAG: mvghi 0(%r2), -1
; CHECK-DAG: mvi 8(%r2), 255
; CHECK: br %r14
; 9 bytes, i64 version.
define void @f20(i8 *%dest) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK-DAG: mvghi 0(%r2), -1
; CHECK-DAG: mvi 8(%r2), 255
; CHECK: br %r14
; 10 bytes, i32 version.
define void @f21(i8 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK-DAG: mvghi 0(%r2), -1
; CHECK-DAG: mvhhi 8(%r2), -1
; CHECK: br %r14
; 10 bytes, i64 version.
define void @f22(i8 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK-DAG: mvghi 0(%r2), -1
; CHECK-DAG: mvhhi 8(%r2), -1
; CHECK: br %r14
; 11 bytes, i32 version.
define void @f23(i8 *%dest) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(10,%r2), 0(%r2)
; CHECK: br %r14
; 11 bytes, i64 version.
define void @f24(i8 *%dest) {
-; CHECK: f24:
+; CHECK-LABEL: f24:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(10,%r2), 0(%r2)
; CHECK: br %r14
; 12 bytes, i32 version.
define void @f25(i8 *%dest) {
-; CHECK: f25:
+; CHECK-LABEL: f25:
; CHECK-DAG: mvghi 0(%r2), -1
; CHECK-DAG: mvhi 8(%r2), -1
; CHECK: br %r14
; 12 bytes, i64 version.
define void @f26(i8 *%dest) {
-; CHECK: f26:
+; CHECK-LABEL: f26:
; CHECK-DAG: mvghi 0(%r2), -1
; CHECK-DAG: mvhi 8(%r2), -1
; CHECK: br %r14
; 13 bytes, i32 version.
define void @f27(i8 *%dest) {
-; CHECK: f27:
+; CHECK-LABEL: f27:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(12,%r2), 0(%r2)
; CHECK: br %r14
; 13 bytes, i64 version.
define void @f28(i8 *%dest) {
-; CHECK: f28:
+; CHECK-LABEL: f28:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(12,%r2), 0(%r2)
; CHECK: br %r14
; 14 bytes, i32 version.
define void @f29(i8 *%dest) {
-; CHECK: f29:
+; CHECK-LABEL: f29:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(13,%r2), 0(%r2)
; CHECK: br %r14
; 14 bytes, i64 version.
define void @f30(i8 *%dest) {
-; CHECK: f30:
+; CHECK-LABEL: f30:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(13,%r2), 0(%r2)
; CHECK: br %r14
; 15 bytes, i32 version.
define void @f31(i8 *%dest) {
-; CHECK: f31:
+; CHECK-LABEL: f31:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(14,%r2), 0(%r2)
; CHECK: br %r14
; 15 bytes, i64 version.
define void @f32(i8 *%dest) {
-; CHECK: f32:
+; CHECK-LABEL: f32:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(14,%r2), 0(%r2)
; CHECK: br %r14
; 16 bytes, i32 version.
define void @f33(i8 *%dest) {
-; CHECK: f33:
+; CHECK-LABEL: f33:
; CHECK-DAG: mvghi 0(%r2), -1
; CHECK-DAG: mvghi 8(%r2), -1
; CHECK: br %r14
; 16 bytes, i64 version.
define void @f34(i8 *%dest) {
-; CHECK: f34:
+; CHECK-LABEL: f34:
; CHECK-DAG: mvghi 0(%r2), -1
; CHECK-DAG: mvghi 8(%r2), -1
; CHECK: br %r14
; 17 bytes, i32 version.
define void @f35(i8 *%dest) {
-; CHECK: f35:
+; CHECK-LABEL: f35:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(16,%r2), 0(%r2)
; CHECK: br %r14
; 17 bytes, i64 version.
define void @f36(i8 *%dest) {
-; CHECK: f36:
+; CHECK-LABEL: f36:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(16,%r2), 0(%r2)
; CHECK: br %r14
; 257 bytes, i32 version.
define void @f37(i8 *%dest) {
-; CHECK: f37:
+; CHECK-LABEL: f37:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(256,%r2), 0(%r2)
; CHECK: br %r14
; 257 bytes, i64 version.
define void @f38(i8 *%dest) {
-; CHECK: f38:
+; CHECK-LABEL: f38:
; CHECK: mvi 0(%r2), 255
; CHECK: mvc 1(256,%r2), 0(%r2)
; CHECK: br %r14
; For now expect none, so that the test fails and gets updated when
; large copies are implemented.
define void @f39(i8 *%dest) {
-; CHECK: f39:
+; CHECK-LABEL: f39:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memset.p0i8.i32(i8 *%dest, i8 -1, i32 258, i32 1, i1 false)
; 258 bytes, i64 version, with the same comments as above.
define void @f40(i8 *%dest) {
-; CHECK: f40:
+; CHECK-LABEL: f40:
; CHECK-NOT: mvc
; CHECK: br %r14
call void @llvm.memset.p0i8.i64(i8 *%dest, i8 -1, i64 258, i32 1, i1 false)
; Check OR.
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: or %r2, %r3
; CHECK: br %r14
%or = or i32 %a, %b
; Check the low end of the O range.
define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: o %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned O range.
define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: o %r2, 4092(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
; Check the next word up, which should use OY instead of O.
define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
; Check the high end of the aligned OY range.
define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oy %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: o %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned OY range.
define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oy %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the OY range.
define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: oy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: o %r2, 0(%r3)
; CHECK: br %r14
; Check that O allows an index.
define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: o %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that OY allows an index.
define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: oy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that ORs of spilled values can use O rather than OR.
define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK: o %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check the lowest useful OILL value.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: oill %r2, 1
; CHECK: br %r14
%or = or i32 %a, 1
; Check the high end of the OILL range.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: oill %r2, 65535
; CHECK: br %r14
%or = or i32 %a, 65535
; Check the lowest useful OILH range, which is the next value up.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oilh %r2, 1
; CHECK: br %r14
%or = or i32 %a, 65536
; Check the lowest useful OILF value, which is the next value up again.
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilf %r2, 65537
; CHECK: br %r14
%or = or i32 %a, 65537
; Check the high end of the OILH range.
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilh %r2, 65535
; CHECK: br %r14
%or = or i32 %a, -65536
; Check the next value up, which must use OILF instead.
define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilf %r2, 4294901761
; CHECK: br %r14
%or = or i32 %a, -65535
; Check the highest useful OILF value.
define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oilf %r2, 4294967294
; CHECK: br %r14
%or = or i32 %a, -2
; Check OGR.
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ogr %r2, %r3
; CHECK: br %r14
%or = or i64 %a, %b
; Check OG with no displacement.
define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: og %r2, 0(%r3)
; CHECK: br %r14
%b = load i64 *%src
; Check the high end of the aligned OG range.
define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: og %r2, 524280(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: og %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned OG range.
define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: og %r2, -8(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the OG range.
define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: og %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: og %r2, 0(%r3)
; CHECK: br %r14
; Check that OG allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: og %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that ORs of spilled values can use OG rather than OGR.
define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: og %r2, 160(%r15)
; CHECK: br %r14
; Check the lowest useful OILL value.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: oill %r2, 1
; CHECK: br %r14
%or = or i64 %a, 1
; Check the high end of the OILL range.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: oill %r2, 65535
; CHECK: br %r14
%or = or i64 %a, 65535
; Check the lowest useful OILH value, which is the next value up.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oilh %r2, 1
; CHECK: br %r14
%or = or i64 %a, 65536
; Check the lowest useful OILF value, which is the next value up again.
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oilf %r2, 4294901759
; CHECK: br %r14
%or = or i64 %a, 4294901759
; Check the high end of the OILH range.
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oilh %r2, 65535
; CHECK: br %r14
%or = or i64 %a, 4294901760
; Check the high end of the OILF range.
define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oilf %r2, 4294967295
; CHECK: br %r14
%or = or i64 %a, 4294967295
; Check the lowest useful OIHL value, which is the next value up.
define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oihl %r2, 1
; CHECK: br %r14
%or = or i64 %a, 4294967296
; Check the next value up again, which must use two ORs.
define i64 @f8(i64 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: oihl %r2, 1
; CHECK: oill %r2, 1
; CHECK: br %r14
; Check the high end of the OILL range.
define i64 @f9(i64 %a) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: oihl %r2, 1
; CHECK: oill %r2, 65535
; CHECK: br %r14
; Check the next value up, which must use OILH
define i64 @f10(i64 %a) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: oihl %r2, 1
; CHECK: oilh %r2, 1
; CHECK: br %r14
; Check the next value up again, which must use OILF
define i64 @f11(i64 %a) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: oihl %r2, 1
; CHECK: oilf %r2, 65537
; CHECK: br %r14
; Check the high end of the OIHL range.
define i64 @f12(i64 %a) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: oihl %r2, 65535
; CHECK: br %r14
%or = or i64 %a, 281470681743360
; Check a combination of the high end of the OIHL range and the high end
; of the OILF range.
define i64 @f13(i64 %a) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: oihl %r2, 65535
; CHECK: oilf %r2, 4294967295
; CHECK: br %r14
; Check the lowest useful OIHH value.
define i64 @f14(i64 %a) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: oihh %r2, 1
; CHECK: br %r14
%or = or i64 %a, 281474976710656
; Check the next value up, which needs two ORs.
define i64 @f15(i64 %a) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: oihh %r2, 1
; CHECK: oill %r2, 1
; CHECK: br %r14
; Check the lowest useful OIHF value.
define i64 @f16(i64 %a) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: oihf %r2, 65537
; CHECK: br %r14
%or = or i64 %a, 281479271677952
; Check the high end of the OIHH range.
define i64 @f17(i64 %a) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: oihh %r2, 65535
; CHECK: br %r14
%or = or i64 %a, 18446462598732840960
; Check the high end of the OIHF range.
define i64 @f18(i64 %a) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: oihf %r2, 4294967295
; CHECK: br %r14
%or = or i64 %a, -4294967296
; Check the highest useful OR value.
define i64 @f19(i64 %a) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: oihf %r2, 4294967295
; CHECK: oilf %r2, 4294967294
; CHECK: br %r14
; Check the lowest useful constant, expressed as a signed integer.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: oi 0(%r2), 1
; CHECK: br %r14
%val = load i8 *%ptr
; Check the highest useful constant, expressed as a signed integer.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Check the lowest useful constant, expressed as an unsigned integer.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oi 0(%r2), 1
; CHECK: br %r14
%val = load i8 *%ptr
; Check the highest useful constant, expressed as a unsigned integer.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Check the high end of the OI range.
define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oi 4095(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4095
; Check the next byte up, which should use OIY instead of OI.
define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oiy 4096(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4096
; Check the high end of the OIY range.
define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oiy 524287(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, 524288
; CHECK: oi 0(%r2), 127
; CHECK: br %r14
; Check the high end of the negative OIY range.
define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: oiy -1(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the OIY range.
define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: oiy -524288(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r2, -524289
; CHECK: oi 0(%r2), 127
; CHECK: br %r14
; Check that OI does not allow an index
define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: agr %r2, %r3
; CHECK: oi 4095(%r2), 127
; CHECK: br %r14
; Check that OIY does not allow an index
define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: agr %r2, %r3
; CHECK: oiy 4096(%r2), 127
; CHECK: br %r14
; Zero extension to 32 bits, negative constant.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 64 bits, negative constant.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 32 bits, positive constant.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 64 bits, positive constant.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 32 bits, negative constant.
define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 64 bits, negative constant.
define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 32 bits, positive constant.
define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 64 bits, positive constant.
define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: oi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Test an extraction of bit 0 from a right-shifted value.
define i32 @f1(i32 %foo) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: risbg %r2, %r2, 63, 191, 54
; CHECK: br %r14
%shr = lshr i32 %foo, 10
; ...and again with i64.
define i64 @f2(i64 %foo) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: risbg %r2, %r2, 63, 191, 54
; CHECK: br %r14
%shr = lshr i64 %foo, 10
; Test an extraction of other bits from a right-shifted value.
define i32 @f3(i32 %foo) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: risbg %r2, %r2, 60, 189, 42
; CHECK: br %r14
%shr = lshr i32 %foo, 22
; ...and again with i64.
define i64 @f4(i64 %foo) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: risbg %r2, %r2, 60, 189, 42
; CHECK: br %r14
%shr = lshr i64 %foo, 22
; Test an extraction of most bits from a right-shifted value.
; The range should be reduced to exclude the zeroed high bits.
define i32 @f5(i32 %foo) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: risbg %r2, %r2, 34, 188, 62
; CHECK: br %r14
%shr = lshr i32 %foo, 2
; ...and again with i64.
define i64 @f6(i64 %foo) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: risbg %r2, %r2, 2, 188, 62
; CHECK: br %r14
%shr = lshr i64 %foo, 2
; Try the next value up (mask ....1111001). The mask itself is suitable
; for RISBG, but the shift is still needed.
define i32 @f7(i32 %foo) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: srl %r2, 2
; CHECK: risbg %r2, %r2, 63, 188, 0
; CHECK: br %r14
; ...and again with i64.
define i64 @f8(i64 %foo) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: srlg [[REG:%r[0-5]]], %r2, 2
; CHECK: risbg %r2, [[REG]], 63, 188, 0
; CHECK: br %r14
; Test an extraction of bits from a left-shifted value. The range should
; be reduced to exclude the zeroed low bits.
define i32 @f9(i32 %foo) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: risbg %r2, %r2, 56, 189, 2
; CHECK: br %r14
%shr = shl i32 %foo, 2
; ...and again with i64.
define i64 @f10(i64 %foo) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: risbg %r2, %r2, 56, 189, 2
; CHECK: br %r14
%shr = shl i64 %foo, 2
; Try a wrap-around mask (mask ....111100001111). The mask itself is suitable
; for RISBG, but the shift is still needed.
define i32 @f11(i32 %foo) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: sll %r2, 2
; CHECK: risbg %r2, %r2, 60, 183, 0
; CHECK: br %r14
; ...and again with i64.
define i64 @f12(i64 %foo) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: sllg [[REG:%r[0-5]]], %r2, 2
; CHECK: risbg %r2, [[REG]], 60, 183, 0
; CHECK: br %r14
; This is equivalent to the lshr case, because the bits from the
; shl are not used.
define i32 @f13(i32 %foo) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: risbg %r2, %r2, 56, 188, 46
; CHECK: br %r14
%parta = shl i32 %foo, 14
; ...and again with i64.
define i64 @f14(i64 %foo) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: risbg %r2, %r2, 56, 188, 14
; CHECK: br %r14
%parta = shl i64 %foo, 14
; Try a case in which only the bits from the shl are used.
define i32 @f15(i32 %foo) {
-; CHECK: f15:
+; CHECK-LABEL: f15:
; CHECK: risbg %r2, %r2, 47, 177, 14
; CHECK: br %r14
%parta = shl i32 %foo, 14
; ...and again with i64.
define i64 @f16(i64 %foo) {
-; CHECK: f16:
+; CHECK-LABEL: f16:
; CHECK: risbg %r2, %r2, 47, 177, 14
; CHECK: br %r14
%parta = shl i64 %foo, 14
; This needs a separate shift (although RISBLG would be better
; if supported).
define i32 @f17(i32 %foo) {
-; CHECK: f17:
+; CHECK-LABEL: f17:
; CHECK: rll [[REG:%r[0-5]]], %r2, 4
; CHECK: risbg %r2, [[REG]], 57, 190, 0
; CHECK: br %r14
; ...and for i64, where RISBG should do the rotate too.
define i64 @f18(i64 %foo) {
-; CHECK: f18:
+; CHECK-LABEL: f18:
; CHECK: risbg %r2, %r2, 57, 190, 4
; CHECK: br %r14
%parta = shl i64 %foo, 4
; Test an arithmetic shift right in which some of the sign bits are kept.
; The SRA is still needed.
define i32 @f19(i32 %foo) {
-; CHECK: f19:
+; CHECK-LABEL: f19:
; CHECK: sra %r2, 28
; CHECK: risbg %r2, %r2, 59, 190, 0
; CHECK: br %r14
; ...and again with i64.
define i64 @f20(i64 %foo) {
-; CHECK: f20:
+; CHECK-LABEL: f20:
; CHECK: srag [[REG:%r[0-5]]], %r2, 60
; CHECK: risbg %r2, [[REG]], 59, 190, 0
; CHECK: br %r14
; Introduce a second use of %shr so that the ashr doesn't decompose to
; an lshr.
define i32 @f21(i32 %foo, i32 *%dest) {
-; CHECK: f21:
+; CHECK-LABEL: f21:
; CHECK: risbg %r2, %r2, 60, 190, 36
; CHECK: br %r14
%shr = ashr i32 %foo, 28
; ...and again with i64.
define i64 @f22(i64 %foo, i64 *%dest) {
-; CHECK: f22:
+; CHECK-LABEL: f22:
; CHECK: risbg %r2, %r2, 60, 190, 4
; CHECK: br %r14
%shr = ashr i64 %foo, 60
; Check that we use RISBG for shifted values even if the AND is a
; natural zero extension.
define i64 @f23(i64 %foo) {
-; CHECK: f23:
+; CHECK-LABEL: f23:
; CHECK: risbg %r2, %r2, 56, 191, 62
; CHECK: br %r14
%shr = lshr i64 %foo, 2
; Check the low end of the SLL range.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sll %r2, 1
; CHECK: br %r14
%shift = shl i32 %a, 1
; Check the high end of the defined SLL range.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sll %r2, 31
; CHECK: br %r14
%shift = shl i32 %a, 31
; We don't generate shifts by out-of-range values.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: sll %r2, 32
; CHECK: br %r14
%shift = shl i32 %a, 32
; Make sure that we don't generate negative shift amounts.
define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: sll %r2, -1{{.*}}
; CHECK: br %r14
%sub = sub i32 %amt, 1
; Check variable shifts.
define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sll %r2, 0(%r3)
; CHECK: br %r14
%shift = shl i32 %a, %amt
; Check shift amounts that have a constant term.
define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sll %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; ...and again with a truncated 64-bit shift amount.
define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sll %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; Check shift amounts that have the largest in-range constant term. We could
; mask the amount instead.
define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sll %r2, 4095(%r3)
; CHECK: br %r14
%add = add i32 %amt, 4095
; Check the next value up. Again, we could mask the amount instead.
define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ahi %r3, 4096
; CHECK: sll %r2, 0(%r3)
; CHECK: br %r14
; Check that we don't try to generate "indexed" shifts.
define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ar {{%r3, %r4|%r4, %r3}}
; CHECK: sll %r2, 0({{%r[34]}})
; CHECK: br %r14
; Check that the shift amount uses an address register. It cannot be in %r0.
define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: l %r1, 0(%r3)
; CHECK: sll %r2, 0(%r1)
; CHECK: br %r14
; Check the low end of the SRL range.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: srl %r2, 1
; CHECK: br %r14
%shift = lshr i32 %a, 1
; Check the high end of the defined SRL range.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: srl %r2, 31
; CHECK: br %r14
%shift = lshr i32 %a, 31
; We don't generate shifts by out-of-range values.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: srl %r2, 32
; CHECK: br %r14
%shift = lshr i32 %a, 32
; Make sure that we don't generate negative shift amounts.
define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: srl %r2, -1{{.*}}
; CHECK: br %r14
%sub = sub i32 %amt, 1
; Check variable shifts.
define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: srl %r2, 0(%r3)
; CHECK: br %r14
%shift = lshr i32 %a, %amt
; Check shift amounts that have a constant term.
define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: srl %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; ...and again with a truncated 64-bit shift amount.
define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: srl %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; Check shift amounts that have the largest in-range constant term. We could
; mask the amount instead.
define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: srl %r2, 4095(%r3)
; CHECK: br %r14
%add = add i32 %amt, 4095
; Check the next value up. Again, we could mask the amount instead.
define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ahi %r3, 4096
; CHECK: srl %r2, 0(%r3)
; CHECK: br %r14
; Check that we don't try to generate "indexed" shifts.
define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ar {{%r3, %r4|%r4, %r3}}
; CHECK: srl %r2, 0({{%r[34]}})
; CHECK: br %r14
; Check that the shift amount uses an address register. It cannot be in %r0.
define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: l %r1, 0(%r3)
; CHECK: srl %r2, 0(%r1)
; CHECK: br %r14
; Check the low end of the SRA range.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sra %r2, 1
; CHECK: br %r14
%shift = ashr i32 %a, 1
; Check the high end of the defined SRA range.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sra %r2, 31
; CHECK: br %r14
%shift = ashr i32 %a, 31
; We don't generate shifts by out-of-range values.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: sra %r2, 32
; CHECK: br %r14
%shift = ashr i32 %a, 32
; Make sure that we don't generate negative shift amounts.
define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NOT: sra %r2, -1{{.*}}
; CHECK: br %r14
%sub = sub i32 %amt, 1
; Check variable shifts.
define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sra %r2, 0(%r3)
; CHECK: br %r14
%shift = ashr i32 %a, %amt
; Check shift amounts that have a constant term.
define i32 @f6(i32 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sra %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; ...and again with a truncated 64-bit shift amount.
define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sra %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; Check shift amounts that have the largest in-range constant term. We could
; mask the amount instead.
define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sra %r2, 4095(%r3)
; CHECK: br %r14
%add = add i32 %amt, 4095
; Check the next value up. Again, we could mask the amount instead.
define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: ahi %r3, 4096
; CHECK: sra %r2, 0(%r3)
; CHECK: br %r14
; Check that we don't try to generate "indexed" shifts.
define i32 @f10(i32 %a, i32 %b, i32 %c) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: ar {{%r3, %r4|%r4, %r3}}
; CHECK: sra %r2, 0({{%r[34]}})
; CHECK: br %r14
; Check that the shift amount uses an address register. It cannot be in %r0.
define i32 @f11(i32 %a, i32 *%ptr) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: l %r1, 0(%r3)
; CHECK: sra %r2, 0(%r1)
; CHECK: br %r14
; Check the low end of the RLL range.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: rll %r2, %r2, 1
; CHECK: br %r14
%parta = shl i32 %a, 1
; Check the high end of the defined RLL range.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: rll %r2, %r2, 31
; CHECK: br %r14
%parta = shl i32 %a, 31
; We don't generate shifts by out-of-range values.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: rll
; CHECK: br %r14
%parta = shl i32 %a, 32
; Check variable shifts.
define i32 @f4(i32 %a, i32 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: rll %r2, %r2, 0(%r3)
; CHECK: br %r14
%amtb = sub i32 32, %amt
; Check shift amounts that have a constant term.
define i32 @f5(i32 %a, i32 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: rll %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; ...and again with a truncated 64-bit shift amount.
define i32 @f6(i32 %a, i64 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: rll %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; ...and again with a different truncation representation.
define i32 @f7(i32 %a, i64 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: rll %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; Check shift amounts that have the largest in-range constant term. We could
; mask the amount instead.
define i32 @f8(i32 %a, i32 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: rll %r2, %r2, 524287(%r3)
; CHECK: br %r14
%add = add i32 %amt, 524287
; Check the next value up, which without masking must use a separate
; addition.
define i32 @f9(i32 %a, i32 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: afi %r3, 524288
; CHECK: rll %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check cases where 1 is subtracted from the shift amount.
define i32 @f10(i32 %a, i32 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: rll %r2, %r2, -1(%r3)
; CHECK: br %r14
%suba = sub i32 %amt, 1
; Check the lowest value that can be subtracted from the shift amount.
; Again, we could mask the shift amount instead.
define i32 @f11(i32 %a, i32 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: rll %r2, %r2, -524288(%r3)
; CHECK: br %r14
%suba = sub i32 %amt, 524288
; Check the next value down, which without masking must use a separate
; addition.
define i32 @f12(i32 %a, i32 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: afi %r3, -524289
; CHECK: rll %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check that we don't try to generate "indexed" shifts.
define i32 @f13(i32 %a, i32 %b, i32 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: ar {{%r3, %r4|%r4, %r3}}
; CHECK: rll %r2, %r2, 0({{%r[34]}})
; CHECK: br %r14
; Check that the shift amount uses an address register. It cannot be in %r0.
define i32 @f14(i32 %a, i32 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: l %r1, 0(%r3)
; CHECK: rll %r2, %r2, 0(%r1)
; CHECK: br %r14
; Check the low end of the SLLG range.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: sllg %r2, %r2, 1
; CHECK: br %r14
%shift = shl i64 %a, 1
; Check the high end of the defined SLLG range.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sllg %r2, %r2, 63
; CHECK: br %r14
%shift = shl i64 %a, 63
; We don't generate shifts by out-of-range values.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: sllg
; CHECK: br %r14
%shift = shl i64 %a, 64
; Check variable shifts.
define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: sllg %r2, %r2, 0(%r3)
; CHECK: br %r14
%shift = shl i64 %a, %amt
; Check shift amounts that have a constant term.
define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sllg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; ...and again with a sign-extended 32-bit shift amount.
define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: sllg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; ...and now with a zero-extended 32-bit shift amount.
define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: sllg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; Check shift amounts that have the largest in-range constant term. We could
; mask the amount instead.
define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: sllg %r2, %r2, 524287(%r3)
; CHECK: br %r14
%add = add i64 %amt, 524287
; Check the next value up, which without masking must use a separate
; addition.
define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: a{{g?}}fi %r3, 524288
; CHECK: sllg %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check cases where 1 is subtracted from the shift amount.
define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: sllg %r2, %r2, -1(%r3)
; CHECK: br %r14
%sub = sub i64 %amt, 1
; Check the lowest value that can be subtracted from the shift amount.
; Again, we could mask the shift amount instead.
define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: sllg %r2, %r2, -524288(%r3)
; CHECK: br %r14
%sub = sub i64 %amt, 524288
; Check the next value down, which without masking must use a separate
; addition.
define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: a{{g?}}fi %r3, -524289
; CHECK: sllg %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check that we don't try to generate "indexed" shifts.
define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
; CHECK: sllg %r2, %r2, 0({{%r[34]}})
; CHECK: br %r14
; Check that the shift amount uses an address register. It cannot be in %r0.
define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: l %r1, 4(%r3)
; CHECK: sllg %r2, %r2, 0(%r1)
; CHECK: br %r14
; Check the low end of the SRLG range.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: srlg %r2, %r2, 1
; CHECK: br %r14
%shift = lshr i64 %a, 1
; Check the high end of the defined SRLG range.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: srlg %r2, %r2, 63
; CHECK: br %r14
%shift = lshr i64 %a, 63
; We don't generate shifts by out-of-range values.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: srlg
; CHECK: br %r14
%shift = lshr i64 %a, 64
; Check variable shifts.
define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: srlg %r2, %r2, 0(%r3)
; CHECK: br %r14
%shift = lshr i64 %a, %amt
; Check shift amounts that have a constant term.
define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: srlg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; ...and again with a sign-extended 32-bit shift amount.
define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: srlg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; ...and now with a zero-extended 32-bit shift amount.
define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: srlg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; Check shift amounts that have the largest in-range constant term. We could
; mask the amount instead.
define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: srlg %r2, %r2, 524287(%r3)
; CHECK: br %r14
%add = add i64 %amt, 524287
; Check the next value up, which without masking must use a separate
; addition.
define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: a{{g?}}fi %r3, 524288
; CHECK: srlg %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check cases where 1 is subtracted from the shift amount.
define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: srlg %r2, %r2, -1(%r3)
; CHECK: br %r14
%sub = sub i64 %amt, 1
; Check the lowest value that can be subtracted from the shift amount.
; Again, we could mask the shift amount instead.
define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: srlg %r2, %r2, -524288(%r3)
; CHECK: br %r14
%sub = sub i64 %amt, 524288
; Check the next value down, which without masking must use a separate
; addition.
define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: a{{g?}}fi %r3, -524289
; CHECK: srlg %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check that we don't try to generate "indexed" shifts.
define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
; CHECK: srlg %r2, %r2, 0({{%r[34]}})
; CHECK: br %r14
; Check that the shift amount uses an address register. It cannot be in %r0.
define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: l %r1, 4(%r3)
; CHECK: srlg %r2, %r2, 0(%r1)
; CHECK: br %r14
; Check the low end of the SRAG range.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: srag %r2, %r2, 1
; CHECK: br %r14
%shift = ashr i64 %a, 1
; Check the high end of the defined SRAG range.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: srag %r2, %r2, 63
; CHECK: br %r14
%shift = ashr i64 %a, 63
; We don't generate shifts by out-of-range values.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: srag
; CHECK: br %r14
%shift = ashr i64 %a, 64
; Check variable shifts.
define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: srag %r2, %r2, 0(%r3)
; CHECK: br %r14
%shift = ashr i64 %a, %amt
; Check shift amounts that have a constant term.
define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: srag %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; ...and again with a sign-extended 32-bit shift amount.
define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: srag %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; ...and now with a zero-extended 32-bit shift amount.
define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: srag %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; Check shift amounts that have the largest in-range constant term. We could
; mask the amount instead.
define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: srag %r2, %r2, 524287(%r3)
; CHECK: br %r14
%add = add i64 %amt, 524287
; Check the next value up, which without masking must use a separate
; addition.
define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: a{{g?}}fi %r3, 524288
; CHECK: srag %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check cases where 1 is subtracted from the shift amount.
define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: srag %r2, %r2, -1(%r3)
; CHECK: br %r14
%sub = sub i64 %amt, 1
; Check the lowest value that can be subtracted from the shift amount.
; Again, we could mask the shift amount instead.
define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: srag %r2, %r2, -524288(%r3)
; CHECK: br %r14
%sub = sub i64 %amt, 524288
; Check the next value down, which without masking must use a separate
; addition.
define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: a{{g?}}fi %r3, -524289
; CHECK: srag %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check that we don't try to generate "indexed" shifts.
define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
; CHECK: srag %r2, %r2, 0({{%r[34]}})
; CHECK: br %r14
; Check that the shift amount uses an address register. It cannot be in %r0.
define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: l %r1, 4(%r3)
; CHECK: srag %r2, %r2, 0(%r1)
; CHECK: br %r14
; Check the low end of the RLLG range.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: rllg %r2, %r2, 1
; CHECK: br %r14
%parta = shl i64 %a, 1
; Check the high end of the defined RLLG range.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: rllg %r2, %r2, 63
; CHECK: br %r14
%parta = shl i64 %a, 63
; We don't generate shifts by out-of-range values.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NOT: rllg
; CHECK: br %r14
%parta = shl i64 %a, 64
; Check variable shifts.
define i64 @f4(i64 %a, i64 %amt) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: rllg %r2, %r2, 0(%r3)
; CHECK: br %r14
%amtb = sub i64 64, %amt
; Check shift amounts that have a constant term.
define i64 @f5(i64 %a, i64 %amt) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: rllg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i64 %amt, 10
; ...and again with a sign-extended 32-bit shift amount.
define i64 @f6(i64 %a, i32 %amt) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: rllg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; ...and now with a zero-extended 32-bit shift amount.
define i64 @f7(i64 %a, i32 %amt) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: rllg %r2, %r2, 10(%r3)
; CHECK: br %r14
%add = add i32 %amt, 10
; Check shift amounts that have the largest in-range constant term. We could
; mask the amount instead.
define i64 @f8(i64 %a, i64 %amt) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: rllg %r2, %r2, 524287(%r3)
; CHECK: br %r14
%add = add i64 %amt, 524287
; Check the next value up, which without masking must use a separate
; addition.
define i64 @f9(i64 %a, i64 %amt) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: a{{g?}}fi %r3, 524288
; CHECK: rllg %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check cases where 1 is subtracted from the shift amount.
define i64 @f10(i64 %a, i64 %amt) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: rllg %r2, %r2, -1(%r3)
; CHECK: br %r14
%suba = sub i64 %amt, 1
; Check the lowest value that can be subtracted from the shift amount.
; Again, we could mask the shift amount instead.
define i64 @f11(i64 %a, i64 %amt) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: rllg %r2, %r2, -524288(%r3)
; CHECK: br %r14
%suba = sub i64 %amt, 524288
; Check the next value down, which without masking must use a separate
; addition.
define i64 @f12(i64 %a, i64 %amt) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: a{{g?}}fi %r3, -524289
; CHECK: rllg %r2, %r2, 0(%r3)
; CHECK: br %r14
; Check that we don't try to generate "indexed" shifts.
define i64 @f13(i64 %a, i64 %b, i64 %c) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: a{{g?}}r {{%r3, %r4|%r4, %r3}}
; CHECK: rllg %r2, %r2, 0({{%r[34]}})
; CHECK: br %r14
; Check that the shift amount uses an address register. It cannot be in %r0.
define i64 @f14(i64 %a, i64 *%ptr) {
-; CHECK: f14:
+; CHECK-LABEL: f14:
; CHECK: l %r1, 4(%r3)
; CHECK: rllg %r2, %r2, 0(%r1)
; CHECK: br %r14
; This function shouldn't spill anything
define void @f1(i32 *%ptr0) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: stmg
; CHECK: aghi %r15, -160
; CHECK-NOT: %r15
; Test a case where at least one i32 load and at least one i32 store
; need spills.
define void @f2(i32 *%ptr0) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
; CHECK: brasl %r14, foo@PLT
; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
; Test a case where at least one i64 load and at least one i64 store
; need spills.
define void @f3(i64 *%ptr0) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
; CHECK: brasl %r14, foo@PLT
; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
; (and are at the time of writing), but it would really be better to use
; MVC for all 10.
define void @f4(float *%ptr0) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mvc [[OFFSET1:16[04]]](4,%r15), [[OFFSET2:[0-9]+]]({{%r[0-9]+}})
; CHECK: brasl %r14, foo@PLT
; CHECK: mvc [[OFFSET2]](4,{{%r[0-9]+}}), [[OFFSET1]](%r15)
; Similarly for f64.
define void @f5(double *%ptr0) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvc 160(8,%r15), [[OFFSET:[0-9]+]]({{%r[0-9]+}})
; CHECK: brasl %r14, foo@PLT
; CHECK: mvc [[OFFSET]](8,{{%r[0-9]+}}), 160(%r15)
; Repeat f2 with atomic accesses. We shouldn't use MVC here.
define void @f6(i32 *%ptr0) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: mvc
; CHECK: br %r14
%ptr1 = getelementptr i32 *%ptr0, i64 2
; ...likewise volatile accesses.
define void @f7(i32 *%ptr0) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK-NOT: mvc
; CHECK: br %r14
%ptr1 = getelementptr i32 *%ptr0, i64 2
; Check that LRL and STRL are not converted.
define void @f8() {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK-NOT: mvc
; CHECK: br %r14
%val0 = load i32 *@g0
; Likewise LGRL and STGRL.
define void @f9() {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK-NOT: mvc
; CHECK: br %r14
%val0 = load i64 *@h0
; [FI0, FI1] -> [FI1, FI2], but applied it in the form FI0 -> FI1 -> FI2,
; so that both operands ended up being the same.
define void @f10() {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: lgrl [[REG:%r[0-9]+]], h9
; CHECK: stg [[REG]], [[VAL9:[0-9]+]](%r15)
; CHECK: brasl %r14, foo@PLT
; This used to generate a no-op MVC. It is very sensitive to spill heuristics.
define void @f11() {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK-NOT: mvc [[OFFSET:[0-9]+]](8,%r15), [[OFFSET]](%r15)
; CHECK: br %r14
entry:
; CHECK-CP: .LCP{{.*}}:
; CHECK-CP: .quad x@NTPOFF
;
-; CHECK-MAIN: foo:
+; CHECK-MAIN-LABEL: foo:
; CHECK-MAIN: ear [[HIGH:%r[0-5]]], %a0
; CHECK-MAIN: sllg %r2, [[HIGH]], 32
; CHECK-MAIN: ear %r2, %a1
; Check that unaligned 2-byte accesses are allowed.
define i16 @f2(i16 *%src, i16 *%dst) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: lh %r2, 0(%r2)
; CHECK: sth %r2, 0(%r3)
; CHECK: br %r14
; Check that unaligned 4-byte accesses are allowed.
define i32 @f3(i32 *%src1, i32 *%src2, i32 *%dst) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: l %r2, 0(%r2)
; CHECK: s %r2, 0(%r3)
; CHECK: st %r2, 0(%r4)
; Check that unaligned 8-byte accesses are allowed.
define i64 @f4(i64 *%src1, i64 *%src2, i64 *%dst) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: lg %r2, 0(%r2)
; CHECK: sg %r2, 0(%r3)
; CHECK: stg %r2, 0(%r4)
; Check XR.
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: xr %r2, %r3
; CHECK: br %r14
%xor = xor i32 %a, %b
; Check the low end of the X range.
define i32 @f2(i32 %a, i32 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: x %r2, 0(%r3)
; CHECK: br %r14
%b = load i32 *%src
; Check the high end of the aligned X range.
define i32 @f3(i32 %a, i32 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: x %r2, 4092(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1023
; Check the next word up, which should use XY instead of X.
define i32 @f4(i32 %a, i32 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xy %r2, 4096(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 1024
; Check the high end of the aligned XY range.
define i32 @f5(i32 %a, i32 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xy %r2, 524284(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 131071
; Check the next word up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f6(i32 %a, i32 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: agfi %r3, 524288
; CHECK: x %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned XY range.
define i32 @f7(i32 %a, i32 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: xy %r2, -4(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -1
; Check the low end of the XY range.
define i32 @f8(i32 %a, i32 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: xy %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i32 *%src, i64 -131072
; Check the next word down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i32 @f9(i32 %a, i32 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: agfi %r3, -524292
; CHECK: x %r2, 0(%r3)
; CHECK: br %r14
; Check that X allows an index.
define i32 @f10(i32 %a, i64 %src, i64 %index) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: x %r2, 4092({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that XY allows an index.
define i32 @f11(i32 %a, i64 %src, i64 %index) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: xy %r2, 4096({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that XORs of spilled values can use X rather than XR.
define i32 @f12(i32 *%ptr0) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: brasl %r14, foo@PLT
; CHECK: x %r2, 16{{[04]}}(%r15)
; CHECK: br %r14
; Check the lowest useful XILF value.
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: xilf %r2, 1
; CHECK: br %r14
%xor = xor i32 %a, 1
; Check the high end of the signed range.
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: xilf %r2, 2147483647
; CHECK: br %r14
%xor = xor i32 %a, 2147483647
; Check the low end of the signed range, which should be treated
; as a positive value.
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xilf %r2, 2147483648
; CHECK: br %r14
%xor = xor i32 %a, -2147483648
; Check the high end of the XILF range.
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xilf %r2, 4294967295
; CHECK: br %r14
%xor = xor i32 %a, 4294967295
; Check XGR.
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: xgr %r2, %r3
; CHECK: br %r14
%xor = xor i64 %a, %b
; Check XG with no displacement.
define i64 @f2(i64 %a, i64 *%src) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: xg %r2, 0(%r3)
; CHECK: br %r14
%b = load i64 *%src
; Check the high end of the aligned XG range.
define i64 @f3(i64 %a, i64 *%src) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xg %r2, 524280(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 65535
; Check the next doubleword up, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f4(i64 %a, i64 *%src) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: agfi %r3, 524288
; CHECK: xg %r2, 0(%r3)
; CHECK: br %r14
; Check the high end of the negative aligned XG range.
define i64 @f5(i64 %a, i64 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xg %r2, -8(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -1
; Check the low end of the XG range.
define i64 @f6(i64 %a, i64 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xg %r2, -524288(%r3)
; CHECK: br %r14
%ptr = getelementptr i64 *%src, i64 -65536
; Check the next doubleword down, which needs separate address logic.
; Other sequences besides this one would be OK.
define i64 @f7(i64 %a, i64 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: agfi %r3, -524296
; CHECK: xg %r2, 0(%r3)
; CHECK: br %r14
; Check that XG allows an index.
define i64 @f8(i64 %a, i64 %src, i64 %index) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: xg %r2, 524280({{%r4,%r3|%r3,%r4}})
; CHECK: br %r14
%add1 = add i64 %src, %index
; Check that XORs of spilled values can use OG rather than OGR.
define i64 @f9(i64 *%ptr0) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: brasl %r14, foo@PLT
; CHECK: xg %r2, 160(%r15)
; CHECK: br %r14
; Check the lowest useful XILF value.
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: xilf %r2, 1
; CHECK: br %r14
%xor = xor i64 %a, 1
; Check the high end of the XILF range.
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: xilf %r2, 4294967295
; CHECK: br %r14
%xor = xor i64 %a, 4294967295
; Check the lowest useful XIHF value, which is one up from the above.
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xihf %r2, 1
; CHECK: br %r14
%xor = xor i64 %a, 4294967296
; Check the next value up again, which needs a combination of XIHF and XILF.
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xihf %r2, 1
; CHECK: xilf %r2, 4294967295
; CHECK: br %r14
; Check the high end of the XIHF range.
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xihf %r2, 4294967295
; CHECK: br %r14
%xor = xor i64 %a, -4294967296
; Check the next value up, which again must use XIHF and XILF.
define i64 @f6(i64 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xihf %r2, 4294967295
; CHECK: xilf %r2, 1
; CHECK: br %r14
; Check full bitwise negation
define i64 @f7(i64 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: xihf %r2, 4294967295
; CHECK: xilf %r2, 4294967295
; CHECK: br %r14
; Check the lowest useful constant, expressed as a signed integer.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: xi 0(%r2), 1
; CHECK: br %r14
%val = load i8 *%ptr
; Check the highest useful constant, expressed as a signed integer.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Check the lowest useful constant, expressed as an unsigned integer.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xi 0(%r2), 1
; CHECK: br %r14
%val = load i8 *%ptr
; Check the highest useful constant, expressed as a unsigned integer.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Check the high end of the XI range.
define void @f5(i8 *%src) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xi 4095(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4095
; Check the next byte up, which should use XIY instead of XI.
define void @f6(i8 *%src) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xiy 4096(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 4096
; Check the high end of the XIY range.
define void @f7(i8 *%src) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: xiy 524287(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 524287
; Check the next byte up, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f8(i8 *%src) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: agfi %r2, 524288
; CHECK: xi 0(%r2), 127
; CHECK: br %r14
; Check the high end of the negative XIY range.
define void @f9(i8 *%src) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: xiy -1(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -1
; Check the low end of the XIY range.
define void @f10(i8 *%src) {
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: xiy -524288(%r2), 127
; CHECK: br %r14
%ptr = getelementptr i8 *%src, i64 -524288
; Check the next byte down, which needs separate address logic.
; Other sequences besides this one would be OK.
define void @f11(i8 *%src) {
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: agfi %r2, -524289
; CHECK: xi 0(%r2), 127
; CHECK: br %r14
; Check that XI does not allow an index
define void @f12(i64 %src, i64 %index) {
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: agr %r2, %r3
; CHECK: xi 4095(%r2), 127
; CHECK: br %r14
; Check that XIY does not allow an index
define void @f13(i64 %src, i64 %index) {
-; CHECK: f13:
+; CHECK-LABEL: f13:
; CHECK: agr %r2, %r3
; CHECK: xiy 4096(%r2), 127
; CHECK: br %r14
; Zero extension to 32 bits, negative constant.
define void @f1(i8 *%ptr) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 64 bits, negative constant.
define void @f2(i8 *%ptr) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 32 bits, positive constant.
define void @f3(i8 *%ptr) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Zero extension to 64 bits, positive constant.
define void @f4(i8 *%ptr) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 32 bits, negative constant.
define void @f5(i8 *%ptr) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 64 bits, negative constant.
define void @f6(i8 *%ptr) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 32 bits, positive constant.
define void @f7(i8 *%ptr) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
; Sign extension to 64 bits, positive constant.
define void @f8(i8 *%ptr) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: xi 0(%r2), 254
; CHECK: br %r14
%val = load i8 *%ptr
@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (%struct.asl_file_t*, i64, i64*)* @t to i8*)], section "llvm.metadata" ; <[1 x i8*]*> [#uses=0]
define i32 @t(%struct.asl_file_t* %s, i64 %off, i64* %out) nounwind optsize {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: adds {{r[0-7]}}, #8
entry:
%val = alloca i64, align 4 ; <i64*> [#uses=3]
; rdar://11331541
define i32 @t(i32 %a) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: asrs [[REG1:(r[0-9]+)]], [[REG2:(r[0-9]+)]], #31
; CHECK: eors [[REG1]], [[REG2]]
%tmp0 = ashr i32 %a, 31
; RUN: llc < %s -march=thumb -mcpu=cortex-m0 | FileCheck %s -check-prefix=V6M
define void @t1() {
-; V6: t1:
+; V6-LABEL: t1:
; V6: blx {{_*}}sync_synchronize
-; V6M: t1:
+; V6M-LABEL: t1:
; V6M: dmb ish
fence seq_cst
ret void
%struct.info = type { i32, i32, i32, i32, i32, i32, i32, i8* }
define void @t1(%struct.state* %v) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: push
; CHECK: add r7, sp, #12
; CHECK: lsls r[[R0:[0-9]+]]
@str215 = external global [2 x i8]
define void @t2(%struct.comment* %vc, i8* %tag, i8* %contents) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: push
; CHECK: add r7, sp, #12
; CHECK: sub sp, #
; RUN: llc < %s -march=thumb | FileCheck %s
define i32 @f1() {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldr r0
%buf = alloca [32 x i32], align 4
%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 0
}
define i32 @f2() {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mov r0
; CHECK: ldrb
%buf = alloca [32 x i8], align 4
}
define i32 @f3() {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ldr r0
%buf = alloca [32 x i32], align 4
%tmp = getelementptr [32 x i32]* %buf, i32 0, i32 32
}
define i32 @f4() {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mov r0
; CHECK: ldrb
%buf = alloca [32 x i8], align 4
; rdar://7268481
define void @t(i8* %a, ...) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: pop {r3}
; CHECK-NEXT: add sp, #12
; CHECK-NEXT: bx r3
; rdar://7268481
define void @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: push {r7}
entry:
call void asm sideeffect alignstack ".long 0xe7ffdefe", ""() nounwind
%tmp1.s = select i1 %tmp, i32 2, i32 3
ret i32 %tmp1.s
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: beq
-; CHECK-EABI: f1:
+; CHECK-EABI-LABEL: f1:
; CHECK-EABI: beq
define i32 @f2(i32 %a.s) {
%tmp1.s = select i1 %tmp, i32 2, i32 3
ret i32 %tmp1.s
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: bgt
-; CHECK-EABI: f2:
+; CHECK-EABI-LABEL: f2:
; CHECK-EABI: bgt
define i32 @f3(i32 %a.s, i32 %b.s) {
%tmp1.s = select i1 %tmp, i32 2, i32 3
ret i32 %tmp1.s
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: blt
-; CHECK-EABI: f3:
+; CHECK-EABI-LABEL: f3:
; CHECK-EABI: blt
define i32 @f4(i32 %a.s, i32 %b.s) {
%tmp1.s = select i1 %tmp, i32 2, i32 3
ret i32 %tmp1.s
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ble
-; CHECK-EABI: f4:
+; CHECK-EABI-LABEL: f4:
; CHECK-EABI: ble
define i32 @f5(i32 %a.u, i32 %b.u) {
%tmp1.s = select i1 %tmp, i32 2, i32 3
ret i32 %tmp1.s
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: bls
-; CHECK-EABI: f5:
+; CHECK-EABI-LABEL: f5:
; CHECK-EABI: bls
define i32 @f6(i32 %a.u, i32 %b.u) {
%tmp1.s = select i1 %tmp, i32 2, i32 3
ret i32 %tmp1.s
}
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: bhi
-; CHECK-EABI: f6:
+; CHECK-EABI-LABEL: f6:
; CHECK-EABI: bhi
define double @f7(double %a, double %b) {
%tmp1 = select i1 %tmp, double -1.000e+00, double %b
ret double %tmp1
}
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: blt
; CHECK: blt
; CHECK: __ltdf2
-; CHECK-EABI: f7:
+; CHECK-EABI-LABEL: f7:
; CHECK-EABI: __aeabi_dcmplt
; CHECK-EABI: bne
; CHECK-EABI: bne
define void @t() nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: trap
call void @llvm.trap()
unreachable
define i32 @t(i32, ...) nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: add r7, sp, #12
%1 = load i8** undef, align 4 ; <i8*> [#uses=3]
%2 = getelementptr i8* %1, i32 4 ; <i8*> [#uses=1]
@sep = external global [20 x i32] ; <[20 x i32]*> [#uses=1]
define void @main(i32 %argc, i8** %argv) noreturn nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: ldrb
entry:
%nb.i.i.i = alloca [25 x i8], align 1 ; <[25 x i8]*> [#uses=0]
define hidden i32 @__gcov_execlp(i8* %path, i8* %arg, ...) nounwind {
entry:
-; CHECK: __gcov_execlp:
+; CHECK-LABEL: __gcov_execlp:
; CHECK: sub sp, #8
; CHECK: push
; CHECK: add r7, sp, #4
@getNeighbour = external global void (i32, i32, i32, i32, %struct.pix_pos*)*, align 4 ; <void (i32, i32, i32, i32, %struct.pix_pos*)**> [#uses=2]
define void @t() nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: it eq
; CHECK-NEXT: cmpeq
entry:
define weak arm_aapcs_vfpcc i32 @_ZNKSs7compareERKSs(%"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %this, %"struct.std::basic_string<char,std::char_traits<char>,std::allocator<char> >"* %__str) {
-; CHECK: _ZNKSs7compareERKSs:
+; CHECK-LABEL: _ZNKSs7compareERKSs:
; CHECK: it eq
; CHECK-NEXT: subeq{{(.w)?}} r0, r{{[0-9]+}}, r{{[0-9]+}}
; CHECK-NEXT: pop.w
define void @t() nounwind ssp {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
%size = mul i32 8, 2
; CHECK: subs r0, #16
; CHECK: mov sp, r0
define internal fastcc i32 @Callee(i32 %i) nounwind {
entry:
-; CHECK: Callee:
+; CHECK-LABEL: Callee:
; CHECK: push
; CHECK: mov r4, sp
; CHECK: sub.w [[R12:r[0-9]+]], r4, #1000
declare i32 @__sprintf_chk(i8*, i32, i32, i8*, ...) nounwind
define i32 @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
bb.nph:
br label %bb
declare void @bar() nounwind optsize
define void @foo() nounwind optsize {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: push
; CHECK: mov r7, sp
; CHECK: sub sp, #4
define i32 @t() nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: sub sp, #12
; CHECK-NOT: sub
; CHECK: add r0, sp, #4
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
define hidden fastcc void @rdictionary_lookup(%struct.Dict_node_struct* %dn, i8* nocapture %s) nounwind ssp {
-; CHECK: rdictionary_lookup:
+; CHECK-LABEL: rdictionary_lookup:
entry:
br label %tailrecurse
%3 = fadd <4 x float> undef, %2
store <4 x float> %3, <4 x float>* undef, align 4
br label %bb8
-; CHECK: RotateStarsFP_Vec:
+; CHECK-LABEL: RotateStarsFP_Vec:
; CHECK: vld1.64
}
define i64 @f1(i64 %a, i64 %b) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: subs r0, r0, r2
; CHECK: sbcs r1, r3
%tmp = sub i64 %a, %b
define i64 @f2(i64 %a, i64 %b) {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: adds r0, r0, r0
; CHECK: adcs r1, r1
; CHECK: subs r0, r0, r2
; rdar://12559385
define i64 @f3(i32 %vi) {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: movw [[REG:r[0-9]+]], #36102
; CHECK: sbcs r{{[0-9]+}}, [[REG]]
%v0 = zext i32 %vi to i64
; RUN: llc < %s -mtriple=thumbv7-apple-darwin9 -mcpu=cortex-a8 | FileCheck %s
define void @fht(float* nocapture %fz, i16 signext %n) nounwind {
-; CHECK: fht:
+; CHECK-LABEL: fht:
entry:
br label %bb5
; Check generated signed and unsigned multiply accumulate long.
define i64 @MACLongTest1(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest1:
+;CHECK-LABEL: MACLongTest1:
;CHECK: umlal
%conv = zext i32 %a to i64
%conv1 = zext i32 %b to i64
}
define i64 @MACLongTest2(i32 %a, i32 %b, i64 %c) {
-;CHECK: MACLongTest2:
+;CHECK-LABEL: MACLongTest2:
;CHECK: smlal
%conv = sext i32 %a to i64
%conv1 = sext i32 %b to i64
}
define i64 @MACLongTest3(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest3:
+;CHECK-LABEL: MACLongTest3:
;CHECK: umlal
%conv = zext i32 %b to i64
%conv1 = zext i32 %a to i64
}
define i64 @MACLongTest4(i32 %a, i32 %b, i32 %c) {
-;CHECK: MACLongTest4:
+;CHECK-LABEL: MACLongTest4:
;CHECK: smlal
%conv = sext i32 %b to i64
%conv1 = sext i32 %a to i64
@array = external global i32* ; <i32**> [#uses=1]
define void @t() nounwind optsize {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: mov{{.*}}, #1000
entry:
%.pre = load i32* @G, align 4 ; <i32> [#uses=1]
define void @t1(i32* nocapture %vals, i32 %c) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: bxeq lr
%0 = icmp eq i32 %c, 0 ; <i1> [#uses=1]
; rdar://8001136
define void @t2(i8* %ptr1, i8* %ptr2) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: vmov.f32 q{{.*}}, #1.000000e+00
br i1 undef, label %bb1, label %bb2
; rdar://8241368
; isel should not fold immediate into eor's which would have prevented LICM.
define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone {
-; CHECK: t3:
+; CHECK-LABEL: t3:
bb.nph:
; CHECK: bb.nph
; CHECK: movw {{(r[0-9])|(lr)}}, #32768
define i32 @t1(i32 %v) nounwind readnone {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: add.w r0, r0, r0, lsl #3
%0 = mul i32 %v, 9
ret i32 %0
define i32 @t2(i32 %v) nounwind readnone {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: rsb r0, r0, r0, lsl #3
%0 = mul i32 %v, 7
ret i32 %0
define hidden i32 @atexit(void ()* %func) nounwind {
entry:
-; CHECK: atexit:
+; CHECK-LABEL: atexit:
; CHECK: add r0, pc
%r = alloca %struct.one_atexit_routine, align 4 ; <%struct.one_atexit_routine*> [#uses=3]
%0 = getelementptr %struct.one_atexit_routine* %r, i32 0, i32 0, i32 0 ; <void ()**> [#uses=1]
; 734439407618 = 0x000000ab00000002
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: adds r0, #2
%tmp = add i64 %a, 734439407618
ret i64 %tmp
; 5066626890203138 = 0x0012001200000002
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: adds r0, #2
%tmp = add i64 %a, 5066626890203138
ret i64 %tmp
; 3747052064576897026 = 0x3400340000000002
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: adds r0, #2
%tmp = add i64 %a, 3747052064576897026
ret i64 %tmp
; 6221254862626095106 = 0x5656565600000002
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: adds r0, #2
%tmp = add i64 %a, 6221254862626095106
ret i64 %tmp
; 287104476244869122 = 0x03fc000000000002
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: adds r0, #2
%tmp = add i64 %a, 287104476244869122
ret i64 %tmp
}
define i64 @f6(i64 %a, i64 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: adds r0, r0, r2
%tmp = add i64 %a, %b
ret i64 %tmp
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @t2ADDrc_255(i32 %lhs) {
-; CHECK: t2ADDrc_255:
+; CHECK-LABEL: t2ADDrc_255:
; CHECK-NOT: bx lr
; CHECK: add{{.*}} #255
; CHECK: bx lr
}
define i32 @t2ADDrc_256(i32 %lhs) {
-; CHECK: t2ADDrc_256:
+; CHECK-LABEL: t2ADDrc_256:
; CHECK-NOT: bx lr
; CHECK: add{{.*}} #256
; CHECK: bx lr
}
define i32 @t2ADDrc_257(i32 %lhs) {
-; CHECK: t2ADDrc_257:
+; CHECK-LABEL: t2ADDrc_257:
; CHECK-NOT: bx lr
; CHECK: add{{.*}} #257
; CHECK: bx lr
}
define i32 @t2ADDrc_4094(i32 %lhs) {
-; CHECK: t2ADDrc_4094:
+; CHECK-LABEL: t2ADDrc_4094:
; CHECK-NOT: bx lr
; CHECK: add{{.*}} #4094
; CHECK: bx lr
}
define i32 @t2ADDrc_4095(i32 %lhs) {
-; CHECK: t2ADDrc_4095:
+; CHECK-LABEL: t2ADDrc_4095:
; CHECK-NOT: bx lr
; CHECK: add{{.*}} #4095
; CHECK: bx lr
}
define i32 @t2ADDrc_4096(i32 %lhs) {
-; CHECK: t2ADDrc_4096:
+; CHECK-LABEL: t2ADDrc_4096:
; CHECK-NOT: bx lr
; CHECK: add{{.*}} #4096
; CHECK: bx lr
}
define i32 @t2ADDrr(i32 %lhs, i32 %rhs) {
-; CHECK: t2ADDrr:
+; CHECK-LABEL: t2ADDrr:
; CHECK-NOT: bx lr
; CHECK: add
; CHECK: bx lr
}
define i32 @t2ADDrs(i32 %lhs, i32 %rhs) {
-; CHECK: t2ADDrs:
+; CHECK-LABEL: t2ADDrs:
; CHECK-NOT: bx lr
; CHECK: add{{.*}} lsl #8
; CHECK: bx lr
; 171 = 0x000000ab
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: adds r0, #171
%tmp = add i32 %a, 171
ret i32 %tmp
; 1179666 = 0x00120012
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: add.w r0, r0, #1179666
%tmp = add i32 %a, 1179666
ret i32 %tmp
; 872428544 = 0x34003400
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: add.w r0, r0, #872428544
%tmp = add i32 %a, 872428544
ret i32 %tmp
; 1448498774 = 0x56565656
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: add.w r0, r0, #1448498774
%tmp = add i32 %a, 1448498774
ret i32 %tmp
; 510 = 0x000001fe
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: add.w r0, r0, #510
%tmp = add i32 %a, 510
ret i32 %tmp
ret i32 %tmp
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: addw r0, r0, #4095
; 171 = 0x000000ab
define i64 @f1(i64 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: adds r0, #171
; CHECK: adc r1, r1, #0
%tmp = add i64 %a, 171
; 1179666 = 0x00120012
define i64 @f2(i64 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: adds.w r0, r0, #1179666
; CHECK: adc r1, r1, #0
%tmp = add i64 %a, 1179666
; 872428544 = 0x34003400
define i64 @f3(i64 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: adds.w r0, r0, #872428544
; CHECK: adc r1, r1, #0
%tmp = add i64 %a, 872428544
; 1448498774 = 0x56565656
define i64 @f4(i64 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: adds.w r0, r0, #1448498774
; CHECK: adc r1, r1, #0
%tmp = add i64 %a, 1448498774
; 66846720 = 0x03fc0000
define i64 @f5(i64 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: adds.w r0, r0, #66846720
; CHECK: adc r1, r1, #0
%tmp = add i64 %a, 66846720
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: add r0, r1
%tmp = add i32 %a, %b
ret i32 %tmp
}
define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: add.w r0, r0, r1, lsl #5
%tmp = shl i32 %b, 5
%tmp1 = add i32 %a, %tmp
}
define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: add.w r0, r0, r1, lsr #6
%tmp = lshr i32 %b, 6
%tmp1 = add i32 %a, %tmp
}
define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: add.w r0, r0, r1, asr #7
%tmp = ashr i32 %b, 7
%tmp1 = add i32 %a, %tmp
}
define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: add.w r0, r0, r0, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: adds r0, r0, r2
; CHECK: adcs r1, r3
%tmp = add i64 %a, %b
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ands r0, r1
%tmp = and i32 %a, %b
ret i32 %tmp
}
define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: and.w r0, r0, r1, lsl #5
%tmp = shl i32 %b, 5
%tmp1 = and i32 %a, %tmp
}
define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: and.w r0, r0, r1, lsr #6
%tmp = lshr i32 %b, 6
%tmp1 = and i32 %a, %tmp
}
define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: and.w r0, r0, r1, asr #7
%tmp = ashr i32 %b, 7
%tmp1 = and i32 %a, %tmp
}
define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: and.w r0, r0, r0, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
%tmp = and i32 %a, 171
ret i32 %tmp
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: and r0, r0, #171
; 1179666 = 0x00120012
%tmp = and i32 %a, 1179666
ret i32 %tmp
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: and r0, r0, #1179666
; 872428544 = 0x34003400
%tmp = and i32 %a, 872428544
ret i32 %tmp
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: and r0, r0, #872428544
; 1448498774 = 0x56565656
%tmp = and i32 %a, 1448498774
ret i32 %tmp
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: bic r0, r0, #-1448498775
; 66846720 = 0x03fc0000
%tmp = and i32 %a, 66846720
ret i32 %tmp
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: and r0, r0, #66846720
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: asrs r0, r1
%tmp = ashr i32 %a, %b
ret i32 %tmp
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: asrs r0, r0, #17
%tmp = ashr i32 %a, 17
ret i32 %tmp
; happen and we get actual branches.
define i32 @t1(i32 %a, i32 %b, i32 %c) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: cbz
%tmp2 = icmp eq i32 %a, 0
br i1 %tmp2, label %cond_false, label %cond_true
; 4278190095 = 0xff00000f
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: bfc r
%tmp = and i32 %a, 4278190095
ret i32 %tmp
; 4286578688 = 0xff800000
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: bfc r
%tmp = and i32 %a, 4286578688
ret i32 %tmp
; 4095 = 0x00000fff
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: bfc r
%tmp = and i32 %a, 4095
ret i32 %tmp
; 2147483646 = 0x7ffffffe not implementable w/ BFC
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
%tmp = and i32 %a, 2147483646
ret i32 %tmp
}
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: bics r0, r1
%tmp = xor i32 %b, 4294967295
%tmp1 = and i32 %a, %tmp
}
define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: bics r0, r1
%tmp = xor i32 %b, 4294967295
%tmp1 = and i32 %tmp, %a
}
define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: bics r0, r1
%tmp = xor i32 4294967295, %b
%tmp1 = and i32 %a, %tmp
}
define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: bics r0, r1
%tmp = xor i32 4294967295, %b
%tmp1 = and i32 %tmp, %a
}
define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: bic.w r0, r0, r1, lsl #5
%tmp = shl i32 %b, 5
%tmp1 = xor i32 4294967295, %tmp
}
define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: bic.w r0, r0, r1, lsr #6
%tmp = lshr i32 %b, 6
%tmp1 = xor i32 %tmp, 4294967295
}
define i32 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: bic.w r0, r0, r1, asr #7
%tmp = ashr i32 %b, 7
%tmp1 = xor i32 %tmp, 4294967295
}
define i32 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: bic.w r0, r0, r0, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
%tmp = and i32 %a, 4294967108
ret i32 %tmp
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: bic r0, r0, #187
}
%tmp = and i32 %a, 4283826005
ret i32 %tmp
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: bic r0, r0, #11141290
}
define i32 @f11(i32 %a) {
%tmp = and i32 %a, 872363007
ret i32 %tmp
-; CHECK: f11:
+; CHECK-LABEL: f11:
; CHECK: bic r0, r0, #-872363008
}
define i32 @f12(i32 %a) {
%tmp = and i32 %a, 4293853183
ret i32 %tmp
-; CHECK: f12:
+; CHECK-LABEL: f12:
; CHECK: bic r0, r0, #1114112
}
define i32 @f1(i32 %a, i32 %b, i32* %v) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: bne LBB
%tmp = icmp eq i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
define i32 @f2(i32 %a, i32 %b, i32* %v) {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: bge LBB
%tmp = icmp slt i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
define i32 @f3(i32 %a, i32 %b, i32* %v) {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: bhs LBB
%tmp = icmp ult i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
define i32 @f4(i32 %a, i32 %b, i32* %v) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: blo LBB
%tmp = icmp uge i32 %a, %b ; <i1> [#uses=1]
br i1 %tmp, label %cond_true, label %return
declare void @g(i32, i32, i32, i32)
define void @f() {
-; DARWIN: f:
+; DARWIN-LABEL: f:
; DARWIN: blx _g
-; LINUX: f:
+; LINUX-LABEL: f:
; LINUX: bl g
tail call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
define void @h() {
-; DARWIN: h:
+; DARWIN-LABEL: h:
; DARWIN: bx r0 @ TAILCALL
-; LINUX: h:
+; LINUX-LABEL: h:
; LINUX: bx r0 @ TAILCALL
%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
%tmp.upgrd.2 = tail call i32 %tmp( ) ; <i32> [#uses=0]
}
define void @j() {
-; DARWIN: j:
+; DARWIN-LABEL: j:
; DARWIN: b.w _f @ TAILCALL
-; LINUX: j:
+; LINUX-LABEL: j:
; LINUX: b.w f @ TAILCALL
tail call void @f()
ret void
declare void @g(i32, i32, i32, i32)
define void @f() {
-; DARWIN: f:
+; DARWIN-LABEL: f:
; DARWIN: blx _g
-; LINUX: f:
+; LINUX-LABEL: f:
; LINUX: bl g
call void @g( i32 1, i32 2, i32 3, i32 4 )
ret void
}
define void @h() {
-; DARWIN: h:
+; DARWIN-LABEL: h:
; DARWIN: blx r0
-; LINUX: h:
+; LINUX-LABEL: h:
; LINUX: blx r0
%tmp = load i32 ()** @t ; <i32 ()*> [#uses=1]
%tmp.upgrd.2 = call i32 %tmp( ) ; <i32> [#uses=0]
; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7 | FileCheck %s
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: clz r
%tmp = tail call i32 @llvm.ctlz.i32(i32 %a, i1 true)
ret i32 %tmp
%tmp = icmp ne i32 %a, %nb
ret i1 %tmp
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cmn {{.*}}, r1
define i1 @f2(i32 %a, i32 %b) {
%tmp = icmp ne i32 %nb, %a
ret i1 %tmp
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cmn {{.*}}, r1
define i1 @f3(i32 %a, i32 %b) {
%tmp = icmp eq i32 %a, %nb
ret i1 %tmp
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cmn {{.*}}, r1
define i1 @f4(i32 %a, i32 %b) {
%tmp = icmp eq i32 %nb, %a
ret i1 %tmp
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cmn {{.*}}, r1
define i1 @f5(i32 %a, i32 %b) {
%tmp1 = icmp eq i32 %nb, %a
ret i1 %tmp1
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cmn.w {{.*}}, r1, lsl #5
define i1 @f6(i32 %a, i32 %b) {
%tmp1 = icmp ne i32 %nb, %a
ret i1 %tmp1
}
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cmn.w {{.*}}, r1, lsr #6
define i1 @f7(i32 %a, i32 %b) {
%tmp1 = icmp eq i32 %a, %nb
ret i1 %tmp1
}
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cmn.w {{.*}}, r1, asr #7
define i1 @f8(i32 %a, i32 %b) {
%tmp1 = icmp ne i32 %a, %nb
ret i1 %tmp1
}
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cmn.w {{.*}}, {{.*}}, ror #8
!0 = metadata !{i32 81}
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cmn.w r0, r1
; -0x000000bb = 4294967109
define i1 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cmn.w {{r.*}}, #187
%tmp = icmp ne i32 %a, 4294967109
ret i1 %tmp
; -0x00aa00aa = 4283826006
define i1 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cmn.w {{r.*}}, #11141290
%tmp = icmp eq i32 %a, 4283826006
ret i1 %tmp
; -0xcc00cc00 = 872363008
define i1 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cmn.w {{r.*}}, #-872363008
%tmp = icmp ne i32 %a, 872363008
ret i1 %tmp
; -0x00110000 = 4293853184
define i1 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cmn.w {{r.*}}, #1114112
%tmp = icmp eq i32 %a, 4293853184
ret i1 %tmp
; 0x000000bb = 187
define i1 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cmp {{.*}}, #187
%tmp = icmp ne i32 %a, 187
ret i1 %tmp
; 0x00aa00aa = 11141290
define i1 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cmp.w {{.*}}, #11141290
%tmp = icmp eq i32 %a, 11141290
ret i1 %tmp
; 0xcc00cc00 = 3422604288
define i1 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: cmp.w {{.*}}, #-872363008
%tmp = icmp ne i32 %a, 3422604288
ret i1 %tmp
; 0xdddddddd = 3722304989
define i1 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: cmp.w {{.*}}, #-572662307
%tmp = icmp ne i32 %a, 3722304989
ret i1 %tmp
; 0x00110000 = 1114112
define i1 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: cmp.w {{.*}}, #1114112
%tmp = icmp eq i32 %a, 1114112
ret i1 %tmp
; Check that we don't do an invalid (a > b) --> !(a < b + 1) transform.
;
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK-NOT: cmp.w {{.*}}, #-2147483648
; CHECK: bx lr
define i32 @f6(i32 %a) {
; test as 'mov.w r0, #0'.
define i1 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cmp {{.*}}, r1
%tmp = icmp ne i32 %a, %b
ret i1 %tmp
}
define i1 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cmp {{.*}}, r1
%tmp = icmp eq i32 %a, %b
ret i1 %tmp
}
define i1 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: cmp.w {{.*}}, r1, lsl #5
%tmp = shl i32 %b, 5
%tmp1 = icmp eq i32 %tmp, %a
}
define i1 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: cmp.w {{.*}}, r1, lsr #6
%tmp = lshr i32 %b, 6
%tmp1 = icmp ne i32 %tmp, %a
}
define i1 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: cmp.w {{.*}}, r1, asr #7
%tmp = ashr i32 %b, 7
%tmp1 = icmp eq i32 %a, %tmp
}
define i1 @f9(i32 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: cmp.w {{.*}}, {{.*}}, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: eors r0, r1
%tmp = xor i32 %a, %b
ret i32 %tmp
}
define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: eors r0, r1
%tmp = xor i32 %b, %a
ret i32 %tmp
}
define i32 @f2b(i32 %a, i32 %b, i32 %c) {
-; CHECK: f2b:
+; CHECK-LABEL: f2b:
; CHECK: eor.w r0, r1, r2
%tmp = xor i32 %b, %c
ret i32 %tmp
}
define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: eor.w r0, r0, r1, lsl #5
%tmp = shl i32 %b, 5
%tmp1 = xor i32 %a, %tmp
}
define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: eor.w r0, r0, r1, lsr #6
%tmp = lshr i32 %b, 6
%tmp1 = xor i32 %tmp, %a
}
define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: eor.w r0, r0, r1, asr #7
%tmp = ashr i32 %b, 7
%tmp1 = xor i32 %a, %tmp
}
define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: eor.w r0, r0, r0, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
; 0x000000bb = 187
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: eor {{.*}}#187
%tmp = xor i32 %a, 187
ret i32 %tmp
; 0x00aa00aa = 11141290
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: eor {{.*}}#11141290
%tmp = xor i32 %a, 11141290
ret i32 %tmp
; 0xcc00cc00 = 3422604288
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: eor {{.*}}#-872363008
%tmp = xor i32 %a, 3422604288
ret i32 %tmp
; 0xdddddddd = 3722304989
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: eor {{.*}}#-572662307
%tmp = xor i32 %a, 3722304989
ret i32 %tmp
; 0x00110000 = 1114112
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: eor {{.*}}#1114112
%tmp = xor i32 %a, 1114112
ret i32 %tmp
; XFAIL: *
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: it ne
; CHECK: cmpne
switch i32 %c, label %cond_next [
; FIXME: Check for # of unconditional branch after adding branch folding post ifcvt.
define i32 @t2(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: ite gt
; CHECK: subgt
; CHECK: suble
; Tail call prevents use of ifcvt in this one. Seems like a win though.
define void @t3(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK-NOT: it lt
; CHECK-NOT: poplt
; CHECK: b.w _foo @ TAILCALL
; RUN: llc < %s -mtriple=thumbv7-apple-darwin | FileCheck %s
define i32 @t1(i32 %a, i32 %b, i32 %c, i32 %d) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: ittt ne
; CHECK: cmpne
; CHECK: addne
define i32 @t2(i32 %a, i32 %b) nounwind {
entry:
; Do not if-convert when branches go to the different loops.
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK-NOT: ite gt
; CHECK-NOT: subgt
; CHECK-NOT: suble
define void @t3(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: itt ge
; CHECK: movge r0, r1
; CHECK: blge _foo
define void @foo(i32 %X, i32 %Y) {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: it ne
; CHECK: cmpne
; CHECK: it hi
define fastcc i32 @CountTree(%struct.quad_struct* %tree) {
entry:
-; CHECK: CountTree:
+; CHECK-LABEL: CountTree:
; CHECK: itt eq
; CHECK: moveq
; CHECK: popeq
define fastcc void @t1(%struct.SString* %word, i8 signext %c) {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: it ne
; CHECK: popne {r7, pc}
%tmp1 = icmp eq %struct.SString* %word, null ; <i1> [#uses=1]
define fastcc void @t2() nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: cmp r0, #0
; CHECK: %growMapping.exit
br i1 undef, label %bb.i.i3, label %growMapping.exit
@X = external global [0 x i32] ; <[0 x i32]*> [#uses=5]
define i32 @t1() {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: push {r7, lr}
; CHECK: pop {r7, pc}
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 0) ; <i32> [#uses=1]
}
define i32 @t2() {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: push {r7, lr}
; CHECK: ldm
; CHECK: pop {r7, pc}
}
define i32 @t3() {
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: push {r7, lr}
; CHECK: pop {r7, pc}
%tmp = load i32* getelementptr ([0 x i32]* @X, i32 0, i32 1) ; <i32> [#uses=1]
define i32 @f1(i32* %v) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldr r0, [r0]
%tmp = load i32* %v
ret i32 %tmp
define i32 @f2(i32* %v) {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldr.w r0, [r0, #4092]
%tmp2 = getelementptr i32* %v, i32 1023
%tmp = load i32* %tmp2
define i32 @f3(i32* %v) {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov.w r1, #4096
; CHECK: ldr r0, [r0, r1]
%tmp2 = getelementptr i32* %v, i32 1024
define i32 @f4(i32 %base) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ldr r0, [r0, #-128]
%tmp1 = sub i32 %base, 128
%tmp2 = inttoptr i32 %tmp1 to i32*
define i32 @f5(i32 %base, i32 %offset) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldr r0, [r0, r1]
%tmp1 = add i32 %base, %offset
%tmp2 = inttoptr i32 %tmp1 to i32*
define i32 @f6(i32 %base, i32 %offset) {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ldr.w r0, [r0, r1, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
define i32 @f7(i32 %base, i32 %offset) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lsrs r1, r1, #2
; CHECK: ldr r0, [r0, r1]
define i8 @f1(i8* %v) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldrb r0, [r0]
%tmp = load i8* %v
ret i8 %tmp
define i8 @f2(i8* %v) {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldrb r0, [r0, #-1]
%tmp2 = getelementptr i8* %v, i8 1023
%tmp = load i8* %tmp2
define i8 @f3(i32 %base) {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov.w r1, #4096
; CHECK: ldrb r0, [r0, r1]
%tmp1 = add i32 %base, 4096
define i8 @f4(i32 %base) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ldrb r0, [r0, #-128]
%tmp1 = sub i32 %base, 128
%tmp2 = inttoptr i32 %tmp1 to i8*
define i8 @f5(i32 %base, i32 %offset) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldrb r0, [r0, r1]
%tmp1 = add i32 %base, %offset
%tmp2 = inttoptr i32 %tmp1 to i8*
define i8 @f6(i32 %base, i32 %offset) {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ldrb.w r0, [r0, r1, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
define i8 @f7(i32 %base, i32 %offset) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lsrs r1, r1, #2
; CHECK: ldrb r0, [r0, r1]
%tmp1 = lshr i32 %offset, 2
define i16 @f1(i16* %v) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldrh r0, [r0]
%tmp = load i16* %v
ret i16 %tmp
define i16 @f2(i16* %v) {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldrh.w r0, [r0, #2046]
%tmp2 = getelementptr i16* %v, i16 1023
%tmp = load i16* %tmp2
define i16 @f3(i16* %v) {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov.w r1, #4096
; CHECK: ldrh r0, [r0, r1]
%tmp2 = getelementptr i16* %v, i16 2048
define i16 @f4(i32 %base) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ldrh r0, [r0, #-128]
%tmp1 = sub i32 %base, 128
%tmp2 = inttoptr i32 %tmp1 to i16*
define i16 @f5(i32 %base, i32 %offset) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldrh r0, [r0, r1]
%tmp1 = add i32 %base, %offset
%tmp2 = inttoptr i32 %tmp1 to i16*
define i16 @f6(i32 %base, i32 %offset) {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: ldrh.w r0, [r0, r1, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
define i16 @f7(i32 %base, i32 %offset) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lsrs r1, r1, #2
; CHECK: ldrh r0, [r0, r1]
%tmp1 = lshr i32 %offset, 2
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lsls r0, r0, #5
%tmp = shl i32 %a, 5
ret i32 %tmp
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lsls r0, r1
%tmp = shl i32 %a, %b
ret i32 %tmp
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lsrs r0, r0, #13
%tmp = lshr i32 %a, 13
ret i32 %tmp
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: lsrs r0, r1
%tmp = lshr i32 %a, %b
ret i32 %tmp
%tmp2 = add i32 %c, %tmp1
ret i32 %tmp2
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mla r0, r0, r1, r2
-; NO_MULOPS: f1:
+; NO_MULOPS-LABEL: f1:
; NO_MULOPS: muls r0, r1, r0
; NO_MULOPS-NEXT: add r0, r2
%tmp2 = add i32 %tmp1, %c
ret i32 %tmp2
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mla r0, r0, r1, r2
-; NO_MULOPS: f2:
+; NO_MULOPS-LABEL: f2:
; NO_MULOPS: muls r0, r1, r0
; NO_MULOPS-NEXT: add r0, r2
%tmp2 = sub i32 %c, %tmp1
ret i32 %tmp2
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mls r0, r0, r1, r2
; sub doesn't commute, so no mls for this one
%tmp2 = sub i32 %tmp1, %c
ret i32 %tmp2
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: muls r0, r1, r0
; var 2.1 - 0x00ab00ab
define i32 @t2_const_var2_1_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_1:
+;CHECK-LABEL: t2_const_var2_1_ok_1:
;CHECK: add.w r0, r0, #11206827
%ret = add i32 %lhs, 11206827 ; 0x00ab00ab
ret i32 %ret
}
define i32 @t2_const_var2_1_ok_2(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_2:
+;CHECK-LABEL: t2_const_var2_1_ok_2:
;CHECK: add.w r0, r0, #11206656
;CHECK: adds r0, #187
%ret = add i32 %lhs, 11206843 ; 0x00ab00bb
}
define i32 @t2_const_var2_1_ok_3(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_3:
+;CHECK-LABEL: t2_const_var2_1_ok_3:
;CHECK: add.w r0, r0, #11206827
;CHECK: add.w r0, r0, #16777216
%ret = add i32 %lhs, 27984043 ; 0x01ab00ab
}
define i32 @t2_const_var2_1_ok_4(i32 %lhs) {
-;CHECK: t2_const_var2_1_ok_4:
+;CHECK-LABEL: t2_const_var2_1_ok_4:
;CHECK: add.w r0, r0, #16777472
;CHECK: add.w r0, r0, #11206827
%ret = add i32 %lhs, 27984299 ; 0x01ab01ab
}
define i32 @t2_const_var2_1_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_1_fail_1:
+;CHECK-LABEL: t2_const_var2_1_fail_1:
;CHECK: movw r1, #43777
;CHECK: movt r1, #427
;CHECK: add r0, r1
; var 2.2 - 0xab00ab00
define i32 @t2_const_var2_2_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_1:
+;CHECK-LABEL: t2_const_var2_2_ok_1:
;CHECK: add.w r0, r0, #-1426019584
%ret = add i32 %lhs, 2868947712 ; 0xab00ab00
ret i32 %ret
}
define i32 @t2_const_var2_2_ok_2(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_2:
+;CHECK-LABEL: t2_const_var2_2_ok_2:
;CHECK: add.w r0, r0, #2868903936
;CHECK: add.w r0, r0, #47616
%ret = add i32 %lhs, 2868951552 ; 0xab00ba00
}
define i32 @t2_const_var2_2_ok_3(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_3:
+;CHECK-LABEL: t2_const_var2_2_ok_3:
;CHECK: add.w r0, r0, #2868947712
;CHECK: adds r0, #16
%ret = add i32 %lhs, 2868947728 ; 0xab00ab10
}
define i32 @t2_const_var2_2_ok_4(i32 %lhs) {
-;CHECK: t2_const_var2_2_ok_4:
+;CHECK-LABEL: t2_const_var2_2_ok_4:
;CHECK: add.w r0, r0, #2868947712
;CHECK: add.w r0, r0, #1048592
%ret = add i32 %lhs, 2869996304 ; 0xab10ab10
}
define i32 @t2_const_var2_2_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_2_fail_1:
+;CHECK-LABEL: t2_const_var2_2_fail_1:
;CHECK: movw r1, #43792
;CHECK: movt r1, #4267
;CHECK: add r0, r1
; var 2.3 - 0xabababab
define i32 @t2_const_var2_3_ok_1(i32 %lhs) {
-;CHECK: t2_const_var2_3_ok_1:
+;CHECK-LABEL: t2_const_var2_3_ok_1:
;CHECK: add.w r0, r0, #-1414812757
%ret = add i32 %lhs, 2880154539 ; 0xabababab
ret i32 %ret
}
define i32 @t2_const_var2_3_fail_1(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_1:
+;CHECK-LABEL: t2_const_var2_3_fail_1:
;CHECK: movw r1, #43962
;CHECK: movt r1, #43947
;CHECK: add r0, r1
}
define i32 @t2_const_var2_3_fail_2(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_2:
+;CHECK-LABEL: t2_const_var2_3_fail_2:
;CHECK: movw r1, #47787
;CHECK: movt r1, #43947
;CHECK: add r0, r1
}
define i32 @t2_const_var2_3_fail_3(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_3:
+;CHECK-LABEL: t2_const_var2_3_fail_3:
;CHECK: movw r1, #43947
;CHECK: movt r1, #43962
;CHECK: add r0, r1
}
define i32 @t2_const_var2_3_fail_4(i32 %lhs) {
-;CHECK: t2_const_var2_3_fail_4:
+;CHECK-LABEL: t2_const_var2_3_fail_4:
;CHECK: movw r1, #43947
;CHECK: movt r1, #47787
;CHECK: add r0, r1
; var 3 - 0x0F000000
define i32 @t2_const_var3_1_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_1_ok_1:
+;CHECK-LABEL: t2_const_var3_1_ok_1:
;CHECK: add.w r0, r0, #251658240
%ret = add i32 %lhs, 251658240 ; 0x0F000000
ret i32 %ret
}
define i32 @t2_const_var3_2_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_2_ok_1:
+;CHECK-LABEL: t2_const_var3_2_ok_1:
;CHECK: add.w r0, r0, #3948544
%ret = add i32 %lhs, 3948544 ; 0b00000000001111000100000000000000
ret i32 %ret
}
define i32 @t2_const_var3_2_ok_2(i32 %lhs) {
-;CHECK: t2_const_var3_2_ok_2:
+;CHECK-LABEL: t2_const_var3_2_ok_2:
;CHECK: add.w r0, r0, #2097152
;CHECK: add.w r0, r0, #1843200
%ret = add i32 %lhs, 3940352 ; 0b00000000001111000010000000000000
}
define i32 @t2_const_var3_3_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_3_ok_1:
+;CHECK-LABEL: t2_const_var3_3_ok_1:
;CHECK: add.w r0, r0, #258
%ret = add i32 %lhs, 258 ; 0b00000000000000000000000100000010
ret i32 %ret
}
define i32 @t2_const_var3_4_ok_1(i32 %lhs) {
-;CHECK: t2_const_var3_4_ok_1:
+;CHECK-LABEL: t2_const_var3_4_ok_1:
;CHECK: add.w r0, r0, #-268435456
%ret = add i32 %lhs, 4026531840 ; 0xF0000000
ret i32 %ret
}
define i32 @t2MOVTi16_ok_1(i32 %a) {
-; CHECK: t2MOVTi16_ok_1:
+; CHECK-LABEL: t2MOVTi16_ok_1:
; CHECK: movt r0, #1234
%1 = and i32 %a, 65535
%2 = shl i32 1234, 16
}
define i32 @t2MOVTi16_test_1(i32 %a) {
-; CHECK: t2MOVTi16_test_1:
+; CHECK-LABEL: t2MOVTi16_test_1:
; CHECK: movt r0, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
}
define i32 @t2MOVTi16_test_2(i32 %a) {
-; CHECK: t2MOVTi16_test_2:
+; CHECK-LABEL: t2MOVTi16_test_2:
; CHECK: movt r0, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
}
define i32 @t2MOVTi16_test_3(i32 %a) {
-; CHECK: t2MOVTi16_test_3:
+; CHECK-LABEL: t2MOVTi16_test_3:
; CHECK: movt r0, #1234
%1 = shl i32 255, 8
%2 = shl i32 1234, 8
; 171 = 0x000000ab
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: movs r0, #171
%tmp = add i32 0, 171
ret i32 %tmp
; 1179666 = 0x00120012
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mov.w r0, #1179666
%tmp = add i32 0, 1179666
ret i32 %tmp
; 872428544 = 0x34003400
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov.w r0, #872428544
%tmp = add i32 0, 872428544
ret i32 %tmp
; 1448498774 = 0x56565656
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: mov.w r0, #1448498774
%tmp = add i32 0, 1448498774
ret i32 %tmp
; 66846720 = 0x03fc0000
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mov.w r0, #66846720
%tmp = add i32 0, 66846720
ret i32 %tmp
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b, i32 %c) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: muls r0, r1, r0
%tmp = mul i32 %a, %b
ret i32 %tmp
define %struct.CMPoint* @t1(i32 %i, i32 %j, i32 %n, %struct.CMPoint* %thePoints) nounwind readnone ssp {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: mla r0, r2, r0, r1
; CHECK: add.w r0, r0, r0, lsl #3
; CHECK: add.w r0, r3, r0, lsl #2
; 0x000000bb = 187
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mvn r0, #187
%tmp = xor i32 4294967295, 187
ret i32 %tmp
; 0x00aa00aa = 11141290
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mvn r0, #11141290
%tmp = xor i32 4294967295, 11141290
ret i32 %tmp
; 0xcc00cc00 = 3422604288
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mvn r0, #-872363008
%tmp = xor i32 4294967295, 3422604288
ret i32 %tmp
; 0x00110000 = 1114112
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvn r0, #1114112
%tmp = xor i32 4294967295, 1114112
ret i32 %tmp
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: mvns r0, r0
%tmp = xor i32 4294967295, %a
ret i32 %tmp
}
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: mvns r0, r0
%tmp = xor i32 %a, 4294967295
ret i32 %tmp
}
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: mvn.w r0, r0, lsl #5
%tmp = shl i32 %a, 5
%tmp1 = xor i32 %tmp, 4294967295
}
define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: mvn.w r0, r0, lsr #6
%tmp = lshr i32 %a, 6
%tmp1 = xor i32 %tmp, 4294967295
}
define i32 @f7(i32 %a) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: mvn.w r0, r0, asr #7
%tmp = ashr i32 %a, 7
%tmp1 = xor i32 %tmp, 4294967295
}
define i32 @f8(i32 %a) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: mvn.w r0, r0, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: rsbs r0, r0, #0
%tmp = sub i32 0, %a
ret i32 %tmp
%tmp1 = or i32 %a, %tmp
ret i32 %tmp1
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: orn r0, r0, r1
define i32 @f2(i32 %a, i32 %b) {
%tmp1 = or i32 %tmp, %a
ret i32 %tmp1
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: orn r0, r0, r1
define i32 @f3(i32 %a, i32 %b) {
%tmp1 = or i32 %a, %tmp
ret i32 %tmp1
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: orn r0, r0, r1
define i32 @f4(i32 %a, i32 %b) {
%tmp1 = or i32 %tmp, %a
ret i32 %tmp1
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: orn r0, r0, r1
define i32 @f5(i32 %a, i32 %b) {
%tmp2 = or i32 %a, %tmp1
ret i32 %tmp2
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: orn r0, r0, r1, lsl #5
define i32 @f6(i32 %a, i32 %b) {
%tmp2 = or i32 %a, %tmp1
ret i32 %tmp2
}
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: orn r0, r0, r1, lsr #6
define i32 @f7(i32 %a, i32 %b) {
%tmp2 = or i32 %a, %tmp1
ret i32 %tmp2
}
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: orn r0, r0, r1, asr #7
define i32 @f8(i32 %a, i32 %b) {
%tmp2 = or i32 %a, %tmp1
ret i32 %tmp2
}
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: orn r0, r0, r0, ror #8
%tmp2 = or i32 %a, %tmp1
ret i32 %tmp2
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: orn r0, r0, #187
; 0x00aa00aa = 11141290
%tmp2 = or i32 %a, %tmp1
ret i32 %tmp2
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: orn r0, r0, #11141290
; 0xcc00cc00 = 3422604288
%tmp2 = or i32 %a, %tmp1
ret i32 %tmp2
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: orn r0, r0, #-872363008
; 0x00110000 = 1114112
%tmp2 = or i32 %a, %tmp1
ret i32 %tmp2
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: orn r0, r0, #1114112
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: orrs r0, r1
%tmp2 = or i32 %a, %b
ret i32 %tmp2
}
define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: orr.w r0, r0, r1, lsl #5
%tmp = shl i32 %b, 5
%tmp2 = or i32 %a, %tmp
}
define i32 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: orr.w r0, r0, r1, lsr #6
%tmp = lshr i32 %b, 6
%tmp2 = or i32 %a, %tmp
}
define i32 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: orr.w r0, r0, r1, asr #7
%tmp = ashr i32 %b, 7
%tmp2 = or i32 %a, %tmp
}
define i32 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: orr.w r0, r0, r0, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
%tmp2 = or i32 %a, 187
ret i32 %tmp2
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: orr r0, r0, #187
; 0x00aa00aa = 11141290
%tmp2 = or i32 %a, 11141290
ret i32 %tmp2
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: orr r0, r0, #11141290
; 0xcc00cc00 = 3422604288
%tmp2 = or i32 %a, 3422604288
ret i32 %tmp2
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: orr r0, r0, #-872363008
; 0x44444444 = 1145324612
%tmp2 = or i32 %a, 1145324612
ret i32 %tmp2
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: orr r0, r0, #1145324612
; 0x00110000 = 1114112
%tmp2 = or i32 %a, 1114112
ret i32 %tmp2
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: orr r0, r0, #1114112
; RUN: llc < %s -march=thumb -mattr=+thumb2,+v7,+t2xtpk | FileCheck %s
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: rev r0, r0
%tmp = tail call i32 @llvm.bswap.i32(i32 %a)
ret i32 %tmp
declare i32 @llvm.bswap.i32(i32) nounwind readnone
define i32 @f2(i32 %X) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: revsh r0, r0
%tmp1 = lshr i32 %X, 8
%tmp1.upgrd.1 = trunc i32 %tmp1 to i16
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
; RUN: llc < %s -march=thumb | FileCheck %s -check-prefix=THUMB1
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ror.w r0, r0, #22
define i32 @f1(i32 %a) {
%l8 = shl i32 %a, 10
ret i32 %tmp
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NOT: and
; CHECK: ror
; THUMB1: f2
%tmp1 = sub i32 %tmp, %a
ret i32 %tmp1
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: rsb r0, r0, r1, lsl #5
define i32 @f2(i32 %a, i32 %b) {
%tmp1 = sub i32 %tmp, %a
ret i32 %tmp1
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: rsb r0, r0, r1, lsr #6
define i32 @f3(i32 %a, i32 %b) {
%tmp1 = sub i32 %tmp, %a
ret i32 %tmp1
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: rsb r0, r0, r1, asr #7
define i32 @f4(i32 %a, i32 %b) {
%tmp1 = sub i32 %tmp, %a
ret i32 %tmp1
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: rsb r0, r0, r0, ror #8
%tmp = sub i32 171, %a
ret i32 %tmp
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: rsb.w r0, r0, #171
; 1179666 = 0x00120012
%tmp = sub i32 1179666, %a
ret i32 %tmp
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: rsb.w r0, r0, #1179666
; 872428544 = 0x34003400
%tmp = sub i32 872428544, %a
ret i32 %tmp
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: rsb.w r0, r0, #872428544
; 1448498774 = 0x56565656
%tmp = sub i32 1448498774, %a
ret i32 %tmp
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: rsb.w r0, r0, #1448498774
; 66846720 = 0x03fc0000
%tmp = sub i32 66846720, %a
ret i32 %tmp
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: rsb.w r0, r0, #66846720
; Example from numerics code that manually computes wider-than-64 values.
;
-; CHECK: livecarry:
+; CHECK-LABEL: livecarry:
; CHECK: adds
; CHECK: adc
define i64 @livecarry(i64 %carry, i32 %digit) nounwind {
define i32 @f1(i32 %a.s) {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: it eq
; CHECK: moveq
define i32 @f2(i32 %a.s) {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: it gt
; CHECK: movgt
%tmp = icmp sgt i32 %a.s, 4
define i32 @f3(i32 %a.s, i32 %b.s) {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: it lt
; CHECK: movlt
%tmp = icmp slt i32 %a.s, %b.s
define i32 @f4(i32 %a.s, i32 %b.s) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: it le
; CHECK: movle
define i32 @f5(i32 %a.u, i32 %b.u) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: it ls
; CHECK: movls
%tmp = icmp ule i32 %a.u, %b.u
define i32 @f6(i32 %a.u, i32 %b.u) {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: it hi
; CHECK: movhi
%tmp = icmp ugt i32 %a.u, %b.u
define i32 @f7(i32 %a, i32 %b, i32 %c) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: it hi
; CHECK: lsrhi.w
%tmp1 = icmp ugt i32 %a, %b
define i32 @f8(i32 %a, i32 %b, i32 %c) {
entry:
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: it lo
; CHECK: lsllo.w
%tmp1 = icmp ult i32 %a, %b
define i32 @f9(i32 %a, i32 %b, i32 %c) {
entry:
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: it ge
; CHECK: rorge.w
%tmp1 = icmp sge i32 %a, %b
declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*, i32) nounwind readonly
define void @aaa(%quuz* %this, i8* %block) {
-; CHECK: aaa:
+; CHECK-LABEL: aaa:
; CHECK: bic r4, r4, #15
; CHECK: vst1.64 {{.*}}[{{.*}}:128]
; CHECK: vld1.64 {{.*}}[{{.*}}:128]
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: str r0, [r1]
store i32 %a, i32* %v
ret i32 %a
}
define i32 @f2(i32 %a, i32* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: str.w r0, [r1, #4092]
%tmp2 = getelementptr i32* %v, i32 1023
store i32 %a, i32* %tmp2
}
define i32 @f2a(i32 %a, i32* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
; CHECK: str r0, [r1, #-128]
%tmp2 = getelementptr i32* %v, i32 -32
store i32 %a, i32* %tmp2
}
define i32 @f3(i32 %a, i32* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov.w r2, #4096
; CHECK: str r0, [r1, r2]
%tmp2 = getelementptr i32* %v, i32 1024
define i32 @f4(i32 %a, i32 %base) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: str r0, [r1, #-128]
%tmp1 = sub i32 %base, 128
%tmp2 = inttoptr i32 %tmp1 to i32*
define i32 @f5(i32 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: str r0, [r1, r2]
%tmp1 = add i32 %base, %offset
%tmp2 = inttoptr i32 %tmp1 to i32*
define i32 @f6(i32 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: str.w r0, [r1, r2, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
define i32 @f7(i32 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lsrs r2, r2, #2
; CHECK: str r0, [r1, r2]
%tmp1 = lshr i32 %offset, 2
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i8 @f1(i8 %a, i8* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: strb r0, [r1]
store i8 %a, i8* %v
ret i8 %a
}
define i8 @f2(i8 %a, i8* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: strb.w r0, [r1, #4092]
%tmp2 = getelementptr i8* %v, i32 4092
store i8 %a, i8* %tmp2
}
define i8 @f2a(i8 %a, i8* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
; CHECK: strb r0, [r1, #-128]
%tmp2 = getelementptr i8* %v, i32 -128
store i8 %a, i8* %tmp2
}
define i8 @f3(i8 %a, i8* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov.w r2, #4096
; CHECK: strb r0, [r1, r2]
%tmp2 = getelementptr i8* %v, i32 4096
define i8 @f4(i8 %a, i32 %base) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: strb r0, [r1, #-128]
%tmp1 = sub i32 %base, 128
%tmp2 = inttoptr i32 %tmp1 to i8*
define i8 @f5(i8 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: strb r0, [r1, r2]
%tmp1 = add i32 %base, %offset
%tmp2 = inttoptr i32 %tmp1 to i8*
define i8 @f6(i8 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: strb.w r0, [r1, r2, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
define i8 @f7(i8 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lsrs r2, r2, #2
; CHECK: strb r0, [r1, r2]
%tmp1 = lshr i32 %offset, 2
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i16 @f1(i16 %a, i16* %v) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: strh r0, [r1]
store i16 %a, i16* %v
ret i16 %a
}
define i16 @f2(i16 %a, i16* %v) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: strh.w r0, [r1, #4092]
%tmp2 = getelementptr i16* %v, i32 2046
store i16 %a, i16* %tmp2
}
define i16 @f2a(i16 %a, i16* %v) {
-; CHECK: f2a:
+; CHECK-LABEL: f2a:
; CHECK: strh r0, [r1, #-128]
%tmp2 = getelementptr i16* %v, i32 -64
store i16 %a, i16* %tmp2
}
define i16 @f3(i16 %a, i16* %v) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: mov.w r2, #4096
; CHECK: strh r0, [r1, r2]
%tmp2 = getelementptr i16* %v, i32 2048
define i16 @f4(i16 %a, i32 %base) {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: strh r0, [r1, #-128]
%tmp1 = sub i32 %base, 128
%tmp2 = inttoptr i32 %tmp1 to i16*
define i16 @f5(i16 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: strh r0, [r1, r2]
%tmp1 = add i32 %base, %offset
%tmp2 = inttoptr i32 %tmp1 to i16*
define i16 @f6(i16 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: strh.w r0, [r1, r2, lsl #2]
%tmp1 = shl i32 %offset, 2
%tmp2 = add i32 %base, %tmp1
define i16 @f7(i16 %a, i32 %base, i32 %offset) {
entry:
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: lsrs r2, r2, #2
; CHECK: strh r0, [r1, r2]
%tmp1 = lshr i32 %offset, 2
; 171 = 0x000000ab
define i32 @f1(i32 %a) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: subs r0, #171
%tmp = sub i32 %a, 171
ret i32 %tmp
; 1179666 = 0x00120012
define i32 @f2(i32 %a) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sub.w r0, r0, #1179666
%tmp = sub i32 %a, 1179666
ret i32 %tmp
; 872428544 = 0x34003400
define i32 @f3(i32 %a) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sub.w r0, r0, #872428544
%tmp = sub i32 %a, 872428544
ret i32 %tmp
; 1448498774 = 0x56565656
define i32 @f4(i32 %a) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: sub.w r0, r0, #1448498774
%tmp = sub i32 %a, 1448498774
ret i32 %tmp
; 510 = 0x000001fe
define i32 @f5(i32 %a) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sub.w r0, r0, #510
%tmp = sub i32 %a, 510
ret i32 %tmp
; Don't change this to an add.
define i32 @f6(i32 %a) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: subs r0, #1
%tmp = sub i32 %a, 1
ret i32 %tmp
%tmp = sub i32 %a, 4095
ret i32 %tmp
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: subw r0, r0, #4095
; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
define i32 @f1(i32 %a, i32 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: subs r0, r0, r1
%tmp = sub i32 %a, %b
ret i32 %tmp
}
define i32 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: sub.w r0, r0, r1, lsl #5
%tmp = shl i32 %b, 5
%tmp1 = sub i32 %a, %tmp
}
define i32 @f3(i32 %a, i32 %b) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: sub.w r0, r0, r1, lsr #6
%tmp = lshr i32 %b, 6
%tmp1 = sub i32 %a, %tmp
}
define i32 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: sub.w r0, r0, r1, asr #7
%tmp = ashr i32 %b, 7
%tmp1 = sub i32 %a, %tmp
}
define i32 @f5(i32 %a, i32 %b) {
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: sub.w r0, r0, r0, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
; RUN: llc < %s -march=thumb -mattr=+thumb2 -mattr=+32bit | FileCheck %s
define i64 @f1(i64 %a, i64 %b) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: subs.w r0, r0, r2
; To test dead_carry, +32bit prevents sbc conveting to 16-bit sbcs
; CHECK: sbc.w r1, r1, r3
define void @bar(i32 %n.u) {
entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: tbb
; CHECK: .data_region jt8
; CHECK: .end_data_region
declare noalias i8* @calloc(i32, i32) nounwind
define i32 @main(i32 %argc, i8** nocapture %argv) nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: tbb
entry:
br label %bb42.i
%tmp1 = icmp eq i32 0, %tmp
ret i1 %tmp1
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: teq.w {{.*}}, #187
; 0x00aa00aa = 11141290
%tmp1 = icmp eq i32 %tmp, 0
ret i1 %tmp1
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: teq.w {{.*}}, #11141290
; 0xcc00cc00 = 3422604288
%tmp1 = icmp eq i32 0, %tmp
ret i1 %tmp1
}
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: teq.w {{.*}}, #-872363008
; 0xdddddddd = 3722304989
%tmp1 = icmp eq i32 %tmp, 0
ret i1 %tmp1
}
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: teq.w {{.*}}, #-572662307
; 0xdddddddd = 3722304989
%tmp1 = icmp eq i32 0, %tmp
ret i1 %tmp1
}
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: teq.w {{.*}}, #1114112
%tmp1 = icmp eq i32 0, %tmp
ret i1 %tmp1
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: tst.w {{.*}}, #187
; 0x00aa00aa = 11141290
%tmp1 = icmp eq i32 %tmp, 0
ret i1 %tmp1
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: tst.w {{.*}}, #11141290
; 0xcc00cc00 = 3422604288
%tmp1 = icmp eq i32 0, %tmp
ret i1 %tmp1
}
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: tst.w {{.*}}, #-872363008
; 0xdddddddd = 3722304989
%tmp1 = icmp eq i32 %tmp, 0
ret i1 %tmp1
}
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: tst.w {{.*}}, #-572662307
; 0x00110000 = 1114112
%tmp1 = icmp eq i32 0, %tmp
ret i1 %tmp1
}
-; CHECK: f10:
+; CHECK-LABEL: f10:
; CHECK: tst.w {{.*}}, #1114112
; tst as 'mov.w r0, #0'.
define i1 @f2(i32 %a, i32 %b) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: tst {{.*}}, r1
%tmp = and i32 %a, %b
%tmp1 = icmp eq i32 %tmp, 0
}
define i1 @f4(i32 %a, i32 %b) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: tst {{.*}}, r1
%tmp = and i32 %a, %b
%tmp1 = icmp eq i32 0, %tmp
}
define i1 @f6(i32 %a, i32 %b) {
-; CHECK: f6:
+; CHECK-LABEL: f6:
; CHECK: tst.w {{.*}}, r1, lsl #5
%tmp = shl i32 %b, 5
%tmp1 = and i32 %a, %tmp
}
define i1 @f7(i32 %a, i32 %b) {
-; CHECK: f7:
+; CHECK-LABEL: f7:
; CHECK: tst.w {{.*}}, r1, lsr #6
%tmp = lshr i32 %b, 6
%tmp1 = and i32 %a, %tmp
}
define i1 @f8(i32 %a, i32 %b) {
-; CHECK: f8:
+; CHECK-LABEL: f8:
; CHECK: tst.w {{.*}}, r1, asr #7
%tmp = ashr i32 %b, 7
%tmp1 = and i32 %a, %tmp
}
define i1 @f9(i32 %a, i32 %b) {
-; CHECK: f9:
+; CHECK-LABEL: f9:
; CHECK: tst.w {{.*}}, {{.*}}, ror #8
%l8 = shl i32 %a, 24
%r8 = lshr i32 %a, 8
define i32 @f() {
entry:
-; CHECK-NOT-PIC: f:
+; CHECK-NOT-PIC-LABEL: f:
; CHECK-NOT-PIC: add r0, pc
; CHECK-NOT-PIC: ldr r1, [r0]
; CHECK-NOT-PIC: i(gottpoff)
-; CHECK-PIC: f:
+; CHECK-PIC-LABEL: f:
; CHECK-PIC: bl __tls_get_addr(PLT)
%tmp1 = load i32* @i ; <i32> [#uses=1]
ret i32 %tmp1
define i32* @g() {
entry:
-; CHECK-NOT-PIC: g:
+; CHECK-NOT-PIC-LABEL: g:
; CHECK-NOT-PIC: add r0, pc
; CHECK-NOT-PIC: ldr r1, [r0]
; CHECK-NOT-PIC: i(gottpoff)
-; CHECK-PIC: g:
+; CHECK-PIC-LABEL: g:
; CHECK-PIC: bl __tls_get_addr(PLT)
ret i32* @i
}
@str = internal constant [9 x i8] c"%f+%f*i\0A\00" ; <[9 x i8]*> [#uses=1]
define i32 @main() {
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK-NOT: ret
; CHECK: subl $4, %{{.*}}
; CHECK: ret
%tmp2 = call x86_fp80 @llvm.sqrt.f80( x86_fp80 %x )
ret x86_fp80 %tmp2
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: fldt 4(%esp)
; CHECK-NEXT: fsqrt
; CHECK-NEXT: ret
entry:
%tmp2 = call x86_fp80 @llvm.powi.f80( x86_fp80 %x, i32 3 )
ret x86_fp80 %tmp2
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: fldt 4(%esp)
; CHECK-NEXT: fld %st(0)
; CHECK-NEXT: fmul %st(1)
ret void
}
-; CHECK: a:
+; CHECK-LABEL: a:
; CHECK: movups
; CHECK: movups
; CHECK-NOT: movups
define i32 @main() nounwind {
entry:
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: lock
; CHECK: decq
atomicrmw sub i64* @var, i64 1 monotonic
target triple = "i386-apple-darwin9.6"
define void @f() nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK-NOT: ret
; CHECK: foo $-81920
; CHECK-NOT: ret
define i64 @foo(i64 %b) nounwind readnone {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: shlq $56, %rdi
; CHECK: sarq $48, %rdi
; CHECK: leaq 1(%rdi), %rax
; RUN: llc < %s -mtriple=i386-apple-darwin10.0 -relocation-model=pic | FileCheck %s
define void @dot(i16* nocapture %A, i32 %As, i16* nocapture %B, i32 %Bs, i16* nocapture %C, i32 %N) nounwind ssp {
-; CHECK: dot:
+; CHECK-LABEL: dot:
; CHECK: decl %
; CHECK-NEXT: jne
entry:
define void @foo(i32 %n, float* nocapture %x) nounwind ssp {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
%0 = icmp sgt i32 %n, 0 ; <i1> [#uses=1]
br i1 %0, label %bb.nph, label %return
define void @t(i32 %count) ssp nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movups L_str+12(%rip), %xmm0
; CHECK: movups L_str(%rip), %xmm1
%tmp0 = alloca [60 x i8], align 1
define void @t() nounwind ssp {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movl %ecx, %eax
; CHECK: %eax = foo (%eax, %ecx)
%b = alloca i32 ; <i32*> [#uses=2]
define void @t2() nounwind ssp {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: movl
; CHECK: [[D2:%e.x]] = foo
; CHECK: ([[D2]],
@_dm_offset_addr_mask = external global [1 x i64], align 64 ; <[1 x i64]*> [#uses=0]
define void @leaf() nounwind {
-; CHECK: leaf:
+; CHECK-LABEL: leaf:
; CHECK-NOT: -8(%rsp)
; CHECK: leaq link_ptr@TLSGD
; CHECK: callq __tls_get_addr@PLT
define void @t(i64* nocapture %p) nounwind ssp {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movl ([[REG:%[a-z]+]]), %eax
; CHECK: movl 4([[REG]]), %edx
; CHECK: LBB0_1:
define i32* @t() nounwind optsize ssp {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: testl %eax, %eax
; CHECK: js
%cmp = icmp slt i32 undef, 0 ; <i1> [#uses=1]
define void @t(%struct.F* %this) nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: addq $12, %rsi
%BitValueArray = alloca [32 x i32], align 4
%tmp2 = getelementptr inbounds %struct.F* %this, i64 0, i32 0
ret i32 %3
}
-; CHECK: extend2bit_v2:
+; CHECK-LABEL: extend2bit_v2:
; CHECK: xorl %eax, %eax
; CHECK-NEXT: ret
%tmp10 = sext i8 %tmp9 to i32
ret i32 %tmp10
}
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: movsbl -2147483647
; PR11494
define void @test(<4 x i32>* nocapture %p) nounwind {
- ; CHECK: test:
+ ; CHECK-LABEL: test:
; CHECK: vpxor %xmm0, %xmm0, %xmm0
; CHECK-NEXT: vpmaxsd {{.*}}, %xmm0, %xmm0
; CHECK-NEXT: vmovdqu %xmm0, (%rdi)
; It's hard to test for the ISEL condition because CodeGen optimizes
; away the bugpointed code. Just ensure the basics are still there.
-;CHECK: func:
+;CHECK-LABEL: func:
;CHECK: vxorps
;CHECK: vinsertf128
;CHECK: vpshufd
; rdar://11472010
define i32 @t(i32 %mask) nounwind readnone ssp {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK-NOT: mov
%sub = add i32 %mask, -65535
%shr = lshr i32 %sub, 23
define void @foo(i8 %arg4, i32 %arg5, i32* %arg14) nounwind {
bb:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK-NOT: testl
; CHECK: testb
%tmp48 = zext i8 %arg4 to i32
; rdar://12081007
-; CHECK: and_1:
+; CHECK-LABEL: and_1:
; CHECK: andb
; CHECK-NEXT: cmovnel
; CHECK: ret
ret i32 %3
}
-; CHECK: and_2:
+; CHECK-LABEL: and_2:
; CHECK: andb
; CHECK-NEXT: setne
; CHECK: ret
ret i1 %2
}
-; CHECK: xor_1:
+; CHECK-LABEL: xor_1:
; CHECK: xorb
; CHECK-NEXT: cmovnel
; CHECK: ret
ret i32 %3
}
-; CHECK: xor_2:
+; CHECK-LABEL: xor_2:
; CHECK: xorb
; CHECK-NEXT: setne
; CHECK: ret
if.end: ; preds = %if.then, %entry
ret void
-; CHECK: fn1:
+; CHECK-LABEL: fn1:
; CHECK: shrq $32, [[REG:%.*]]
; CHECK: je
}
define zeroext i16 @t1(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
entry:
-; 32BIT: t1:
+; 32BIT-LABEL: t1:
; 32BIT: movw 20(%esp), %ax
; 32BIT-NOT: movw %ax, %cx
; 32BIT: leal 1(%eax), %ecx
-; 64BIT: t1:
+; 64BIT-LABEL: t1:
; 64BIT-NOT: movw %si, %ax
; 64BIT: leal 1(%rsi), %eax
%0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
define zeroext i16 @t2(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
entry:
-; 32BIT: t2:
+; 32BIT-LABEL: t2:
; 32BIT: movw 20(%esp), %ax
; 32BIT-NOT: movw %ax, %cx
; 32BIT: leal -1(%eax), %ecx
-; 64BIT: t2:
+; 64BIT-LABEL: t2:
; 64BIT-NOT: movw %si, %ax
; 64BIT: leal -1(%rsi), %eax
%0 = icmp eq i16 %k, %c ; <i1> [#uses=1]
define zeroext i16 @t3(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
entry:
-; 32BIT: t3:
+; 32BIT-LABEL: t3:
; 32BIT: movw 20(%esp), %ax
; 32BIT-NOT: movw %ax, %cx
; 32BIT: leal 2(%eax), %ecx
-; 64BIT: t3:
+; 64BIT-LABEL: t3:
; 64BIT-NOT: movw %si, %ax
; 64BIT: leal 2(%rsi), %eax
%0 = add i16 %k, 2 ; <i16> [#uses=3]
define zeroext i16 @t4(i16 zeroext %c, i16 zeroext %k) nounwind ssp {
entry:
-; 32BIT: t4:
+; 32BIT-LABEL: t4:
; 32BIT: movw 16(%esp), %ax
; 32BIT: movw 20(%esp), %cx
; 32BIT-NOT: movw %cx, %dx
; 32BIT: leal (%ecx,%eax), %edx
-; 64BIT: t4:
+; 64BIT-LABEL: t4:
; 64BIT-NOT: movw %si, %ax
; 64BIT: leal (%rsi,%rdi), %eax
%0 = add i16 %k, %c ; <i16> [#uses=3]
store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 0), align 4
ret void
-; LINUX-64-STATIC: foo00:
+; LINUX-64-STATIC-LABEL: foo00:
; LINUX-64-STATIC: movl src(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], dst
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo00:
+; LINUX-32-STATIC-LABEL: foo00:
; LINUX-32-STATIC: movl src, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], dst
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo00:
+; LINUX-32-PIC-LABEL: foo00:
; LINUX-32-PIC: movl src, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], dst
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo00:
+; LINUX-64-PIC-LABEL: foo00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r..]]
; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e..]]
; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r..]]
store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 0), align 4
ret void
-; LINUX-64-STATIC: fxo00:
+; LINUX-64-STATIC-LABEL: fxo00:
; LINUX-64-STATIC: movl xsrc(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], xdst
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: fxo00:
+; LINUX-32-STATIC-LABEL: fxo00:
; LINUX-32-STATIC: movl xsrc, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], xdst
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: fxo00:
+; LINUX-32-PIC-LABEL: fxo00:
; LINUX-32-PIC: movl xsrc, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], xdst
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: fxo00:
+; LINUX-64-PIC-LABEL: fxo00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]]
entry:
store i32* getelementptr ([131072 x i32]* @dst, i32 0, i32 0), i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: foo01:
+; LINUX-64-STATIC-LABEL: foo01:
; LINUX-64-STATIC: movq $dst, ptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo01:
+; LINUX-32-STATIC-LABEL: foo01:
; LINUX-32-STATIC: movl $dst, ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo01:
+; LINUX-32-PIC-LABEL: foo01:
; LINUX-32-PIC: movl $dst, ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo01:
+; LINUX-64-PIC-LABEL: foo01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]])
entry:
store i32* getelementptr ([32 x i32]* @xdst, i32 0, i32 0), i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: fxo01:
+; LINUX-64-STATIC-LABEL: fxo01:
; LINUX-64-STATIC: movq $xdst, ptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: fxo01:
+; LINUX-32-STATIC-LABEL: fxo01:
; LINUX-32-STATIC: movl $xdst, ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: fxo01:
+; LINUX-32-PIC-LABEL: fxo01:
; LINUX-32-PIC: movl $xdst, ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: fxo01:
+; LINUX-64-PIC-LABEL: fxo01:
; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]])
%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 0), align 4
store i32 %1, i32* %0, align 4
ret void
-; LINUX-64-STATIC: foo02:
+; LINUX-64-STATIC-LABEL: foo02:
; LINUX-64-STATIC: movl src(%rip), %
; LINUX-64-STATIC: movq ptr(%rip), %
; LINUX-64-STATIC: movl
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo02:
+; LINUX-32-STATIC-LABEL: foo02:
; LINUX-32-STATIC: movl src, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ([[ECX]])
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo02:
+; LINUX-32-PIC-LABEL: foo02:
; LINUX-32-PIC: movl src, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo02:
+; LINUX-64-PIC-LABEL: foo02:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = load i32** @ptr, align 8
%1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 0), align 4
store i32 %1, i32* %0, align 4
-; LINUX-64-STATIC: fxo02:
+; LINUX-64-STATIC-LABEL: fxo02:
; LINUX-64-STATIC: movl xsrc(%rip), %
; LINUX-64-STATIC: movq ptr(%rip), %
; LINUX-64-STATIC: movl
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: fxo02:
+; LINUX-32-STATIC-LABEL: fxo02:
; LINUX-32-STATIC: movl xsrc, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ([[ECX]])
; LINUX-32-STATIC-NEXT: ret
ret void
-; LINUX-32-PIC: fxo02:
+; LINUX-32-PIC-LABEL: fxo02:
; LINUX-32-PIC: movl xsrc, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: fxo02:
+; LINUX-64-PIC-LABEL: fxo02:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 0), align 32
ret void
-; LINUX-64-STATIC: foo03:
+; LINUX-64-STATIC-LABEL: foo03:
; LINUX-64-STATIC: movl dsrc(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ddst
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo03:
+; LINUX-32-STATIC-LABEL: foo03:
; LINUX-32-STATIC: movl dsrc, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ddst
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo03:
+; LINUX-32-PIC-LABEL: foo03:
; LINUX-32-PIC: movl dsrc, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ddst
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo03:
+; LINUX-64-PIC-LABEL: foo03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]]
entry:
store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i32 0), i32** @dptr, align 8
ret void
-; LINUX-64-STATIC: foo04:
+; LINUX-64-STATIC-LABEL: foo04:
; LINUX-64-STATIC: movq $ddst, dptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo04:
+; LINUX-32-STATIC-LABEL: foo04:
; LINUX-32-STATIC: movl $ddst, dptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo04:
+; LINUX-32-PIC-LABEL: foo04:
; LINUX-32-PIC: movl $ddst, dptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo04:
+; LINUX-64-PIC-LABEL: foo04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], ([[RCX]])
%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 0), align 32
store i32 %1, i32* %0, align 4
ret void
-; LINUX-64-STATIC: foo05:
+; LINUX-64-STATIC-LABEL: foo05:
; LINUX-64-STATIC: movl dsrc(%rip), %
; LINUX-64-STATIC: movq dptr(%rip), %
; LINUX-64-STATIC: movl
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo05:
+; LINUX-32-STATIC-LABEL: foo05:
; LINUX-32-STATIC: movl dsrc, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ([[ECX]])
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo05:
+; LINUX-32-PIC-LABEL: foo05:
; LINUX-32-PIC: movl dsrc, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo05:
+; LINUX-64-PIC-LABEL: foo05:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 0), align 4
ret void
-; LINUX-64-STATIC: foo06:
+; LINUX-64-STATIC-LABEL: foo06:
; LINUX-64-STATIC: movl lsrc(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ldst(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo06:
+; LINUX-32-STATIC-LABEL: foo06:
; LINUX-32-STATIC: movl lsrc, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ldst
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo06:
+; LINUX-32-PIC-LABEL: foo06:
; LINUX-32-PIC: movl lsrc, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ldst
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo06:
+; LINUX-64-PIC-LABEL: foo06:
; LINUX-64-PIC: movl lsrc(%rip), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movl [[EAX]], ldst(%rip)
; LINUX-64-PIC-NEXT: ret
entry:
store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i32 0), i32** @lptr, align 8
ret void
-; LINUX-64-STATIC: foo07:
+; LINUX-64-STATIC-LABEL: foo07:
; LINUX-64-STATIC: movq $ldst, lptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo07:
+; LINUX-32-STATIC-LABEL: foo07:
; LINUX-32-STATIC: movl $ldst, lptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo07:
+; LINUX-32-PIC-LABEL: foo07:
; LINUX-32-PIC: movl $ldst, lptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo07:
+; LINUX-64-PIC-LABEL: foo07:
; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip)
; LINUX-64-PIC-NEXT: ret
%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 0), align 4
store i32 %1, i32* %0, align 4
ret void
-; LINUX-64-STATIC: foo08:
+; LINUX-64-STATIC-LABEL: foo08:
; LINUX-64-STATIC: movl lsrc(%rip), %
; LINUX-64-STATIC: movq lptr(%rip), %
; LINUX-64-STATIC: movl
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: foo08:
+; LINUX-32-STATIC-LABEL: foo08:
; LINUX-32-STATIC: movl lsrc, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ([[ECX]])
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: foo08:
+; LINUX-32-PIC-LABEL: foo08:
; LINUX-32-PIC: movl lsrc, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: foo08:
+; LINUX-64-PIC-LABEL: foo08:
; LINUX-64-PIC: movl lsrc(%rip), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]]
; LINUX-64-PIC-NEXT: movl [[EAX]], ([[RCX]])
%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), align 4
ret void
-; LINUX-64-STATIC: qux00:
+; LINUX-64-STATIC-LABEL: qux00:
; LINUX-64-STATIC: movl src+64(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], dst+64(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux00:
+; LINUX-32-STATIC-LABEL: qux00:
; LINUX-32-STATIC: movl src+64, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], dst+64
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: qux00:
+; LINUX-32-PIC-LABEL: qux00:
; LINUX-32-PIC: movl src+64, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], dst+64
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux00:
+; LINUX-64-PIC-LABEL: qux00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
store i32 %0, i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), align 4
ret void
-; LINUX-64-STATIC: qxx00:
+; LINUX-64-STATIC-LABEL: qxx00:
; LINUX-64-STATIC: movl xsrc+64(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], xdst+64(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qxx00:
+; LINUX-32-STATIC-LABEL: qxx00:
; LINUX-32-STATIC: movl xsrc+64, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], xdst+64
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: qxx00:
+; LINUX-32-PIC-LABEL: qxx00:
; LINUX-32-PIC: movl xsrc+64, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], xdst+64
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qxx00:
+; LINUX-64-PIC-LABEL: qxx00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]]
entry:
store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16), i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: qux01:
+; LINUX-64-STATIC-LABEL: qux01:
; LINUX-64-STATIC: movq $dst+64, ptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux01:
+; LINUX-32-STATIC-LABEL: qux01:
; LINUX-32-STATIC: movl $dst+64, ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: qux01:
+; LINUX-32-PIC-LABEL: qux01:
; LINUX-32-PIC: movl $dst+64, ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux01:
+; LINUX-64-PIC-LABEL: qux01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: addq $64, [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
entry:
store i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16), i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: qxx01:
+; LINUX-64-STATIC-LABEL: qxx01:
; LINUX-64-STATIC: movq $xdst+64, ptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qxx01:
+; LINUX-32-STATIC-LABEL: qxx01:
; LINUX-32-STATIC: movl $xdst+64, ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: qxx01:
+; LINUX-32-PIC-LABEL: qxx01:
; LINUX-32-PIC: movl $xdst+64, ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qxx01:
+; LINUX-64-PIC-LABEL: qxx01:
; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: addq $64, [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%1 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16), align 4
%2 = getelementptr i32* %0, i64 16
store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux02:
+; LINUX-64-STATIC-LABEL: qux02:
; LINUX-64-STATIC: movl src+64(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]])
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux02:
+; LINUX-32-STATIC-LABEL: qux02:
; LINUX-32-STATIC: movl src+64, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]])
; LINUX-32-STATIC-NEXT: ret
ret void
-; LINUX-32-PIC: qux02:
+; LINUX-32-PIC-LABEL: qux02:
; LINUX-32-PIC: movl src+64, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], 64([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux02:
+; LINUX-64-PIC-LABEL: qux02:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%1 = load i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16), align 4
%2 = getelementptr i32* %0, i64 16
store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qxx02:
+; LINUX-64-STATIC-LABEL: qxx02:
; LINUX-64-STATIC: movl xsrc+64(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]])
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qxx02:
+; LINUX-32-STATIC-LABEL: qxx02:
; LINUX-32-STATIC: movl xsrc+64, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]])
; LINUX-32-STATIC-NEXT: ret
ret void
-; LINUX-32-PIC: qxx02:
+; LINUX-32-PIC-LABEL: qxx02:
; LINUX-32-PIC: movl xsrc+64, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], 64([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qxx02:
+; LINUX-64-PIC-LABEL: qxx02:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), align 32
ret void
-; LINUX-64-STATIC: qux03:
+; LINUX-64-STATIC-LABEL: qux03:
; LINUX-64-STATIC: movl dsrc+64(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ddst+64(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux03:
+; LINUX-32-STATIC-LABEL: qux03:
; LINUX-32-STATIC: movl dsrc+64, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ddst+64
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: qux03:
+; LINUX-32-PIC-LABEL: qux03:
; LINUX-32-PIC: movl dsrc+64, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ddst+64
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux03:
+; LINUX-64-PIC-LABEL: qux03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]]
entry:
store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16), i32** @dptr, align 8
ret void
-; LINUX-64-STATIC: qux04:
+; LINUX-64-STATIC-LABEL: qux04:
; LINUX-64-STATIC: movq $ddst+64, dptr(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux04:
+; LINUX-32-STATIC-LABEL: qux04:
; LINUX-32-STATIC: movl $ddst+64, dptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: qux04:
+; LINUX-32-PIC-LABEL: qux04:
; LINUX-32-PIC: movl $ddst+64, dptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux04:
+; LINUX-64-PIC-LABEL: qux04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: addq $64, [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%1 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16), align 32
%2 = getelementptr i32* %0, i64 16
store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux05:
+; LINUX-64-STATIC-LABEL: qux05:
; LINUX-64-STATIC: movl dsrc+64(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]])
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux05:
+; LINUX-32-STATIC-LABEL: qux05:
; LINUX-32-STATIC: movl dsrc+64, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]])
; LINUX-32-STATIC-NEXT: ret
ret void
-; LINUX-32-PIC: qux05:
+; LINUX-32-PIC-LABEL: qux05:
; LINUX-32-PIC: movl dsrc+64, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], 64([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux05:
+; LINUX-64-PIC-LABEL: qux05:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), align 4
ret void
-; LINUX-64-STATIC: qux06:
+; LINUX-64-STATIC-LABEL: qux06:
; LINUX-64-STATIC: movl lsrc+64(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ldst+64
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux06:
+; LINUX-32-STATIC-LABEL: qux06:
; LINUX-32-STATIC: movl lsrc+64, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ldst+64
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: qux06:
+; LINUX-32-PIC-LABEL: qux06:
; LINUX-32-PIC: movl lsrc+64, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ldst+64
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux06:
+; LINUX-64-PIC-LABEL: qux06:
; LINUX-64-PIC: movl lsrc+64(%rip), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movl [[EAX]], ldst+64(%rip)
; LINUX-64-PIC-NEXT: ret
entry:
store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16), i32** @lptr, align 8
ret void
-; LINUX-64-STATIC: qux07:
+; LINUX-64-STATIC-LABEL: qux07:
; LINUX-64-STATIC: movq $ldst+64, lptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux07:
+; LINUX-32-STATIC-LABEL: qux07:
; LINUX-32-STATIC: movl $ldst+64, lptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: qux07:
+; LINUX-32-PIC-LABEL: qux07:
; LINUX-32-PIC: movl $ldst+64, lptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux07:
+; LINUX-64-PIC-LABEL: qux07:
; LINUX-64-PIC: leaq ldst+64(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip)
; LINUX-64-PIC-NEXT: ret
%1 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16), align 4
%2 = getelementptr i32* %0, i64 16
store i32 %1, i32* %2, align 4
-; LINUX-64-STATIC: qux08:
+; LINUX-64-STATIC-LABEL: qux08:
; LINUX-64-STATIC: movl lsrc+64(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]])
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: qux08:
+; LINUX-32-STATIC-LABEL: qux08:
; LINUX-32-STATIC: movl lsrc+64, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], 64([[ECX]])
; LINUX-32-STATIC-NEXT: ret
ret void
-; LINUX-32-PIC: qux08:
+; LINUX-32-PIC-LABEL: qux08:
; LINUX-32-PIC: movl lsrc+64, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], 64([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: qux08:
+; LINUX-64-PIC-LABEL: qux08:
; LINUX-64-PIC: movl lsrc+64(%rip), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]]
; LINUX-64-PIC-NEXT: movl [[EAX]], 64([[RCX]])
%2 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
store i32 %1, i32* %2, align 4
ret void
-; LINUX-64-STATIC: ind00:
+; LINUX-64-STATIC-LABEL: ind00:
; LINUX-64-STATIC: movl src(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], dst(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind00:
+; LINUX-32-STATIC-LABEL: ind00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl src(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], dst(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind00:
+; LINUX-32-PIC-LABEL: ind00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl src(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], dst(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind00:
+; LINUX-64-PIC-LABEL: ind00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]]
%2 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
store i32 %1, i32* %2, align 4
ret void
-; LINUX-64-STATIC: ixd00:
+; LINUX-64-STATIC-LABEL: ixd00:
; LINUX-64-STATIC: movl xsrc(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], xdst(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ixd00:
+; LINUX-32-STATIC-LABEL: ixd00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl xsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], xdst(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ixd00:
+; LINUX-32-PIC-LABEL: ixd00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl xsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], xdst(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ixd00:
+; LINUX-64-PIC-LABEL: ixd00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %i
store i32* %0, i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: ind01:
+; LINUX-64-STATIC-LABEL: ind01:
; LINUX-64-STATIC: leaq dst(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], ptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind01:
+; LINUX-32-STATIC-LABEL: ind01:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal dst(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind01:
+; LINUX-32-PIC-LABEL: ind01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal dst(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind01:
+; LINUX-64-PIC-LABEL: ind01:
; LINUX-64-PIC: shlq $2, %rdi
; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), %rdi
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]]
%0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %i
store i32* %0, i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: ixd01:
+; LINUX-64-STATIC-LABEL: ixd01:
; LINUX-64-STATIC: leaq xdst(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], ptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ixd01:
+; LINUX-32-STATIC-LABEL: ixd01:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal xdst(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ixd01:
+; LINUX-32-PIC-LABEL: ixd01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal xdst(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ixd01:
+; LINUX-64-PIC-LABEL: ixd01:
; LINUX-64-PIC: shlq $2, %rdi
; LINUX-64-PIC-NEXT: addq xdst@GOTPCREL(%rip), %rdi
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]]
%3 = getelementptr i32* %0, i64 %i
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: ind02:
+; LINUX-64-STATIC-LABEL: ind02:
; LINUX-64-STATIC: movl src(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], ([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind02:
+; LINUX-32-STATIC-LABEL: ind02:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl src(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind02:
+; LINUX-32-PIC-LABEL: ind02:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl src(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind02:
+; LINUX-64-PIC-LABEL: ind02:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%3 = getelementptr i32* %0, i64 %i
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: ixd02:
+; LINUX-64-STATIC-LABEL: ixd02:
; LINUX-64-STATIC: movl xsrc(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], ([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ixd02:
+; LINUX-32-STATIC-LABEL: ixd02:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl xsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ixd02:
+; LINUX-32-PIC-LABEL: ixd02:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl xsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ixd02:
+; LINUX-64-PIC-LABEL: ixd02:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%2 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
store i32 %1, i32* %2, align 4
ret void
-; LINUX-64-STATIC: ind03:
+; LINUX-64-STATIC-LABEL: ind03:
; LINUX-64-STATIC: movl dsrc(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ddst(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind03:
+; LINUX-32-STATIC-LABEL: ind03:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ddst(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind03:
+; LINUX-32-PIC-LABEL: ind03:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ddst(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind03:
+; LINUX-64-PIC-LABEL: ind03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %i
store i32* %0, i32** @dptr, align 8
ret void
-; LINUX-64-STATIC: ind04:
+; LINUX-64-STATIC-LABEL: ind04:
; LINUX-64-STATIC: leaq ddst(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], dptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind04:
+; LINUX-32-STATIC-LABEL: ind04:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ddst(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], dptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind04:
+; LINUX-32-PIC-LABEL: ind04:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ddst(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], dptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind04:
+; LINUX-64-PIC-LABEL: ind04:
; LINUX-64-PIC: shlq $2, %rdi
; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), %rdi
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]]
%3 = getelementptr i32* %0, i64 %i
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: ind05:
+; LINUX-64-STATIC-LABEL: ind05:
; LINUX-64-STATIC: movl dsrc(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], ([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind05:
+; LINUX-32-STATIC-LABEL: ind05:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind05:
+; LINUX-32-PIC-LABEL: ind05:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl dptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind05:
+; LINUX-64-PIC-LABEL: ind05:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%2 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
store i32 %1, i32* %2, align 4
ret void
-; LINUX-64-STATIC: ind06:
+; LINUX-64-STATIC-LABEL: ind06:
; LINUX-64-STATIC: movl lsrc(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ldst(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind06:
+; LINUX-32-STATIC-LABEL: ind06:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ldst(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind06:
+; LINUX-32-PIC-LABEL: ind06:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ldst(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind06:
+; LINUX-64-PIC-LABEL: ind06:
; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: leaq ldst(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %i
store i32* %0, i32** @lptr, align 8
ret void
-; LINUX-64-STATIC: ind07:
+; LINUX-64-STATIC-LABEL: ind07:
; LINUX-64-STATIC: leaq ldst(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], lptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind07:
+; LINUX-32-STATIC-LABEL: ind07:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ldst(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], lptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind07:
+; LINUX-32-PIC-LABEL: ind07:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ldst(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], lptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind07:
+; LINUX-64-PIC-LABEL: ind07:
; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq ([[RAX]],%rdi,4), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip)
%3 = getelementptr i32* %0, i64 %i
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: ind08:
+; LINUX-64-STATIC-LABEL: ind08:
; LINUX-64-STATIC: movl lsrc(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], ([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ind08:
+; LINUX-32-STATIC-LABEL: ind08:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ind08:
+; LINUX-32-PIC-LABEL: ind08:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lsrc(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl lptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ind08:
+; LINUX-64-PIC-LABEL: ind08:
; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl ([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]]
%3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: off00:
+; LINUX-64-STATIC-LABEL: off00:
; LINUX-64-STATIC: movl src+64(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], dst+64(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off00:
+; LINUX-32-STATIC-LABEL: off00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl src+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], dst+64(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off00:
+; LINUX-32-PIC-LABEL: off00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl src+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], dst+64(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off00:
+; LINUX-64-PIC-LABEL: off00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]]
%3 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: oxf00:
+; LINUX-64-STATIC-LABEL: oxf00:
; LINUX-64-STATIC: movl xsrc+64(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], xdst+64(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: oxf00:
+; LINUX-32-STATIC-LABEL: oxf00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], xdst+64(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: oxf00:
+; LINUX-32-PIC-LABEL: oxf00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], xdst+64(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: oxf00:
+; LINUX-64-PIC-LABEL: oxf00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq xdst@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
store i32* %0, i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: off01:
+; LINUX-64-STATIC-LABEL: off01:
; LINUX-64-STATIC: leaq dst+64(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], ptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off01:
+; LINUX-32-STATIC-LABEL: off01:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal dst+64(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off01:
+; LINUX-32-PIC-LABEL: off01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal dst+64(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off01:
+; LINUX-64-PIC-LABEL: off01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = getelementptr [32 x i32]* @xdst, i64 0, i64 %.sum
store i32* %0, i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: oxf01:
+; LINUX-64-STATIC-LABEL: oxf01:
; LINUX-64-STATIC: leaq xdst+64(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], ptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: oxf01:
+; LINUX-32-STATIC-LABEL: oxf01:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal xdst+64(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: oxf01:
+; LINUX-32-PIC-LABEL: oxf01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal xdst+64(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: oxf01:
+; LINUX-64-PIC-LABEL: oxf01:
; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%4 = getelementptr i32* %0, i64 %1
store i32 %3, i32* %4, align 4
ret void
-; LINUX-64-STATIC: off02:
+; LINUX-64-STATIC-LABEL: off02:
; LINUX-64-STATIC: movl src+64(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off02:
+; LINUX-32-STATIC-LABEL: off02:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl src+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off02:
+; LINUX-32-PIC-LABEL: off02:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl src+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off02:
+; LINUX-64-PIC-LABEL: off02:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%4 = getelementptr i32* %0, i64 %1
store i32 %3, i32* %4, align 4
ret void
-; LINUX-64-STATIC: oxf02:
+; LINUX-64-STATIC-LABEL: oxf02:
; LINUX-64-STATIC: movl xsrc+64(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: oxf02:
+; LINUX-32-STATIC-LABEL: oxf02:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: oxf02:
+; LINUX-32-PIC-LABEL: oxf02:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl xsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: oxf02:
+; LINUX-64-PIC-LABEL: oxf02:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: off03:
+; LINUX-64-STATIC-LABEL: off03:
; LINUX-64-STATIC: movl dsrc+64(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ddst+64(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off03:
+; LINUX-32-STATIC-LABEL: off03:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ddst+64(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off03:
+; LINUX-32-PIC-LABEL: off03:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ddst+64(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off03:
+; LINUX-64-PIC-LABEL: off03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
store i32* %0, i32** @dptr, align 8
ret void
-; LINUX-64-STATIC: off04:
+; LINUX-64-STATIC-LABEL: off04:
; LINUX-64-STATIC: leaq ddst+64(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], dptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off04:
+; LINUX-32-STATIC-LABEL: off04:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ddst+64(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], dptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off04:
+; LINUX-32-PIC-LABEL: off04:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ddst+64(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], dptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off04:
+; LINUX-64-PIC-LABEL: off04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%4 = getelementptr i32* %0, i64 %1
store i32 %3, i32* %4, align 4
ret void
-; LINUX-64-STATIC: off05:
+; LINUX-64-STATIC-LABEL: off05:
; LINUX-64-STATIC: movl dsrc+64(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off05:
+; LINUX-32-STATIC-LABEL: off05:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off05:
+; LINUX-32-PIC-LABEL: off05:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl dptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off05:
+; LINUX-64-PIC-LABEL: off05:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: off06:
+; LINUX-64-STATIC-LABEL: off06:
; LINUX-64-STATIC: movl lsrc+64(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ldst+64(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off06:
+; LINUX-32-STATIC-LABEL: off06:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ldst+64(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off06:
+; LINUX-32-PIC-LABEL: off06:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ldst+64(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off06:
+; LINUX-64-PIC-LABEL: off06:
; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: leaq ldst(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
store i32* %0, i32** @lptr, align 8
ret void
-; LINUX-64-STATIC: off07:
+; LINUX-64-STATIC-LABEL: off07:
; LINUX-64-STATIC: leaq ldst+64(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], lptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off07:
+; LINUX-32-STATIC-LABEL: off07:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ldst+64(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], lptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off07:
+; LINUX-32-PIC-LABEL: off07:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ldst+64(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], lptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off07:
+; LINUX-64-PIC-LABEL: off07:
; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip)
%4 = getelementptr i32* %0, i64 %1
store i32 %3, i32* %4, align 4
ret void
-; LINUX-64-STATIC: off08:
+; LINUX-64-STATIC-LABEL: off08:
; LINUX-64-STATIC: movl lsrc+64(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 64([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: off08:
+; LINUX-32-STATIC-LABEL: off08:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: off08:
+; LINUX-32-PIC-LABEL: off08:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lsrc+64(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl lptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], 64([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: off08:
+; LINUX-64-PIC-LABEL: off08:
; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 64([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]]
%0 = load i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536), align 4
store i32 %0, i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), align 4
ret void
-; LINUX-64-STATIC: moo00:
+; LINUX-64-STATIC-LABEL: moo00:
; LINUX-64-STATIC: movl src+262144(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], dst+262144(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo00:
+; LINUX-32-STATIC-LABEL: moo00:
; LINUX-32-STATIC: movl src+262144, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], dst+262144
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo00:
+; LINUX-32-PIC-LABEL: moo00:
; LINUX-32-PIC: movl src+262144, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], dst+262144
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo00:
+; LINUX-64-PIC-LABEL: moo00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]]
entry:
store i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536), i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: moo01:
+; LINUX-64-STATIC-LABEL: moo01:
; LINUX-64-STATIC: movq $dst+262144, ptr(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo01:
+; LINUX-32-STATIC-LABEL: moo01:
; LINUX-32-STATIC: movl $dst+262144, ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo01:
+; LINUX-32-PIC-LABEL: moo01:
; LINUX-32-PIC: movl $dst+262144, ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo01:
+; LINUX-64-PIC-LABEL: moo01:
; LINUX-64-PIC: movl $262144, [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%2 = getelementptr i32* %0, i64 65536
store i32 %1, i32* %2, align 4
ret void
-; LINUX-64-STATIC: moo02:
+; LINUX-64-STATIC-LABEL: moo02:
; LINUX-64-STATIC: movl src+262144(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]])
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo02:
+; LINUX-32-STATIC-LABEL: moo02:
; LINUX-32-STATIC: movl src+262144, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]])
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo02:
+; LINUX-32-PIC-LABEL: moo02:
; LINUX-32-PIC: movl src+262144, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], 262144([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo02:
+; LINUX-64-PIC-LABEL: moo02:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = load i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536), align 32
store i32 %0, i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), align 32
ret void
-; LINUX-64-STATIC: moo03:
+; LINUX-64-STATIC-LABEL: moo03:
; LINUX-64-STATIC: movl dsrc+262144(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ddst+262144(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo03:
+; LINUX-32-STATIC-LABEL: moo03:
; LINUX-32-STATIC: movl dsrc+262144, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ddst+262144
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo03:
+; LINUX-32-PIC-LABEL: moo03:
; LINUX-32-PIC: movl dsrc+262144, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ddst+262144
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo03:
+; LINUX-64-PIC-LABEL: moo03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]]
entry:
store i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536), i32** @dptr, align 8
ret void
-; LINUX-64-STATIC: moo04:
+; LINUX-64-STATIC-LABEL: moo04:
; LINUX-64-STATIC: movq $ddst+262144, dptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo04:
+; LINUX-32-STATIC-LABEL: moo04:
; LINUX-32-STATIC: movl $ddst+262144, dptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo04:
+; LINUX-32-PIC-LABEL: moo04:
; LINUX-32-PIC: movl $ddst+262144, dptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo04:
+; LINUX-64-PIC-LABEL: moo04:
; LINUX-64-PIC: movl $262144, [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%2 = getelementptr i32* %0, i64 65536
store i32 %1, i32* %2, align 4
ret void
-; LINUX-64-STATIC: moo05:
+; LINUX-64-STATIC-LABEL: moo05:
; LINUX-64-STATIC: movl dsrc+262144(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]])
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo05:
+; LINUX-32-STATIC-LABEL: moo05:
; LINUX-32-STATIC: movl dsrc+262144, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]])
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo05:
+; LINUX-32-PIC-LABEL: moo05:
; LINUX-32-PIC: movl dsrc+262144, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], 262144([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo05:
+; LINUX-64-PIC-LABEL: moo05:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]]), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = load i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536), align 4
store i32 %0, i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), align 4
ret void
-; LINUX-64-STATIC: moo06:
+; LINUX-64-STATIC-LABEL: moo06:
; LINUX-64-STATIC: movl lsrc+262144(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ldst+262144(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo06:
+; LINUX-32-STATIC-LABEL: moo06:
; LINUX-32-STATIC: movl lsrc+262144, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ldst+262144
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo06:
+; LINUX-32-PIC-LABEL: moo06:
; LINUX-32-PIC: movl lsrc+262144, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ldst+262144
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo06:
+; LINUX-64-PIC-LABEL: moo06:
; LINUX-64-PIC: movl lsrc+262144(%rip), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movl [[EAX]], ldst+262144(%rip)
; LINUX-64-PIC-NEXT: ret
entry:
store i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536), i32** @lptr, align 8
ret void
-; LINUX-64-STATIC: moo07:
+; LINUX-64-STATIC-LABEL: moo07:
; LINUX-64-STATIC: movq $ldst+262144, lptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo07:
+; LINUX-32-STATIC-LABEL: moo07:
; LINUX-32-STATIC: movl $ldst+262144, lptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo07:
+; LINUX-32-PIC-LABEL: moo07:
; LINUX-32-PIC: movl $ldst+262144, lptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo07:
+; LINUX-64-PIC-LABEL: moo07:
; LINUX-64-PIC: leaq ldst+262144(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip)
; LINUX-64-PIC-NEXT: ret
%2 = getelementptr i32* %0, i64 65536
store i32 %1, i32* %2, align 4
ret void
-; LINUX-64-STATIC: moo08:
+; LINUX-64-STATIC-LABEL: moo08:
; LINUX-64-STATIC: movl lsrc+262144(%rip), [[EAX:%e.x]]
; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]])
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: moo08:
+; LINUX-32-STATIC-LABEL: moo08:
; LINUX-32-STATIC: movl lsrc+262144, [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], 262144([[ECX]])
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: moo08:
+; LINUX-32-PIC-LABEL: moo08:
; LINUX-32-PIC: movl lsrc+262144, [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], 262144([[ECX]])
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: moo08:
+; LINUX-64-PIC-LABEL: moo08:
; LINUX-64-PIC: movl lsrc+262144(%rip), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]]
; LINUX-64-PIC-NEXT: movl [[EAX]], 262144([[RCX]])
%3 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: big00:
+; LINUX-64-STATIC-LABEL: big00:
; LINUX-64-STATIC: movl src+262144(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], dst+262144(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big00:
+; LINUX-32-STATIC-LABEL: big00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl src+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], dst+262144(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big00:
+; LINUX-32-PIC-LABEL: big00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl src+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], dst+262144(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big00:
+; LINUX-64-PIC-LABEL: big00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dst@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @dst, i64 0, i64 %.sum
store i32* %0, i32** @ptr, align 8
ret void
-; LINUX-64-STATIC: big01:
+; LINUX-64-STATIC-LABEL: big01:
; LINUX-64-STATIC: leaq dst+262144(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], ptr(%rip)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big01:
+; LINUX-32-STATIC-LABEL: big01:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal dst+262144(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], ptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big01:
+; LINUX-32-PIC-LABEL: big01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal dst+262144(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], ptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big01:
+; LINUX-64-PIC-LABEL: big01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%4 = getelementptr i32* %0, i64 %1
store i32 %3, i32* %4, align 4
ret void
-; LINUX-64-STATIC: big02:
+; LINUX-64-STATIC-LABEL: big02:
; LINUX-64-STATIC: movl src+262144(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq ptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big02:
+; LINUX-32-STATIC-LABEL: big02:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl src+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big02:
+; LINUX-32-PIC-LABEL: big02:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl src+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big02:
+; LINUX-64-PIC-LABEL: big02:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
%3 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: big03:
+; LINUX-64-STATIC-LABEL: big03:
; LINUX-64-STATIC: movl dsrc+262144(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ddst+262144(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big03:
+; LINUX-32-STATIC-LABEL: big03:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ddst+262144(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big03:
+; LINUX-32-PIC-LABEL: big03:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ddst+262144(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big03:
+; LINUX-64-PIC-LABEL: big03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq ddst@GOTPCREL(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %.sum
store i32* %0, i32** @dptr, align 8
ret void
-; LINUX-64-STATIC: big04:
+; LINUX-64-STATIC-LABEL: big04:
; LINUX-64-STATIC: leaq ddst+262144(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], dptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big04:
+; LINUX-32-STATIC-LABEL: big04:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], dptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big04:
+; LINUX-32-PIC-LABEL: big04:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ddst+262144(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], dptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big04:
+; LINUX-64-PIC-LABEL: big04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%4 = getelementptr i32* %0, i64 %1
store i32 %3, i32* %4, align 4
ret void
-; LINUX-64-STATIC: big05:
+; LINUX-64-STATIC-LABEL: big05:
; LINUX-64-STATIC: movl dsrc+262144(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq dptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big05:
+; LINUX-32-STATIC-LABEL: big05:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big05:
+; LINUX-32-PIC-LABEL: big05:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl dptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big05:
+; LINUX-64-PIC-LABEL: big05:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
%3 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
store i32 %2, i32* %3, align 4
ret void
-; LINUX-64-STATIC: big06:
+; LINUX-64-STATIC-LABEL: big06:
; LINUX-64-STATIC: movl lsrc+262144(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movl [[EAX]], ldst+262144(,%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big06:
+; LINUX-32-STATIC-LABEL: big06:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], ldst+262144(,[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big06:
+; LINUX-32-PIC-LABEL: big06:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], ldst+262144(,[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big06:
+; LINUX-64-PIC-LABEL: big06:
; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: leaq ldst(%rip), [[RCX:%r.x]]
%0 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %.sum
store i32* %0, i32** @lptr, align 8
ret void
-; LINUX-64-STATIC: big07:
+; LINUX-64-STATIC-LABEL: big07:
; LINUX-64-STATIC: leaq ldst+262144(,%rdi,4), [[RAX:%r.x]]
; LINUX-64-STATIC: movq [[RAX]], lptr
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big07:
+; LINUX-32-STATIC-LABEL: big07:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[EAX]], lptr
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big07:
+; LINUX-32-PIC-LABEL: big07:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ldst+262144(,[[EAX]],4), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[EAX]], lptr
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big07:
+; LINUX-64-PIC-LABEL: big07:
; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq [[RAX]], lptr(%rip)
%4 = getelementptr i32* %0, i64 %1
store i32 %3, i32* %4, align 4
ret void
-; LINUX-64-STATIC: big08:
+; LINUX-64-STATIC-LABEL: big08:
; LINUX-64-STATIC: movl lsrc+262144(,%rdi,4), [[EAX:%e.x]]
; LINUX-64-STATIC: movq lptr(%rip), [[RCX:%r.x]]
; LINUX-64-STATIC: movl [[EAX]], 262144([[RCX]],%rdi,4)
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: big08:
+; LINUX-32-STATIC-LABEL: big08:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lptr, [[EDX:%e.x]]
; LINUX-32-STATIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4)
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: big08:
+; LINUX-32-PIC-LABEL: big08:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lsrc+262144(,[[EAX]],4), [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: movl lptr, [[EDX:%e.x]]
; LINUX-32-PIC-NEXT: movl [[ECX]], 262144([[EDX]],[[EAX]],4)
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: big08:
+; LINUX-64-PIC-LABEL: big08:
; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movl 262144([[RAX]],%rdi,4), [[EAX:%e.x]]
; LINUX-64-PIC-NEXT: movq lptr(%rip), [[RCX:%r.x]]
define i8* @bar00() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @src to i8*)
-; LINUX-64-STATIC: bar00:
+; LINUX-64-STATIC-LABEL: bar00:
; LINUX-64-STATIC: movl $src, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar00:
+; LINUX-32-STATIC-LABEL: bar00:
; LINUX-32-STATIC: movl $src, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar00:
+; LINUX-32-PIC-LABEL: bar00:
; LINUX-32-PIC: movl $src, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar00:
+; LINUX-64-PIC-LABEL: bar00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bxr00() nounwind {
entry:
ret i8* bitcast ([32 x i32]* @xsrc to i8*)
-; LINUX-64-STATIC: bxr00:
+; LINUX-64-STATIC-LABEL: bxr00:
; LINUX-64-STATIC: movl $xsrc, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bxr00:
+; LINUX-32-STATIC-LABEL: bxr00:
; LINUX-32-STATIC: movl $xsrc, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bxr00:
+; LINUX-32-PIC-LABEL: bxr00:
; LINUX-32-PIC: movl $xsrc, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bxr00:
+; LINUX-64-PIC-LABEL: bxr00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bar01() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @dst to i8*)
-; LINUX-64-STATIC: bar01:
+; LINUX-64-STATIC-LABEL: bar01:
; LINUX-64-STATIC: movl $dst, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar01:
+; LINUX-32-STATIC-LABEL: bar01:
; LINUX-32-STATIC: movl $dst, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar01:
+; LINUX-32-PIC-LABEL: bar01:
; LINUX-32-PIC: movl $dst, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar01:
+; LINUX-64-PIC-LABEL: bar01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bxr01() nounwind {
entry:
ret i8* bitcast ([32 x i32]* @xdst to i8*)
-; LINUX-64-STATIC: bxr01:
+; LINUX-64-STATIC-LABEL: bxr01:
; LINUX-64-STATIC: movl $xdst, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bxr01:
+; LINUX-32-STATIC-LABEL: bxr01:
; LINUX-32-STATIC: movl $xdst, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bxr01:
+; LINUX-32-PIC-LABEL: bxr01:
; LINUX-32-PIC: movl $xdst, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bxr01:
+; LINUX-64-PIC-LABEL: bxr01:
; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bar02() nounwind {
entry:
ret i8* bitcast (i32** @ptr to i8*)
-; LINUX-64-STATIC: bar02:
+; LINUX-64-STATIC-LABEL: bar02:
; LINUX-64-STATIC: movl $ptr, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar02:
+; LINUX-32-STATIC-LABEL: bar02:
; LINUX-32-STATIC: movl $ptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar02:
+; LINUX-32-PIC-LABEL: bar02:
; LINUX-32-PIC: movl $ptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar02:
+; LINUX-64-PIC-LABEL: bar02:
; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bar03() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
-; LINUX-64-STATIC: bar03:
+; LINUX-64-STATIC-LABEL: bar03:
; LINUX-64-STATIC: movl $dsrc, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar03:
+; LINUX-32-STATIC-LABEL: bar03:
; LINUX-32-STATIC: movl $dsrc, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar03:
+; LINUX-32-PIC-LABEL: bar03:
; LINUX-32-PIC: movl $dsrc, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar03:
+; LINUX-64-PIC-LABEL: bar03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bar04() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @ddst to i8*)
-; LINUX-64-STATIC: bar04:
+; LINUX-64-STATIC-LABEL: bar04:
; LINUX-64-STATIC: movl $ddst, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar04:
+; LINUX-32-STATIC-LABEL: bar04:
; LINUX-32-STATIC: movl $ddst, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar04:
+; LINUX-32-PIC-LABEL: bar04:
; LINUX-32-PIC: movl $ddst, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar04:
+; LINUX-64-PIC-LABEL: bar04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bar05() nounwind {
entry:
ret i8* bitcast (i32** @dptr to i8*)
-; LINUX-64-STATIC: bar05:
+; LINUX-64-STATIC-LABEL: bar05:
; LINUX-64-STATIC: movl $dptr, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar05:
+; LINUX-32-STATIC-LABEL: bar05:
; LINUX-32-STATIC: movl $dptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar05:
+; LINUX-32-PIC-LABEL: bar05:
; LINUX-32-PIC: movl $dptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar05:
+; LINUX-64-PIC-LABEL: bar05:
; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bar06() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
-; LINUX-64-STATIC: bar06:
+; LINUX-64-STATIC-LABEL: bar06:
; LINUX-64-STATIC: movl $lsrc, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar06:
+; LINUX-32-STATIC-LABEL: bar06:
; LINUX-32-STATIC: movl $lsrc, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar06:
+; LINUX-32-PIC-LABEL: bar06:
; LINUX-32-PIC: movl $lsrc, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar06:
+; LINUX-64-PIC-LABEL: bar06:
; LINUX-64-PIC: leaq lsrc(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bar07() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @ldst to i8*)
-; LINUX-64-STATIC: bar07:
+; LINUX-64-STATIC-LABEL: bar07:
; LINUX-64-STATIC: movl $ldst, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar07:
+; LINUX-32-STATIC-LABEL: bar07:
; LINUX-32-STATIC: movl $ldst, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar07:
+; LINUX-32-PIC-LABEL: bar07:
; LINUX-32-PIC: movl $ldst, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar07:
+; LINUX-64-PIC-LABEL: bar07:
; LINUX-64-PIC: leaq ldst(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bar08() nounwind {
entry:
ret i8* bitcast (i32** @lptr to i8*)
-; LINUX-64-STATIC: bar08:
+; LINUX-64-STATIC-LABEL: bar08:
; LINUX-64-STATIC: movl $lptr, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bar08:
+; LINUX-32-STATIC-LABEL: bar08:
; LINUX-32-STATIC: movl $lptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bar08:
+; LINUX-32-PIC-LABEL: bar08:
; LINUX-32-PIC: movl $lptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bar08:
+; LINUX-64-PIC-LABEL: bar08:
; LINUX-64-PIC: leaq lptr(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @har00() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @src to i8*)
-; LINUX-64-STATIC: har00:
+; LINUX-64-STATIC-LABEL: har00:
; LINUX-64-STATIC: movl $src, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har00:
+; LINUX-32-STATIC-LABEL: har00:
; LINUX-32-STATIC: movl $src, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har00:
+; LINUX-32-PIC-LABEL: har00:
; LINUX-32-PIC: movl $src, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har00:
+; LINUX-64-PIC-LABEL: har00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @hxr00() nounwind {
entry:
ret i8* bitcast ([32 x i32]* @xsrc to i8*)
-; LINUX-64-STATIC: hxr00:
+; LINUX-64-STATIC-LABEL: hxr00:
; LINUX-64-STATIC: movl $xsrc, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: hxr00:
+; LINUX-32-STATIC-LABEL: hxr00:
; LINUX-32-STATIC: movl $xsrc, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: hxr00:
+; LINUX-32-PIC-LABEL: hxr00:
; LINUX-32-PIC: movl $xsrc, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: hxr00:
+; LINUX-64-PIC-LABEL: hxr00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @har01() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @dst to i8*)
-; LINUX-64-STATIC: har01:
+; LINUX-64-STATIC-LABEL: har01:
; LINUX-64-STATIC: movl $dst, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har01:
+; LINUX-32-STATIC-LABEL: har01:
; LINUX-32-STATIC: movl $dst, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har01:
+; LINUX-32-PIC-LABEL: har01:
; LINUX-32-PIC: movl $dst, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har01:
+; LINUX-64-PIC-LABEL: har01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @hxr01() nounwind {
entry:
ret i8* bitcast ([32 x i32]* @xdst to i8*)
-; LINUX-64-STATIC: hxr01:
+; LINUX-64-STATIC-LABEL: hxr01:
; LINUX-64-STATIC: movl $xdst, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: hxr01:
+; LINUX-32-STATIC-LABEL: hxr01:
; LINUX-32-STATIC: movl $xdst, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: hxr01:
+; LINUX-32-PIC-LABEL: hxr01:
; LINUX-32-PIC: movl $xdst, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: hxr01:
+; LINUX-64-PIC-LABEL: hxr01:
; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
%0 = load i32** @ptr, align 8
%1 = bitcast i32* %0 to i8*
ret i8* %1
-; LINUX-64-STATIC: har02:
+; LINUX-64-STATIC-LABEL: har02:
; LINUX-64-STATIC: movq ptr(%rip), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har02:
+; LINUX-32-STATIC-LABEL: har02:
; LINUX-32-STATIC: movl ptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har02:
+; LINUX-32-PIC-LABEL: har02:
; LINUX-32-PIC: movl ptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har02:
+; LINUX-64-PIC-LABEL: har02:
; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ([[RAX]]), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @har03() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @dsrc to i8*)
-; LINUX-64-STATIC: har03:
+; LINUX-64-STATIC-LABEL: har03:
; LINUX-64-STATIC: movl $dsrc, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har03:
+; LINUX-32-STATIC-LABEL: har03:
; LINUX-32-STATIC: movl $dsrc, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har03:
+; LINUX-32-PIC-LABEL: har03:
; LINUX-32-PIC: movl $dsrc, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har03:
+; LINUX-64-PIC-LABEL: har03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @har04() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @ddst to i8*)
-; LINUX-64-STATIC: har04:
+; LINUX-64-STATIC-LABEL: har04:
; LINUX-64-STATIC: movl $ddst, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har04:
+; LINUX-32-STATIC-LABEL: har04:
; LINUX-32-STATIC: movl $ddst, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har04:
+; LINUX-32-PIC-LABEL: har04:
; LINUX-32-PIC: movl $ddst, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har04:
+; LINUX-64-PIC-LABEL: har04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
%0 = load i32** @dptr, align 8
%1 = bitcast i32* %0 to i8*
ret i8* %1
-; LINUX-64-STATIC: har05:
+; LINUX-64-STATIC-LABEL: har05:
; LINUX-64-STATIC: movq dptr(%rip), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har05:
+; LINUX-32-STATIC-LABEL: har05:
; LINUX-32-STATIC: movl dptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har05:
+; LINUX-32-PIC-LABEL: har05:
; LINUX-32-PIC: movl dptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har05:
+; LINUX-64-PIC-LABEL: har05:
; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ([[RAX]]), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @har06() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @lsrc to i8*)
-; LINUX-64-STATIC: har06:
+; LINUX-64-STATIC-LABEL: har06:
; LINUX-64-STATIC: movl $lsrc, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har06:
+; LINUX-32-STATIC-LABEL: har06:
; LINUX-32-STATIC: movl $lsrc, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har06:
+; LINUX-32-PIC-LABEL: har06:
; LINUX-32-PIC: movl $lsrc, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har06:
+; LINUX-64-PIC-LABEL: har06:
; LINUX-64-PIC: leaq lsrc(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @har07() nounwind {
entry:
ret i8* bitcast ([131072 x i32]* @ldst to i8*)
-; LINUX-64-STATIC: har07:
+; LINUX-64-STATIC-LABEL: har07:
; LINUX-64-STATIC: movl $ldst, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har07:
+; LINUX-32-STATIC-LABEL: har07:
; LINUX-32-STATIC: movl $ldst, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har07:
+; LINUX-32-PIC-LABEL: har07:
; LINUX-32-PIC: movl $ldst, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har07:
+; LINUX-64-PIC-LABEL: har07:
; LINUX-64-PIC: leaq ldst(%rip), %rax
; LINUX-64-PIC-NEXT: ret
%0 = load i32** @lptr, align 8
%1 = bitcast i32* %0 to i8*
ret i8* %1
-; LINUX-64-STATIC: har08:
+; LINUX-64-STATIC-LABEL: har08:
; LINUX-64-STATIC: movq lptr(%rip), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: har08:
+; LINUX-32-STATIC-LABEL: har08:
; LINUX-32-STATIC: movl lptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: har08:
+; LINUX-32-PIC-LABEL: har08:
; LINUX-32-PIC: movl lptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: har08:
+; LINUX-64-PIC-LABEL: har08:
; LINUX-64-PIC: movq lptr(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bat00() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat00:
+; LINUX-64-STATIC-LABEL: bat00:
; LINUX-64-STATIC: movl $src+64, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat00:
+; LINUX-32-STATIC-LABEL: bat00:
; LINUX-32-STATIC: movl $src+64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat00:
+; LINUX-32-PIC-LABEL: bat00:
; LINUX-32-PIC: movl $src+64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat00:
+; LINUX-64-PIC-LABEL: bat00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bxt00() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([32 x i32]* @xsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bxt00:
+; LINUX-64-STATIC-LABEL: bxt00:
; LINUX-64-STATIC: movl $xsrc+64, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bxt00:
+; LINUX-32-STATIC-LABEL: bxt00:
; LINUX-32-STATIC: movl $xsrc+64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bxt00:
+; LINUX-32-PIC-LABEL: bxt00:
; LINUX-32-PIC: movl $xsrc+64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bxt00:
+; LINUX-64-PIC-LABEL: bxt00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bat01() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat01:
+; LINUX-64-STATIC-LABEL: bat01:
; LINUX-64-STATIC: movl $dst+64, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat01:
+; LINUX-32-STATIC-LABEL: bat01:
; LINUX-32-STATIC: movl $dst+64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat01:
+; LINUX-32-PIC-LABEL: bat01:
; LINUX-32-PIC: movl $dst+64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat01:
+; LINUX-64-PIC-LABEL: bat01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bxt01() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bxt01:
+; LINUX-64-STATIC-LABEL: bxt01:
; LINUX-64-STATIC: movl $xdst+64, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bxt01:
+; LINUX-32-STATIC-LABEL: bxt01:
; LINUX-32-STATIC: movl $xdst+64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bxt01:
+; LINUX-32-PIC-LABEL: bxt01:
; LINUX-32-PIC: movl $xdst+64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bxt01:
+; LINUX-64-PIC-LABEL: bxt01:
; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr i32* %0, i64 16
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: bat02:
+; LINUX-64-STATIC-LABEL: bat02:
; LINUX-64-STATIC: movq ptr(%rip), %rax
; LINUX-64-STATIC: addq $64, %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat02:
+; LINUX-32-STATIC-LABEL: bat02:
; LINUX-32-STATIC: movl ptr, %eax
; LINUX-32-STATIC-NEXT: addl $64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat02:
+; LINUX-32-PIC-LABEL: bat02:
; LINUX-32-PIC: movl ptr, %eax
; LINUX-32-PIC-NEXT: addl $64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat02:
+; LINUX-64-PIC-LABEL: bat02:
; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ([[RAX]]), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
define i8* @bat03() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat03:
+; LINUX-64-STATIC-LABEL: bat03:
; LINUX-64-STATIC: movl $dsrc+64, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat03:
+; LINUX-32-STATIC-LABEL: bat03:
; LINUX-32-STATIC: movl $dsrc+64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat03:
+; LINUX-32-PIC-LABEL: bat03:
; LINUX-32-PIC: movl $dsrc+64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat03:
+; LINUX-64-PIC-LABEL: bat03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bat04() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat04:
+; LINUX-64-STATIC-LABEL: bat04:
; LINUX-64-STATIC: movl $ddst+64, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat04:
+; LINUX-32-STATIC-LABEL: bat04:
; LINUX-32-STATIC: movl $ddst+64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat04:
+; LINUX-32-PIC-LABEL: bat04:
; LINUX-32-PIC: movl $ddst+64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat04:
+; LINUX-64-PIC-LABEL: bat04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr i32* %0, i64 16
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: bat05:
+; LINUX-64-STATIC-LABEL: bat05:
; LINUX-64-STATIC: movq dptr(%rip), %rax
; LINUX-64-STATIC: addq $64, %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat05:
+; LINUX-32-STATIC-LABEL: bat05:
; LINUX-32-STATIC: movl dptr, %eax
; LINUX-32-STATIC-NEXT: addl $64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat05:
+; LINUX-32-PIC-LABEL: bat05:
; LINUX-32-PIC: movl dptr, %eax
; LINUX-32-PIC-NEXT: addl $64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat05:
+; LINUX-64-PIC-LABEL: bat05:
; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ([[RAX]]), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
define i8* @bat06() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat06:
+; LINUX-64-STATIC-LABEL: bat06:
; LINUX-64-STATIC: movl $lsrc+64, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat06:
+; LINUX-32-STATIC-LABEL: bat06:
; LINUX-32-STATIC: movl $lsrc+64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat06:
+; LINUX-32-PIC-LABEL: bat06:
; LINUX-32-PIC: movl $lsrc+64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat06:
+; LINUX-64-PIC-LABEL: bat06:
; LINUX-64-PIC: leaq lsrc+64(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bat07() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 16) to i8*)
-; LINUX-64-STATIC: bat07:
+; LINUX-64-STATIC-LABEL: bat07:
; LINUX-64-STATIC: movl $ldst+64, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat07:
+; LINUX-32-STATIC-LABEL: bat07:
; LINUX-32-STATIC: movl $ldst+64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat07:
+; LINUX-32-PIC-LABEL: bat07:
; LINUX-32-PIC: movl $ldst+64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat07:
+; LINUX-64-PIC-LABEL: bat07:
; LINUX-64-PIC: leaq ldst+64(%rip), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr i32* %0, i64 16
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: bat08:
+; LINUX-64-STATIC-LABEL: bat08:
; LINUX-64-STATIC: movq lptr(%rip), %rax
; LINUX-64-STATIC: addq $64, %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bat08:
+; LINUX-32-STATIC-LABEL: bat08:
; LINUX-32-STATIC: movl lptr, %eax
; LINUX-32-STATIC-NEXT: addl $64, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bat08:
+; LINUX-32-PIC-LABEL: bat08:
; LINUX-32-PIC: movl lptr, %eax
; LINUX-32-PIC-NEXT: addl $64, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bat08:
+; LINUX-64-PIC-LABEL: bat08:
; LINUX-64-PIC: movq lptr(%rip), %rax
; LINUX-64-PIC-NEXT: addq $64, %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bam00() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @src, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam00:
+; LINUX-64-STATIC-LABEL: bam00:
; LINUX-64-STATIC: movl $src+262144, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam00:
+; LINUX-32-STATIC-LABEL: bam00:
; LINUX-32-STATIC: movl $src+262144, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam00:
+; LINUX-32-PIC-LABEL: bam00:
; LINUX-32-PIC: movl $src+262144, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam00:
+; LINUX-64-PIC-LABEL: bam00:
; LINUX-64-PIC: movl $262144, %eax
; LINUX-64-PIC-NEXT: addq src@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bam01() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam01:
+; LINUX-64-STATIC-LABEL: bam01:
; LINUX-64-STATIC: movl $dst+262144, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam01:
+; LINUX-32-STATIC-LABEL: bam01:
; LINUX-32-STATIC: movl $dst+262144, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam01:
+; LINUX-32-PIC-LABEL: bam01:
; LINUX-32-PIC: movl $dst+262144, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam01:
+; LINUX-64-PIC-LABEL: bam01:
; LINUX-64-PIC: movl $262144, %eax
; LINUX-64-PIC-NEXT: addq dst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bxm01() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([32 x i32]* @xdst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bxm01:
+; LINUX-64-STATIC-LABEL: bxm01:
; LINUX-64-STATIC: movl $xdst+262144, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bxm01:
+; LINUX-32-STATIC-LABEL: bxm01:
; LINUX-32-STATIC: movl $xdst+262144, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bxm01:
+; LINUX-32-PIC-LABEL: bxm01:
; LINUX-32-PIC: movl $xdst+262144, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bxm01:
+; LINUX-64-PIC-LABEL: bxm01:
; LINUX-64-PIC: movl $262144, %eax
; LINUX-64-PIC-NEXT: addq xdst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr i32* %0, i64 65536
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: bam02:
+; LINUX-64-STATIC-LABEL: bam02:
; LINUX-64-STATIC: movl $262144, %eax
; LINUX-64-STATIC: addq ptr(%rip), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam02:
+; LINUX-32-STATIC-LABEL: bam02:
; LINUX-32-STATIC: movl $262144, %eax
; LINUX-32-STATIC-NEXT: addl ptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam02:
+; LINUX-32-PIC-LABEL: bam02:
; LINUX-32-PIC: movl $262144, %eax
; LINUX-32-PIC-NEXT: addl ptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam02:
+; LINUX-64-PIC-LABEL: bam02:
; LINUX-64-PIC: movl $262144, %eax
; LINUX-64-PIC-NEXT: movq ptr@GOTPCREL(%rip), [[RCX:%r.x]]
; LINUX-64-PIC-NEXT: addq ([[RCX]]), %rax
define i8* @bam03() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @dsrc, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam03:
+; LINUX-64-STATIC-LABEL: bam03:
; LINUX-64-STATIC: movl $dsrc+262144, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam03:
+; LINUX-32-STATIC-LABEL: bam03:
; LINUX-32-STATIC: movl $dsrc+262144, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam03:
+; LINUX-32-PIC-LABEL: bam03:
; LINUX-32-PIC: movl $dsrc+262144, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam03:
+; LINUX-64-PIC-LABEL: bam03:
; LINUX-64-PIC: movl $262144, %eax
; LINUX-64-PIC-NEXT: addq dsrc@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bam04() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ddst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam04:
+; LINUX-64-STATIC-LABEL: bam04:
; LINUX-64-STATIC: movl $ddst+262144, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam04:
+; LINUX-32-STATIC-LABEL: bam04:
; LINUX-32-STATIC: movl $ddst+262144, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam04:
+; LINUX-32-PIC-LABEL: bam04:
; LINUX-32-PIC: movl $ddst+262144, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam04:
+; LINUX-64-PIC-LABEL: bam04:
; LINUX-64-PIC: movl $262144, %eax
; LINUX-64-PIC-NEXT: addq ddst@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr i32* %0, i64 65536
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: bam05:
+; LINUX-64-STATIC-LABEL: bam05:
; LINUX-64-STATIC: movl $262144, %eax
; LINUX-64-STATIC: addq dptr(%rip), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam05:
+; LINUX-32-STATIC-LABEL: bam05:
; LINUX-32-STATIC: movl $262144, %eax
; LINUX-32-STATIC-NEXT: addl dptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam05:
+; LINUX-32-PIC-LABEL: bam05:
; LINUX-32-PIC: movl $262144, %eax
; LINUX-32-PIC-NEXT: addl dptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam05:
+; LINUX-64-PIC-LABEL: bam05:
; LINUX-64-PIC: movl $262144, %eax
; LINUX-64-PIC-NEXT: movq dptr@GOTPCREL(%rip), [[RCX:%r.x]]
; LINUX-64-PIC-NEXT: addq ([[RCX]]), %rax
define i8* @bam06() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @lsrc, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam06:
+; LINUX-64-STATIC-LABEL: bam06:
; LINUX-64-STATIC: movl $lsrc+262144, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam06:
+; LINUX-32-STATIC-LABEL: bam06:
; LINUX-32-STATIC: movl $lsrc+262144, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam06:
+; LINUX-32-PIC-LABEL: bam06:
; LINUX-32-PIC: movl $lsrc+262144, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam06:
+; LINUX-64-PIC-LABEL: bam06:
; LINUX-64-PIC: leaq lsrc+262144(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define i8* @bam07() nounwind {
entry:
ret i8* bitcast (i32* getelementptr ([131072 x i32]* @ldst, i32 0, i64 65536) to i8*)
-; LINUX-64-STATIC: bam07:
+; LINUX-64-STATIC-LABEL: bam07:
; LINUX-64-STATIC: movl $ldst+262144, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam07:
+; LINUX-32-STATIC-LABEL: bam07:
; LINUX-32-STATIC: movl $ldst+262144, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam07:
+; LINUX-32-PIC-LABEL: bam07:
; LINUX-32-PIC: movl $ldst+262144, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam07:
+; LINUX-64-PIC-LABEL: bam07:
; LINUX-64-PIC: leaq ldst+262144(%rip), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr i32* %0, i64 65536
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: bam08:
+; LINUX-64-STATIC-LABEL: bam08:
; LINUX-64-STATIC: movl $262144, %eax
; LINUX-64-STATIC: addq lptr(%rip), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: bam08:
+; LINUX-32-STATIC-LABEL: bam08:
; LINUX-32-STATIC: movl $262144, %eax
; LINUX-32-STATIC-NEXT: addl lptr, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: bam08:
+; LINUX-32-PIC-LABEL: bam08:
; LINUX-32-PIC: movl $262144, %eax
; LINUX-32-PIC-NEXT: addl lptr, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: bam08:
+; LINUX-64-PIC-LABEL: bam08:
; LINUX-64-PIC: movl $262144, %eax
; LINUX-64-PIC-NEXT: addq lptr(%rip), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cat00:
+; LINUX-64-STATIC-LABEL: cat00:
; LINUX-64-STATIC: leaq src+64(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat00:
+; LINUX-32-STATIC-LABEL: cat00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal src+64(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat00:
+; LINUX-32-PIC-LABEL: cat00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal src+64(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat00:
+; LINUX-64-PIC-LABEL: cat00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cxt00:
+; LINUX-64-STATIC-LABEL: cxt00:
; LINUX-64-STATIC: leaq xsrc+64(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cxt00:
+; LINUX-32-STATIC-LABEL: cxt00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal xsrc+64(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cxt00:
+; LINUX-32-PIC-LABEL: cxt00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal xsrc+64(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cxt00:
+; LINUX-64-PIC-LABEL: cxt00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cat01:
+; LINUX-64-STATIC-LABEL: cat01:
; LINUX-64-STATIC: leaq dst+64(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat01:
+; LINUX-32-STATIC-LABEL: cat01:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal dst+64(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat01:
+; LINUX-32-PIC-LABEL: cat01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal dst+64(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat01:
+; LINUX-64-PIC-LABEL: cat01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cxt01:
+; LINUX-64-STATIC-LABEL: cxt01:
; LINUX-64-STATIC: leaq xdst+64(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cxt01:
+; LINUX-32-STATIC-LABEL: cxt01:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal xdst+64(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cxt01:
+; LINUX-32-PIC-LABEL: cxt01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal xdst+64(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cxt01:
+; LINUX-64-PIC-LABEL: cxt01:
; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%2 = getelementptr i32* %0, i64 %1
%3 = bitcast i32* %2 to i8*
ret i8* %3
-; LINUX-64-STATIC: cat02:
+; LINUX-64-STATIC-LABEL: cat02:
; LINUX-64-STATIC: movq ptr(%rip), [[RAX:%r.x]]
; LINUX-64-STATIC: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat02:
+; LINUX-32-STATIC-LABEL: cat02:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat02:
+; LINUX-32-PIC-LABEL: cat02:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat02:
+; LINUX-64-PIC-LABEL: cat02:
; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cat03:
+; LINUX-64-STATIC-LABEL: cat03:
; LINUX-64-STATIC: leaq dsrc+64(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat03:
+; LINUX-32-STATIC-LABEL: cat03:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal dsrc+64(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat03:
+; LINUX-32-PIC-LABEL: cat03:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal dsrc+64(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat03:
+; LINUX-64-PIC-LABEL: cat03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cat04:
+; LINUX-64-STATIC-LABEL: cat04:
; LINUX-64-STATIC: leaq ddst+64(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat04:
+; LINUX-32-STATIC-LABEL: cat04:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ddst+64(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat04:
+; LINUX-32-PIC-LABEL: cat04:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ddst+64(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat04:
+; LINUX-64-PIC-LABEL: cat04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%2 = getelementptr i32* %0, i64 %1
%3 = bitcast i32* %2 to i8*
ret i8* %3
-; LINUX-64-STATIC: cat05:
+; LINUX-64-STATIC-LABEL: cat05:
; LINUX-64-STATIC: movq dptr(%rip), [[RAX:%r.x]]
; LINUX-64-STATIC: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat05:
+; LINUX-32-STATIC-LABEL: cat05:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat05:
+; LINUX-32-PIC-LABEL: cat05:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat05:
+; LINUX-64-PIC-LABEL: cat05:
; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cat06:
+; LINUX-64-STATIC-LABEL: cat06:
; LINUX-64-STATIC: leaq lsrc+64(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat06:
+; LINUX-32-STATIC-LABEL: cat06:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal lsrc+64(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat06:
+; LINUX-32-PIC-LABEL: cat06:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal lsrc+64(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat06:
+; LINUX-64-PIC-LABEL: cat06:
; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cat07:
+; LINUX-64-STATIC-LABEL: cat07:
; LINUX-64-STATIC: leaq ldst+64(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat07:
+; LINUX-32-STATIC-LABEL: cat07:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ldst+64(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat07:
+; LINUX-32-PIC-LABEL: cat07:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ldst+64(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat07:
+; LINUX-64-PIC-LABEL: cat07:
; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%2 = getelementptr i32* %0, i64 %1
%3 = bitcast i32* %2 to i8*
ret i8* %3
-; LINUX-64-STATIC: cat08:
+; LINUX-64-STATIC-LABEL: cat08:
; LINUX-64-STATIC: movq lptr(%rip), [[RAX:%r.x]]
; LINUX-64-STATIC: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cat08:
+; LINUX-32-STATIC-LABEL: cat08:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cat08:
+; LINUX-32-PIC-LABEL: cat08:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: leal 64([[ECX]],[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cat08:
+; LINUX-64-PIC-LABEL: cat08:
; LINUX-64-PIC: movq lptr(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 64([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [131072 x i32]* @src, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cam00:
+; LINUX-64-STATIC-LABEL: cam00:
; LINUX-64-STATIC: leaq src+262144(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam00:
+; LINUX-32-STATIC-LABEL: cam00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal src+262144(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam00:
+; LINUX-32-PIC-LABEL: cam00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal src+262144(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam00:
+; LINUX-64-PIC-LABEL: cam00:
; LINUX-64-PIC: movq src@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [32 x i32]* @xsrc, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cxm00:
+; LINUX-64-STATIC-LABEL: cxm00:
; LINUX-64-STATIC: leaq xsrc+262144(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cxm00:
+; LINUX-32-STATIC-LABEL: cxm00:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal xsrc+262144(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cxm00:
+; LINUX-32-PIC-LABEL: cxm00:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal xsrc+262144(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cxm00:
+; LINUX-64-PIC-LABEL: cxm00:
; LINUX-64-PIC: movq xsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [131072 x i32]* @dst, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cam01:
+; LINUX-64-STATIC-LABEL: cam01:
; LINUX-64-STATIC: leaq dst+262144(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam01:
+; LINUX-32-STATIC-LABEL: cam01:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal dst+262144(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam01:
+; LINUX-32-PIC-LABEL: cam01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal dst+262144(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam01:
+; LINUX-64-PIC-LABEL: cam01:
; LINUX-64-PIC: movq dst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [32 x i32]* @xdst, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cxm01:
+; LINUX-64-STATIC-LABEL: cxm01:
; LINUX-64-STATIC: leaq xdst+262144(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cxm01:
+; LINUX-32-STATIC-LABEL: cxm01:
; LINUX-32-STATIC: movl 4(%esp), %eax
; LINUX-32-STATIC-NEXT: leal xdst+262144(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cxm01:
+; LINUX-32-PIC-LABEL: cxm01:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal xdst+262144(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cxm01:
+; LINUX-64-PIC-LABEL: cxm01:
; LINUX-64-PIC: movq xdst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%2 = getelementptr i32* %0, i64 %1
%3 = bitcast i32* %2 to i8*
ret i8* %3
-; LINUX-64-STATIC: cam02:
+; LINUX-64-STATIC-LABEL: cam02:
; LINUX-64-STATIC: movq ptr(%rip), [[RAX:%r.x]]
; LINUX-64-STATIC: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam02:
+; LINUX-32-STATIC-LABEL: cam02:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam02:
+; LINUX-32-PIC-LABEL: cam02:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl ptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam02:
+; LINUX-64-PIC-LABEL: cam02:
; LINUX-64-PIC: movq ptr@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
%1 = getelementptr [131072 x i32]* @dsrc, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cam03:
+; LINUX-64-STATIC-LABEL: cam03:
; LINUX-64-STATIC: leaq dsrc+262144(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam03:
+; LINUX-32-STATIC-LABEL: cam03:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal dsrc+262144(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam03:
+; LINUX-32-PIC-LABEL: cam03:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal dsrc+262144(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam03:
+; LINUX-64-PIC-LABEL: cam03:
; LINUX-64-PIC: movq dsrc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [131072 x i32]* @ddst, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cam04:
+; LINUX-64-STATIC-LABEL: cam04:
; LINUX-64-STATIC: leaq ddst+262144(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam04:
+; LINUX-32-STATIC-LABEL: cam04:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ddst+262144(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam04:
+; LINUX-32-PIC-LABEL: cam04:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ddst+262144(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam04:
+; LINUX-64-PIC-LABEL: cam04:
; LINUX-64-PIC: movq ddst@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%2 = getelementptr i32* %0, i64 %1
%3 = bitcast i32* %2 to i8*
ret i8* %3
-; LINUX-64-STATIC: cam05:
+; LINUX-64-STATIC-LABEL: cam05:
; LINUX-64-STATIC: movq dptr(%rip), [[RAX:%r.x]]
; LINUX-64-STATIC: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam05:
+; LINUX-32-STATIC-LABEL: cam05:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam05:
+; LINUX-32-PIC-LABEL: cam05:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl dptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam05:
+; LINUX-64-PIC-LABEL: cam05:
; LINUX-64-PIC: movq dptr@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: movq ([[RAX]]), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
%1 = getelementptr [131072 x i32]* @lsrc, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cam06:
+; LINUX-64-STATIC-LABEL: cam06:
; LINUX-64-STATIC: leaq lsrc+262144(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam06:
+; LINUX-32-STATIC-LABEL: cam06:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal lsrc+262144(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam06:
+; LINUX-32-PIC-LABEL: cam06:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal lsrc+262144(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam06:
+; LINUX-64-PIC-LABEL: cam06:
; LINUX-64-PIC: leaq lsrc(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%1 = getelementptr [131072 x i32]* @ldst, i64 0, i64 %0
%2 = bitcast i32* %1 to i8*
ret i8* %2
-; LINUX-64-STATIC: cam07:
+; LINUX-64-STATIC-LABEL: cam07:
; LINUX-64-STATIC: leaq ldst+262144(,%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam07:
+; LINUX-32-STATIC-LABEL: cam07:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: leal ldst+262144(,[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam07:
+; LINUX-32-PIC-LABEL: cam07:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: leal ldst+262144(,[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam07:
+; LINUX-64-PIC-LABEL: cam07:
; LINUX-64-PIC: leaq ldst(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
%2 = getelementptr i32* %0, i64 %1
%3 = bitcast i32* %2 to i8*
ret i8* %3
-; LINUX-64-STATIC: cam08:
+; LINUX-64-STATIC-LABEL: cam08:
; LINUX-64-STATIC: movq lptr(%rip), [[RAX:%r.x]]
; LINUX-64-STATIC: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: cam08:
+; LINUX-32-STATIC-LABEL: cam08:
; LINUX-32-STATIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-STATIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-STATIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: cam08:
+; LINUX-32-PIC-LABEL: cam08:
; LINUX-32-PIC: movl 4(%esp), [[EAX:%e.x]]
; LINUX-32-PIC-NEXT: movl lptr, [[ECX:%e.x]]
; LINUX-32-PIC-NEXT: leal 262144([[ECX]],[[EAX]],4), %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: cam08:
+; LINUX-64-PIC-LABEL: cam08:
; LINUX-64-PIC: movq lptr(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: leaq 262144([[RAX]],%rdi,4), %rax
; LINUX-64-PIC-NEXT: ret
call void @x() nounwind
call void @x() nounwind
ret void
-; LINUX-64-STATIC: lcallee:
+; LINUX-64-STATIC-LABEL: lcallee:
; LINUX-64-STATIC: callq x
; LINUX-64-STATIC: callq x
; LINUX-64-STATIC: callq x
; LINUX-64-STATIC: callq x
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: lcallee:
+; LINUX-32-STATIC-LABEL: lcallee:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll x
; LINUX-32-STATIC-NEXT: calll x
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: lcallee:
+; LINUX-32-PIC-LABEL: lcallee:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll x
; LINUX-32-PIC-NEXT: calll x
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: lcallee:
+; LINUX-64-PIC-LABEL: lcallee:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq x@PLT
; LINUX-64-PIC-NEXT: callq x@PLT
call void @y() nounwind
call void @y() nounwind
ret void
-; LINUX-64-STATIC: dcallee:
+; LINUX-64-STATIC-LABEL: dcallee:
; LINUX-64-STATIC: callq y
; LINUX-64-STATIC: callq y
; LINUX-64-STATIC: callq y
; LINUX-64-STATIC: callq y
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: dcallee:
+; LINUX-32-STATIC-LABEL: dcallee:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll y
; LINUX-32-STATIC-NEXT: calll y
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: dcallee:
+; LINUX-32-PIC-LABEL: dcallee:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll y
; LINUX-32-PIC-NEXT: calll y
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: dcallee:
+; LINUX-64-PIC-LABEL: dcallee:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq y@PLT
; LINUX-64-PIC-NEXT: callq y@PLT
define void ()* @address() nounwind {
entry:
ret void ()* @callee
-; LINUX-64-STATIC: address:
+; LINUX-64-STATIC-LABEL: address:
; LINUX-64-STATIC: movl $callee, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: address:
+; LINUX-32-STATIC-LABEL: address:
; LINUX-32-STATIC: movl $callee, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: address:
+; LINUX-32-PIC-LABEL: address:
; LINUX-32-PIC: movl $callee, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: address:
+; LINUX-64-PIC-LABEL: address:
; LINUX-64-PIC: movq callee@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define void ()* @laddress() nounwind {
entry:
ret void ()* @lcallee
-; LINUX-64-STATIC: laddress:
+; LINUX-64-STATIC-LABEL: laddress:
; LINUX-64-STATIC: movl $lcallee, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: laddress:
+; LINUX-32-STATIC-LABEL: laddress:
; LINUX-32-STATIC: movl $lcallee, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: laddress:
+; LINUX-32-PIC-LABEL: laddress:
; LINUX-32-PIC: movl $lcallee, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: laddress:
+; LINUX-64-PIC-LABEL: laddress:
; LINUX-64-PIC: movq lcallee@GOTPCREL(%rip), %rax
; LINUX-64-PIC-NEXT: ret
define void ()* @daddress() nounwind {
entry:
ret void ()* @dcallee
-; LINUX-64-STATIC: daddress:
+; LINUX-64-STATIC-LABEL: daddress:
; LINUX-64-STATIC: movl $dcallee, %eax
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: daddress:
+; LINUX-32-STATIC-LABEL: daddress:
; LINUX-32-STATIC: movl $dcallee, %eax
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: daddress:
+; LINUX-32-PIC-LABEL: daddress:
; LINUX-32-PIC: movl $dcallee, %eax
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: daddress:
+; LINUX-64-PIC-LABEL: daddress:
; LINUX-64-PIC: leaq dcallee(%rip), %rax
; LINUX-64-PIC-NEXT: ret
call void @callee() nounwind
call void @callee() nounwind
ret void
-; LINUX-64-STATIC: caller:
+; LINUX-64-STATIC-LABEL: caller:
; LINUX-64-STATIC: callq callee
; LINUX-64-STATIC: callq callee
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: caller:
+; LINUX-32-STATIC-LABEL: caller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll callee
; LINUX-32-STATIC-NEXT: calll callee
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: caller:
+; LINUX-32-PIC-LABEL: caller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll callee
; LINUX-32-PIC-NEXT: calll callee
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: caller:
+; LINUX-64-PIC-LABEL: caller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq callee@PLT
; LINUX-64-PIC-NEXT: callq callee@PLT
call void @dcallee() nounwind
call void @dcallee() nounwind
ret void
-; LINUX-64-STATIC: dcaller:
+; LINUX-64-STATIC-LABEL: dcaller:
; LINUX-64-STATIC: callq dcallee
; LINUX-64-STATIC: callq dcallee
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: dcaller:
+; LINUX-32-STATIC-LABEL: dcaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll dcallee
; LINUX-32-STATIC-NEXT: calll dcallee
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: dcaller:
+; LINUX-32-PIC-LABEL: dcaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll dcallee
; LINUX-32-PIC-NEXT: calll dcallee
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: dcaller:
+; LINUX-64-PIC-LABEL: dcaller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq dcallee
; LINUX-64-PIC-NEXT: callq dcallee
call void @lcallee() nounwind
call void @lcallee() nounwind
ret void
-; LINUX-64-STATIC: lcaller:
+; LINUX-64-STATIC-LABEL: lcaller:
; LINUX-64-STATIC: callq lcallee
; LINUX-64-STATIC: callq lcallee
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: lcaller:
+; LINUX-32-STATIC-LABEL: lcaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll lcallee
; LINUX-32-STATIC-NEXT: calll lcallee
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: lcaller:
+; LINUX-32-PIC-LABEL: lcaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll lcallee
; LINUX-32-PIC-NEXT: calll lcallee
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: lcaller:
+; LINUX-64-PIC-LABEL: lcaller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq lcallee@PLT
; LINUX-64-PIC-NEXT: callq lcallee@PLT
entry:
call void @callee() nounwind
ret void
-; LINUX-64-STATIC: tailcaller:
+; LINUX-64-STATIC-LABEL: tailcaller:
; LINUX-64-STATIC: callq callee
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: tailcaller:
+; LINUX-32-STATIC-LABEL: tailcaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll callee
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: tailcaller:
+; LINUX-32-PIC-LABEL: tailcaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll callee
; LINUX-32-PIC-NEXT: addl
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: tailcaller:
+; LINUX-64-PIC-LABEL: tailcaller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq callee@PLT
; LINUX-64-PIC-NEXT: popq
entry:
call void @dcallee() nounwind
ret void
-; LINUX-64-STATIC: dtailcaller:
+; LINUX-64-STATIC-LABEL: dtailcaller:
; LINUX-64-STATIC: callq dcallee
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: dtailcaller:
+; LINUX-32-STATIC-LABEL: dtailcaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll dcallee
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: dtailcaller:
+; LINUX-32-PIC-LABEL: dtailcaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll dcallee
; LINUX-32-PIC-NEXT: addl
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: dtailcaller:
+; LINUX-64-PIC-LABEL: dtailcaller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq dcallee
; LINUX-64-PIC-NEXT: popq
entry:
call void @lcallee() nounwind
ret void
-; LINUX-64-STATIC: ltailcaller:
+; LINUX-64-STATIC-LABEL: ltailcaller:
; LINUX-64-STATIC: callq lcallee
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ltailcaller:
+; LINUX-32-STATIC-LABEL: ltailcaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll lcallee
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ltailcaller:
+; LINUX-32-PIC-LABEL: ltailcaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll lcallee
; LINUX-32-PIC-NEXT: addl
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ltailcaller:
+; LINUX-64-PIC-LABEL: ltailcaller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq lcallee@PLT
; LINUX-64-PIC-NEXT: popq
%1 = load void ()** @ifunc, align 8
call void %1() nounwind
ret void
-; LINUX-64-STATIC: icaller:
+; LINUX-64-STATIC-LABEL: icaller:
; LINUX-64-STATIC: callq *ifunc
; LINUX-64-STATIC: callq *ifunc
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: icaller:
+; LINUX-32-STATIC-LABEL: icaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll *ifunc
; LINUX-32-STATIC-NEXT: calll *ifunc
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: icaller:
+; LINUX-32-PIC-LABEL: icaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll *ifunc
; LINUX-32-PIC-NEXT: calll *ifunc
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: icaller:
+; LINUX-64-PIC-LABEL: icaller:
; LINUX-64-PIC: pushq [[RBX:%r.x]]
; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), [[RBX:%r.x]]
; LINUX-64-PIC-NEXT: callq *([[RBX]])
%1 = load void ()** @difunc, align 8
call void %1() nounwind
ret void
-; LINUX-64-STATIC: dicaller:
+; LINUX-64-STATIC-LABEL: dicaller:
; LINUX-64-STATIC: callq *difunc
; LINUX-64-STATIC: callq *difunc
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: dicaller:
+; LINUX-32-STATIC-LABEL: dicaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll *difunc
; LINUX-32-STATIC-NEXT: calll *difunc
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: dicaller:
+; LINUX-32-PIC-LABEL: dicaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll *difunc
; LINUX-32-PIC-NEXT: calll *difunc
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: dicaller:
+; LINUX-64-PIC-LABEL: dicaller:
; LINUX-64-PIC: pushq [[RBX:%r.x]]
; LINUX-64-PIC-NEXT: movq difunc@GOTPCREL(%rip), [[RBX:%r.x]]
; LINUX-64-PIC-NEXT: callq *([[RBX]])
%1 = load void ()** @lifunc, align 8
call void %1() nounwind
ret void
-; LINUX-64-STATIC: licaller:
+; LINUX-64-STATIC-LABEL: licaller:
; LINUX-64-STATIC: callq *lifunc
; LINUX-64-STATIC: callq *lifunc
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: licaller:
+; LINUX-32-STATIC-LABEL: licaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll *lifunc
; LINUX-32-STATIC-NEXT: calll *lifunc
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: licaller:
+; LINUX-32-PIC-LABEL: licaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll *lifunc
; LINUX-32-PIC-NEXT: calll *lifunc
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: licaller:
+; LINUX-64-PIC-LABEL: licaller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq *lifunc(%rip)
; LINUX-64-PIC-NEXT: callq *lifunc(%rip)
%1 = load void ()** @ifunc, align 8
call void %1() nounwind
ret void
-; LINUX-64-STATIC: itailcaller:
+; LINUX-64-STATIC-LABEL: itailcaller:
; LINUX-64-STATIC: callq *ifunc
; LINUX-64-STATIC: callq *ifunc
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: itailcaller:
+; LINUX-32-STATIC-LABEL: itailcaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll *ifunc
; LINUX-32-STATIC-NEXT: calll *ifunc
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: itailcaller:
+; LINUX-32-PIC-LABEL: itailcaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll *ifunc
; LINUX-32-PIC-NEXT: calll *ifunc
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: itailcaller:
+; LINUX-64-PIC-LABEL: itailcaller:
; LINUX-64-PIC: pushq [[RBX:%r.x]]
; LINUX-64-PIC-NEXT: movq ifunc@GOTPCREL(%rip), [[RBX:%r.x]]
; LINUX-64-PIC-NEXT: callq *([[RBX]])
%0 = load void ()** @difunc, align 8
call void %0() nounwind
ret void
-; LINUX-64-STATIC: ditailcaller:
+; LINUX-64-STATIC-LABEL: ditailcaller:
; LINUX-64-STATIC: callq *difunc
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: ditailcaller:
+; LINUX-32-STATIC-LABEL: ditailcaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll *difunc
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: ditailcaller:
+; LINUX-32-PIC-LABEL: ditailcaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll *difunc
; LINUX-32-PIC-NEXT: addl
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: ditailcaller:
+; LINUX-64-PIC-LABEL: ditailcaller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: movq difunc@GOTPCREL(%rip), [[RAX:%r.x]]
; LINUX-64-PIC-NEXT: callq *([[RAX]])
%0 = load void ()** @lifunc, align 8
call void %0() nounwind
ret void
-; LINUX-64-STATIC: litailcaller:
+; LINUX-64-STATIC-LABEL: litailcaller:
; LINUX-64-STATIC: callq *lifunc
; LINUX-64-STATIC: ret
-; LINUX-32-STATIC: litailcaller:
+; LINUX-32-STATIC-LABEL: litailcaller:
; LINUX-32-STATIC: subl
; LINUX-32-STATIC-NEXT: calll *lifunc
; LINUX-32-STATIC-NEXT: addl
; LINUX-32-STATIC-NEXT: ret
-; LINUX-32-PIC: litailcaller:
+; LINUX-32-PIC-LABEL: litailcaller:
; LINUX-32-PIC: subl
; LINUX-32-PIC-NEXT: calll *lifunc
; LINUX-32-PIC-NEXT: addl
; LINUX-32-PIC-NEXT: ret
-; LINUX-64-PIC: litailcaller:
+; LINUX-64-PIC-LABEL: litailcaller:
; LINUX-64-PIC: pushq
; LINUX-64-PIC-NEXT: callq *lifunc(%rip)
; LINUX-64-PIC-NEXT: popq
; Don't duplicate the load.
define fastcc i32 @foo(i32* %p) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: andl $10, %eax
; CHECK: je
%t0 = load i32* %p
define fastcc double @bar(i32 %hash, double %x, double %y) nounwind {
entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
%0 = and i32 %hash, 15
%1 = icmp ult i32 %0, 8
br i1 %1, label %bb11, label %bb10
; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse3 | FileCheck %s -check-prefix=WIN64
; PR8573
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: leaq (%rdi), %rax
; CHECK-NEXT: movl %esi, %ecx
; CHECK-NEXT: monitor
-; WIN64: foo:
+; WIN64-LABEL: foo:
; WIN64: leaq (%rcx), %rax
; WIN64-NEXT: movl %edx, %ecx
; WIN64-NEXT: movl %r8d, %edx
declare void @llvm.x86.sse3.monitor(i8*, i32, i32) nounwind
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: movl %edi, %ecx
; CHECK-NEXT: movl %esi, %eax
; CHECK-NEXT: mwait
-; WIN64: bar:
+; WIN64-LABEL: bar:
; WIN64: movl %edx, %eax
; WIN64-NEXT: mwait
define void @bar(i32 %E, i32 %H) nounwind {
@str = external global [12 x i8] ; <[12 x i8]*> [#uses=1]
define void @foo() {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK-NOT: ret
; CHECK: test1 $_GV
; CHECK-NOT: ret
entry:
; P suffix removes (rip) in -static 64-bit mode.
-; CHECK-PIC-64: test1:
+; CHECK-PIC-64-LABEL: test1:
; CHECK-PIC-64: movq G@GOTPCREL(%rip), %rax
; CHECK-PIC-64: frob (%rax) x
; CHECK-PIC-64: frob (%rax) x
-; CHECK-STATIC-64: test1:
+; CHECK-STATIC-64-LABEL: test1:
; CHECK-STATIC-64: frob G(%rip) x
; CHECK-STATIC-64: frob G x
-; CHECK-PIC-32: test1:
+; CHECK-PIC-32-LABEL: test1:
; CHECK-PIC-32: frob G x
; CHECK-PIC-32: frob G x
-; CHECK-STATIC-32: test1:
+; CHECK-STATIC-32-LABEL: test1:
; CHECK-STATIC-32: frob G x
; CHECK-STATIC-32: frob G x
define void @test3() nounwind {
entry:
-; CHECK-STATIC-64: test3:
+; CHECK-STATIC-64-LABEL: test3:
; CHECK-STATIC-64: call bar
; CHECK-STATIC-64: call test3
; CHECK-STATIC-64: call $bar
; CHECK-STATIC-64: call $test3
-; CHECK-STATIC-32: test3:
+; CHECK-STATIC-32-LABEL: test3:
; CHECK-STATIC-32: call bar
; CHECK-STATIC-32: call test3
; CHECK-STATIC-32: call $bar
; CHECK-STATIC-32: call $test3
-; CHECK-PIC-64: test3:
+; CHECK-PIC-64-LABEL: test3:
; CHECK-PIC-64: call bar@PLT
; CHECK-PIC-64: call test3@PLT
; CHECK-PIC-64: call $bar
; CHECK-PIC-64: call $test3
-; CHECK-PIC-32: test3:
+; CHECK-PIC-32-LABEL: test3:
; CHECK-PIC-32: call bar@PLT
; CHECK-PIC-32: call test3@PLT
; CHECK-PIC-32: call $bar
; Additional tests for 64-bit divide bypass
define i64 @Test_get_quotient(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_quotient:
+; CHECK-LABEL: Test_get_quotient:
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
}
define i64 @Test_get_remainder(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_remainder:
+; CHECK-LABEL: Test_get_remainder:
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
}
define i64 @Test_get_quotient_and_remainder(i64 %a, i64 %b) nounwind {
-; CHECK: Test_get_quotient_and_remainder:
+; CHECK-LABEL: Test_get_quotient_and_remainder:
; CHECK: movq %rdi, %rax
; CHECK: orq %rsi, %rax
; CHECK-NEXT: testq $-65536, %rax
; RUN: llc < %s -mcpu=atom -mtriple=i686-linux | FileCheck %s
define i32 @Test_get_quotient(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_quotient:
+; CHECK-LABEL: Test_get_quotient:
; CHECK: orl %ecx, %edx
; CHECK-NEXT: testl $-256, %edx
; CHECK-NEXT: je
}
define i32 @Test_get_remainder(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_remainder:
+; CHECK-LABEL: Test_get_remainder:
; CHECK: orl %ecx, %edx
; CHECK-NEXT: testl $-256, %edx
; CHECK-NEXT: je
}
define i32 @Test_get_quotient_and_remainder(i32 %a, i32 %b) nounwind {
-; CHECK: Test_get_quotient_and_remainder:
+; CHECK-LABEL: Test_get_quotient_and_remainder:
; CHECK: orl %ecx, %edx
; CHECK-NEXT: testl $-256, %edx
; CHECK-NEXT: je
}
define i32 @Test_use_div_and_idiv(i32 %a, i32 %b) nounwind {
-; CHECK: Test_use_div_and_idiv:
+; CHECK-LABEL: Test_use_div_and_idiv:
; CHECK: idivl
; CHECK: divb
; CHECK: divl
}
define i32 @Test_use_div_imm_imm() nounwind {
-; CHECK: Test_use_div_imm_imm:
+; CHECK-LABEL: Test_use_div_imm_imm:
; CHECK: movl $64
%resultdiv = sdiv i32 256, 4
ret i32 %resultdiv
}
define i32 @Test_use_div_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_div_reg_imm:
+; CHECK-LABEL: Test_use_div_reg_imm:
; CHECK-NOT: test
; CHECK-NOT: idiv
; CHECK-NOT: divb
}
define i32 @Test_use_rem_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_rem_reg_imm:
+; CHECK-LABEL: Test_use_rem_reg_imm:
; CHECK-NOT: test
; CHECK-NOT: idiv
; CHECK-NOT: divb
}
define i32 @Test_use_divrem_reg_imm(i32 %a) nounwind {
-; CHECK: Test_use_divrem_reg_imm:
+; CHECK-LABEL: Test_use_divrem_reg_imm:
; CHECK-NOT: test
; CHECK-NOT: idiv
; CHECK-NOT: divb
}
define i32 @Test_use_div_imm_reg(i32 %a) nounwind {
-; CHECK: Test_use_div_imm_reg:
+; CHECK-LABEL: Test_use_div_imm_reg:
; CHECK: test
; CHECK: idiv
; CHECK: divb
}
define i32 @Test_use_rem_imm_reg(i32 %a) nounwind {
-; CHECK: Test_use_rem_imm_reg:
+; CHECK-LABEL: Test_use_rem_imm_reg:
; CHECK: test
; CHECK: idiv
; CHECK: divb
@id = internal global i64 0, align 8
define void @tf_bug(i8* %ptr) nounwind {
-; PIC: tf_bug:
+; PIC-LABEL: tf_bug:
; PIC: movl _id-L1$pb(
; PIC: movl (_id-L1$pb)+4(
%tmp1 = atomicrmw add i64* @id, i64 1 seq_cst
%p.addr = alloca i64*, align 8
store i64* %p, i64** %p.addr, align 8
%tmp = load i64** %p.addr, align 8
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: movl $2147483648, %eax
; CHECK: lock
; CHECK-NEXT: orq %r{{.*}}, (%r{{.*}})
%p.addr = alloca i64*, align 8
store i64* %p, i64** %p.addr, align 8
%tmp = load i64** %p.addr, align 8
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: lock
; CHECK-NEXT: orq $2147483644, (%r{{.*}})
%0 = atomicrmw or i64* %tmp, i64 2147483644 seq_cst
define void @sub1(i32* nocapture %p, i32 %v) nounwind ssp {
entry:
-; CHECK: sub1:
+; CHECK-LABEL: sub1:
; CHECK: subl
%0 = atomicrmw sub i32* %p, i32 %v monotonic
ret void
define void @inc4(i64* nocapture %p) nounwind ssp {
entry:
-; CHECK: inc4:
+; CHECK-LABEL: inc4:
; CHECK: incq
%0 = atomicrmw add i64* %p, i64 1 monotonic
ret void
define void @add8(i64* nocapture %p) nounwind ssp {
entry:
-; CHECK: add8:
+; CHECK-LABEL: add8:
; CHECK: addq $2
%0 = atomicrmw add i64* %p, i64 2 monotonic
ret void
define void @add4(i64* nocapture %p, i32 %v) nounwind ssp {
entry:
-; CHECK: add4:
+; CHECK-LABEL: add4:
; CHECK: addq
%0 = sext i32 %v to i64 ; <i64> [#uses=1]
%1 = atomicrmw add i64* %p, i64 %0 monotonic
define void @inc3(i8* nocapture %p) nounwind ssp {
entry:
-; CHECK: inc3:
+; CHECK-LABEL: inc3:
; CHECK: incb
%0 = atomicrmw add i8* %p, i8 1 monotonic
ret void
define void @add7(i8* nocapture %p) nounwind ssp {
entry:
-; CHECK: add7:
+; CHECK-LABEL: add7:
; CHECK: addb $2
%0 = atomicrmw add i8* %p, i8 2 monotonic
ret void
define void @add3(i8* nocapture %p, i32 %v) nounwind ssp {
entry:
-; CHECK: add3:
+; CHECK-LABEL: add3:
; CHECK: addb
%0 = trunc i32 %v to i8 ; <i8> [#uses=1]
%1 = atomicrmw add i8* %p, i8 %0 monotonic
define void @inc2(i16* nocapture %p) nounwind ssp {
entry:
-; CHECK: inc2:
+; CHECK-LABEL: inc2:
; CHECK: incw
%0 = atomicrmw add i16* %p, i16 1 monotonic
ret void
define void @add6(i16* nocapture %p) nounwind ssp {
entry:
-; CHECK: add6:
+; CHECK-LABEL: add6:
; CHECK: addw $2
%0 = atomicrmw add i16* %p, i16 2 monotonic
ret void
define void @add2(i16* nocapture %p, i32 %v) nounwind ssp {
entry:
-; CHECK: add2:
+; CHECK-LABEL: add2:
; CHECK: addw
%0 = trunc i32 %v to i16 ; <i16> [#uses=1]
%1 = atomicrmw add i16* %p, i16 %0 monotonic
define void @inc1(i32* nocapture %p) nounwind ssp {
entry:
-; CHECK: inc1:
+; CHECK-LABEL: inc1:
; CHECK: incl
%0 = atomicrmw add i32* %p, i32 1 monotonic
ret void
define void @add5(i32* nocapture %p) nounwind ssp {
entry:
-; CHECK: add5:
+; CHECK-LABEL: add5:
; CHECK: addl $2
%0 = atomicrmw add i32* %p, i32 2 monotonic
ret void
define void @add1(i32* nocapture %p, i32 %v) nounwind ssp {
entry:
-; CHECK: add1:
+; CHECK-LABEL: add1:
; CHECK: addl
%0 = atomicrmw add i32* %p, i32 %v monotonic
ret void
define void @dec4(i64* nocapture %p) nounwind ssp {
entry:
-; CHECK: dec4:
+; CHECK-LABEL: dec4:
; CHECK: decq
%0 = atomicrmw sub i64* %p, i64 1 monotonic
ret void
define void @sub8(i64* nocapture %p) nounwind ssp {
entry:
-; CHECK: sub8:
+; CHECK-LABEL: sub8:
; CHECK: subq $2
%0 = atomicrmw sub i64* %p, i64 2 monotonic
ret void
define void @sub4(i64* nocapture %p, i32 %v) nounwind ssp {
entry:
-; CHECK: sub4:
+; CHECK-LABEL: sub4:
; CHECK: subq
%0 = sext i32 %v to i64 ; <i64> [#uses=1]
%1 = atomicrmw sub i64* %p, i64 %0 monotonic
define void @dec3(i8* nocapture %p) nounwind ssp {
entry:
-; CHECK: dec3:
+; CHECK-LABEL: dec3:
; CHECK: decb
%0 = atomicrmw sub i8* %p, i8 1 monotonic
ret void
define void @sub7(i8* nocapture %p) nounwind ssp {
entry:
-; CHECK: sub7:
+; CHECK-LABEL: sub7:
; CHECK: subb $2
%0 = atomicrmw sub i8* %p, i8 2 monotonic
ret void
define void @sub3(i8* nocapture %p, i32 %v) nounwind ssp {
entry:
-; CHECK: sub3:
+; CHECK-LABEL: sub3:
; CHECK: subb
%0 = trunc i32 %v to i8 ; <i8> [#uses=1]
%1 = atomicrmw sub i8* %p, i8 %0 monotonic
define void @dec2(i16* nocapture %p) nounwind ssp {
entry:
-; CHECK: dec2:
+; CHECK-LABEL: dec2:
; CHECK: decw
%0 = atomicrmw sub i16* %p, i16 1 monotonic
ret void
define void @sub6(i16* nocapture %p) nounwind ssp {
entry:
-; CHECK: sub6:
+; CHECK-LABEL: sub6:
; CHECK: subw $2
%0 = atomicrmw sub i16* %p, i16 2 monotonic
ret void
define void @sub2(i16* nocapture %p, i32 %v) nounwind ssp {
entry:
-; CHECK: sub2:
+; CHECK-LABEL: sub2:
; CHECK-NOT: negl
; CHECK: subw
%0 = trunc i32 %v to i16 ; <i16> [#uses=1]
define void @dec1(i32* nocapture %p) nounwind ssp {
entry:
-; CHECK: dec1:
+; CHECK-LABEL: dec1:
; CHECK: decl
%0 = atomicrmw sub i32* %p, i32 1 monotonic
ret void
define void @sub5(i32* nocapture %p) nounwind ssp {
entry:
-; CHECK: sub5:
+; CHECK-LABEL: sub5:
; CHECK: subl $2
%0 = atomicrmw sub i32* %p, i32 2 monotonic
ret void
; RUN: llc < %s -march=x86-64 -mattr=+avx -asm-verbose=false -enable-unsafe-fp-math -enable-no-nans-fp-math | FileCheck -check-prefix=UNSAFE %s
-; UNSAFE: maxpd:
+; UNSAFE-LABEL: maxpd:
; UNSAFE: vmaxpd {{.+}}, %xmm
define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
%max_is_x = fcmp oge <2 x double> %x, %y
ret <2 x double> %max
}
-; UNSAFE: minpd:
+; UNSAFE-LABEL: minpd:
; UNSAFE: vminpd {{.+}}, %xmm
define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
%min_is_x = fcmp ole <2 x double> %x, %y
ret <2 x double> %min
}
-; UNSAFE: maxps:
+; UNSAFE-LABEL: maxps:
; UNSAFE: vmaxps {{.+}}, %xmm
define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
%max_is_x = fcmp oge <4 x float> %x, %y
ret <4 x float> %max
}
-; UNSAFE: minps:
+; UNSAFE-LABEL: minps:
; UNSAFE: vminps {{.+}}, %xmm
define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
%min_is_x = fcmp ole <4 x float> %x, %y
ret <4 x float> %min
}
-; UNSAFE: vmaxpd:
+; UNSAFE-LABEL: vmaxpd:
; UNSAFE: vmaxpd {{.+}}, %ymm
define <4 x double> @vmaxpd(<4 x double> %x, <4 x double> %y) {
%max_is_x = fcmp oge <4 x double> %x, %y
ret <4 x double> %max
}
-; UNSAFE: vminpd:
+; UNSAFE-LABEL: vminpd:
; UNSAFE: vminpd {{.+}}, %ymm
define <4 x double> @vminpd(<4 x double> %x, <4 x double> %y) {
%min_is_x = fcmp ole <4 x double> %x, %y
ret <4 x double> %min
}
-; UNSAFE: vmaxps:
+; UNSAFE-LABEL: vmaxps:
; UNSAFE: vmaxps {{.+}}, %ymm
define <8 x float> @vmaxps(<8 x float> %x, <8 x float> %y) {
%max_is_x = fcmp oge <8 x float> %x, %y
ret <8 x float> %max
}
-; UNSAFE: vminps:
+; UNSAFE-LABEL: vminps:
; UNSAFE: vminps {{.+}}, %ymm
define <8 x float> @vminps(<8 x float> %x, <8 x float> %y) {
%min_is_x = fcmp ole <8 x float> %x, %y
define <4 x i64> @test1(<4 x i64> %a) nounwind {
%b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
ret <4 x i64>%b
- ; CHECK: test1:
+ ; CHECK-LABEL: test1:
; CHECK-NOT: vinsertf128
}
store i64 0, i64* %s
ret void
-; CHECK: t9:
+; CHECK-LABEL: t9:
; CHECK: vxorps %xmm
; CHECK-NOT: vextractf
; CHECK: vmovups
define <8 x i32> @signd(<8 x i32> %a, <8 x i32> %b) nounwind {
entry:
-; CHECK: signd:
+; CHECK-LABEL: signd:
; CHECK: psignd
; CHECK-NOT: sub
; CHECK: ret
define <8 x i32> @blendvb(<8 x i32> %b, <8 x i32> %a, <8 x i32> %c) nounwind {
entry:
-; CHECK: blendvb:
+; CHECK-LABEL: blendvb:
; CHECK: pblendvb
; CHECK: ret
%b.lobit = ashr <8 x i32> %b, <i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31, i32 31>
; RUN: llc < %s -march=x86-64 -mattr=+avx2 | FileCheck %s
-; CHECK: phaddw1:
+; CHECK-LABEL: phaddw1:
; CHECK: vphaddw
define <16 x i16> @phaddw1(<16 x i16> %x, <16 x i16> %y) {
%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
ret <16 x i16> %r
}
-; CHECK: phaddw2:
+; CHECK-LABEL: phaddw2:
; CHECK: vphaddw
define <16 x i16> @phaddw2(<16 x i16> %x, <16 x i16> %y) {
%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 17, i32 19, i32 21, i32 23, i32 9, i32 11, i32 13, i32 15, i32 25, i32 27, i32 29, i32 31>
ret <16 x i16> %r
}
-; CHECK: phaddd1:
+; CHECK-LABEL: phaddd1:
; CHECK: vphaddd
define <8 x i32> @phaddd1(<8 x i32> %x, <8 x i32> %y) {
%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
ret <8 x i32> %r
}
-; CHECK: phaddd2:
+; CHECK-LABEL: phaddd2:
; CHECK: vphaddd
define <8 x i32> @phaddd2(<8 x i32> %x, <8 x i32> %y) {
%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
ret <8 x i32> %r
}
-; CHECK: phaddd3:
+; CHECK-LABEL: phaddd3:
; CHECK: vphaddd
define <8 x i32> @phaddd3(<8 x i32> %x) {
%a = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
ret <8 x i32> %r
}
-; CHECK: phsubw1:
+; CHECK-LABEL: phsubw1:
; CHECK: vphsubw
define <16 x i16> @phsubw1(<16 x i16> %x, <16 x i16> %y) {
%a = shufflevector <16 x i16> %x, <16 x i16> %y, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 16, i32 18, i32 20, i32 22, i32 8, i32 10, i32 12, i32 14, i32 24, i32 26, i32 28, i32 30>
ret <16 x i16> %r
}
-; CHECK: phsubd1:
+; CHECK-LABEL: phsubd1:
; CHECK: vphsubd
define <8 x i32> @phsubd1(<8 x i32> %x, <8 x i32> %y) {
%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
ret <8 x i32> %r
}
-; CHECK: phsubd2:
+; CHECK-LABEL: phsubd2:
; CHECK: vphsubd
define <8 x i32> @phsubd2(<8 x i32> %x, <8 x i32> %y) {
%a = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> <i32 0, i32 undef, i32 8, i32 undef, i32 4, i32 6, i32 12, i32 14>
define <32 x i8> @shl9(<32 x i8> %A) nounwind {
%B = shl <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %B
-; CHECK: shl9:
+; CHECK-LABEL: shl9:
; CHECK: vpsllw $3
; CHECK: vpand
; CHECK: ret
define <32 x i8> @shr9(<32 x i8> %A) nounwind {
%B = lshr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %B
-; CHECK: shr9:
+; CHECK-LABEL: shr9:
; CHECK: vpsrlw $3
; CHECK: vpand
; CHECK: ret
define <32 x i8> @sra_v32i8_7(<32 x i8> %A) nounwind {
%B = ashr <32 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <32 x i8> %B
-; CHECK: sra_v32i8_7:
+; CHECK-LABEL: sra_v32i8_7:
; CHECK: vpxor
; CHECK: vpcmpgtb
; CHECK: ret
define <32 x i8> @sra_v32i8(<32 x i8> %A) nounwind {
%B = ashr <32 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <32 x i8> %B
-; CHECK: sra_v32i8:
+; CHECK-LABEL: sra_v32i8:
; CHECK: vpsrlw $3
; CHECK: vpand
; CHECK: vpxor
define i8 @t1(i8 %x) nounwind {
%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 false )
ret i8 %tmp
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: tzcntl
}
define i16 @t2(i16 %x) nounwind {
%tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 false )
ret i16 %tmp
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: tzcntw
}
define i32 @t3(i32 %x) nounwind {
%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 false )
ret i32 %tmp
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: tzcntl
}
%x1 = load i32* %x
%tmp = tail call i32 @llvm.cttz.i32(i32 %x1, i1 false )
ret i32 %tmp
-; CHECK: tzcnt32_load:
+; CHECK-LABEL: tzcnt32_load:
; CHECK: tzcntl ({{.*}})
}
define i64 @t4(i64 %x) nounwind {
%tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 false )
ret i64 %tmp
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: tzcntq
}
define i8 @t5(i8 %x) nounwind {
%tmp = tail call i8 @llvm.cttz.i8( i8 %x, i1 true )
ret i8 %tmp
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: tzcntl
}
define i16 @t6(i16 %x) nounwind {
%tmp = tail call i16 @llvm.cttz.i16( i16 %x, i1 true )
ret i16 %tmp
-; CHECK: t6:
+; CHECK-LABEL: t6:
; CHECK: tzcntw
}
define i32 @t7(i32 %x) nounwind {
%tmp = tail call i32 @llvm.cttz.i32( i32 %x, i1 true )
ret i32 %tmp
-; CHECK: t7:
+; CHECK-LABEL: t7:
; CHECK: tzcntl
}
define i64 @t8(i64 %x) nounwind {
%tmp = tail call i64 @llvm.cttz.i64( i64 %x, i1 true )
ret i64 %tmp
-; CHECK: t8:
+; CHECK-LABEL: t8:
; CHECK: tzcntq
}
%tmp1 = xor i32 %x, -1
%tmp2 = and i32 %y, %tmp1
ret i32 %tmp2
-; CHECK: andn32:
+; CHECK-LABEL: andn32:
; CHECK: andnl
}
%tmp1 = xor i32 %x, -1
%tmp2 = and i32 %y1, %tmp1
ret i32 %tmp2
-; CHECK: andn32_load:
+; CHECK-LABEL: andn32_load:
; CHECK: andnl ({{.*}})
}
%tmp1 = xor i64 %x, -1
%tmp2 = and i64 %tmp1, %y
ret i64 %tmp2
-; CHECK: andn64:
+; CHECK-LABEL: andn64:
; CHECK: andnq
}
define i32 @bextr32(i32 %x, i32 %y) nounwind readnone {
%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x, i32 %y)
ret i32 %tmp
-; CHECK: bextr32:
+; CHECK-LABEL: bextr32:
; CHECK: bextrl
}
%x1 = load i32* %x
%tmp = tail call i32 @llvm.x86.bmi.bextr.32(i32 %x1, i32 %y)
ret i32 %tmp
-; CHECK: bextr32_load:
+; CHECK-LABEL: bextr32_load:
; CHECK: bextrl {{.*}}, ({{.*}}), {{.*}}
}
define i64 @bextr64(i64 %x, i64 %y) nounwind readnone {
%tmp = tail call i64 @llvm.x86.bmi.bextr.64(i64 %x, i64 %y)
ret i64 %tmp
-; CHECK: bextr64:
+; CHECK-LABEL: bextr64:
; CHECK: bextrq
}
define i32 @bzhi32(i32 %x, i32 %y) nounwind readnone {
%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x, i32 %y)
ret i32 %tmp
-; CHECK: bzhi32:
+; CHECK-LABEL: bzhi32:
; CHECK: bzhil
}
%x1 = load i32* %x
%tmp = tail call i32 @llvm.x86.bmi.bzhi.32(i32 %x1, i32 %y)
ret i32 %tmp
-; CHECK: bzhi32_load:
+; CHECK-LABEL: bzhi32_load:
; CHECK: bzhil {{.*}}, ({{.*}}), {{.*}}
}
define i64 @bzhi64(i64 %x, i64 %y) nounwind readnone {
%tmp = tail call i64 @llvm.x86.bmi.bzhi.64(i64 %x, i64 %y)
ret i64 %tmp
-; CHECK: bzhi64:
+; CHECK-LABEL: bzhi64:
; CHECK: bzhiq
}
%tmp = sub i32 0, %x
%tmp2 = and i32 %x, %tmp
ret i32 %tmp2
-; CHECK: blsi32:
+; CHECK-LABEL: blsi32:
; CHECK: blsil
}
%tmp = sub i32 0, %x1
%tmp2 = and i32 %x1, %tmp
ret i32 %tmp2
-; CHECK: blsi32_load:
+; CHECK-LABEL: blsi32_load:
; CHECK: blsil ({{.*}})
}
%tmp = sub i64 0, %x
%tmp2 = and i64 %tmp, %x
ret i64 %tmp2
-; CHECK: blsi64:
+; CHECK-LABEL: blsi64:
; CHECK: blsiq
}
%tmp = sub i32 %x, 1
%tmp2 = xor i32 %x, %tmp
ret i32 %tmp2
-; CHECK: blsmsk32:
+; CHECK-LABEL: blsmsk32:
; CHECK: blsmskl
}
%tmp = sub i32 %x1, 1
%tmp2 = xor i32 %x1, %tmp
ret i32 %tmp2
-; CHECK: blsmsk32_load:
+; CHECK-LABEL: blsmsk32_load:
; CHECK: blsmskl ({{.*}})
}
%tmp = sub i64 %x, 1
%tmp2 = xor i64 %tmp, %x
ret i64 %tmp2
-; CHECK: blsmsk64:
+; CHECK-LABEL: blsmsk64:
; CHECK: blsmskq
}
%tmp = sub i32 %x, 1
%tmp2 = and i32 %x, %tmp
ret i32 %tmp2
-; CHECK: blsr32:
+; CHECK-LABEL: blsr32:
; CHECK: blsrl
}
%tmp = sub i32 %x1, 1
%tmp2 = and i32 %x1, %tmp
ret i32 %tmp2
-; CHECK: blsr32_load:
+; CHECK-LABEL: blsr32_load:
; CHECK: blsrl ({{.*}})
}
%tmp = sub i64 %x, 1
%tmp2 = and i64 %tmp, %x
ret i64 %tmp2
-; CHECK: blsr64:
+; CHECK-LABEL: blsr64:
; CHECK: blsrq
}
define i32 @pdep32(i32 %x, i32 %y) nounwind readnone {
%tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y)
ret i32 %tmp
-; CHECK: pdep32:
+; CHECK-LABEL: pdep32:
; CHECK: pdepl
}
%y1 = load i32* %y
%tmp = tail call i32 @llvm.x86.bmi.pdep.32(i32 %x, i32 %y1)
ret i32 %tmp
-; CHECK: pdep32_load:
+; CHECK-LABEL: pdep32_load:
; CHECK: pdepl ({{.*}})
}
define i64 @pdep64(i64 %x, i64 %y) nounwind readnone {
%tmp = tail call i64 @llvm.x86.bmi.pdep.64(i64 %x, i64 %y)
ret i64 %tmp
-; CHECK: pdep64:
+; CHECK-LABEL: pdep64:
; CHECK: pdepq
}
define i32 @pext32(i32 %x, i32 %y) nounwind readnone {
%tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y)
ret i32 %tmp
-; CHECK: pext32:
+; CHECK-LABEL: pext32:
; CHECK: pextl
}
%y1 = load i32* %y
%tmp = tail call i32 @llvm.x86.bmi.pext.32(i32 %x, i32 %y1)
ret i32 %tmp
-; CHECK: pext32_load:
+; CHECK-LABEL: pext32_load:
; CHECK: pextl ({{.*}})
}
define i64 @pext64(i64 %x, i64 %y) nounwind readnone {
%tmp = tail call i64 @llvm.x86.bmi.pext.64(i64 %x, i64 %y)
ret i64 %tmp
-; CHECK: pext64:
+; CHECK-LABEL: pext64:
; CHECK: pextq
}
define double @t1(float* nocapture %x) nounwind readonly ssp {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: movss ([[A0:%rdi|%rcx]]), %xmm0
; CHECK: cvtss2sd %xmm0, %xmm0
define float @t2(double* nocapture %x) nounwind readonly ssp optsize {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: cvtsd2ss ([[A0]]), %xmm0
%0 = load double* %x, align 8
%1 = fptrunc double %0 to float
define float @squirtf(float* %x) nounwind {
entry:
-; CHECK: squirtf:
+; CHECK-LABEL: squirtf:
; CHECK: movss ([[A0]]), %xmm0
; CHECK: sqrtss %xmm0, %xmm0
%z = load float* %x
define double @squirt(double* %x) nounwind {
entry:
-; CHECK: squirt:
+; CHECK-LABEL: squirt:
; CHECK: sqrtsd ([[A0]]), %xmm0
%z = load double* %x
%t = call double @llvm.sqrt.f64(double %z)
define float @squirtf_size(float* %x) nounwind optsize {
entry:
-; CHECK: squirtf_size:
+; CHECK-LABEL: squirtf_size:
; CHECK: sqrtss ([[A0]]), %xmm0
%z = load float* %x
%t = call float @llvm.sqrt.f32(float %z)
define double @squirt_size(double* %x) nounwind optsize {
entry:
-; CHECK: squirt_size:
+; CHECK-LABEL: squirt_size:
; CHECK: sqrtsd ([[A0]]), %xmm0
%z = load double* %x
%t = call double @llvm.sqrt.f64(double %z)
; CHK-NOT: InlineAsm
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: bswapq
define i64 @foo(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: bswapq
define i64 @bar(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}
-; CHECK: pen:
+; CHECK-LABEL: pen:
; CHECK: bswapl
define i32 @pen(i32 %x) nounwind {
%asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
ret i32 %asmtmp
}
-; CHECK: s16:
+; CHECK-LABEL: s16:
; CHECK: rolw $8,
define zeroext i16 @s16(i16 zeroext %x) nounwind {
%asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
ret i16 %asmtmp
}
-; CHECK: t16:
+; CHECK-LABEL: t16:
; CHECK: rolw $8,
define zeroext i16 @t16(i16 zeroext %x) nounwind {
%asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
ret i16 %asmtmp
}
-; CHECK: u16:
+; CHECK-LABEL: u16:
; CHECK: rolw $8,
define zeroext i16 @u16(i16 zeroext %x) nounwind {
%asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
ret i16 %asmtmp
}
-; CHECK: v16:
+; CHECK-LABEL: v16:
; CHECK: rolw $8,
define zeroext i16 @v16(i16 zeroext %x) nounwind {
%asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
ret i16 %asmtmp
}
-; CHECK: s32:
+; CHECK-LABEL: s32:
; CHECK: bswapl
define i32 @s32(i32 %x) nounwind {
%asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
ret i32 %asmtmp
}
-; CHECK: t32:
+; CHECK-LABEL: t32:
; CHECK: bswapl
define i32 @t32(i32 %x) nounwind {
%asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
ret i32 %asmtmp
}
-; CHECK: u32:
+; CHECK-LABEL: u32:
; CHECK: bswapl
define i32 @u32(i32 %x) nounwind {
%asmtmp = tail call i32 asm "rorw $$8, ${0:w};rorl $$16, $0;rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
ret i32 %asmtmp
}
-; CHECK: s64:
+; CHECK-LABEL: s64:
; CHECK: bswapq
define i64 @s64(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
ret i64 %asmtmp
}
-; CHECK: t64:
+; CHECK-LABEL: t64:
; CHECK: bswapq
define i64 @t64(i64 %x) nounwind {
%asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{fpsr},~{dirflag},~{flags}"(i64 %x) nounwind
declare i64 @llvm.bswap.i64(i64)
define i16 @W(i16 %A) {
-; CHECK: W:
+; CHECK-LABEL: W:
; CHECK: rolw $8, %ax
%Z = call i16 @llvm.bswap.i16( i16 %A ) ; <i16> [#uses=1]
ret i16 %Z
}
define i32 @X(i32 %A) {
-; CHECK: X:
+; CHECK-LABEL: X:
; CHECK: bswapl %eax
%Z = call i32 @llvm.bswap.i32( i32 %A ) ; <i32> [#uses=1]
ret i32 %Z
}
define i64 @Y(i64 %A) {
-; CHECK: Y:
+; CHECK-LABEL: Y:
; CHECK: bswapl %eax
; CHECK: bswapl %edx
%Z = call i64 @llvm.bswap.i64( i64 %A ) ; <i64> [#uses=1]
define i32 @main() nounwind {
entry:
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: movl $1, (%esp)
; CHECK: leal 16(%esp), %edi
; CHECK: leal 160(%esp), %esi
%struct.range_t = type { float, float, i32, i32, i32, [0 x i8] }
define i32 @decode_byte(%struct.decode_t* %decode) nounwind {
-; CHECK: decode_byte:
+; CHECK-LABEL: decode_byte:
; CHECK: pushl
; CHECK: popl
; CHECK: jmp
; XFAIL: *
define void @borf(i8* nocapture %in, i8* nocapture %out) nounwind {
-; CHECK: borf:
+; CHECK-LABEL: borf:
; CHECK-NOT: inc
; CHECK-NOT: leal 1(
; CHECK-NOT: leal -1(
; The comparison happens before the relevant use, but it can still be rewritten
; to compare with zero.
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: align
; CHECK: incl %eax
; CHECK-NEXT: decl %ecx
; could be made simpler.
define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK-NOT: ret
; CHECK: cmpl $10
; CHECK: ret
define i8 @cttz_i8(i8 %x) {
%tmp = call i8 @llvm.cttz.i8( i8 %x, i1 true )
ret i8 %tmp
-; CHECK: cttz_i8:
+; CHECK-LABEL: cttz_i8:
; CHECK: bsfl
; CHECK-NOT: cmov
; CHECK: ret
define i16 @cttz_i16(i16 %x) {
%tmp = call i16 @llvm.cttz.i16( i16 %x, i1 true )
ret i16 %tmp
-; CHECK: cttz_i16:
+; CHECK-LABEL: cttz_i16:
; CHECK: bsfw
; CHECK-NOT: cmov
; CHECK: ret
define i32 @cttz_i32(i32 %x) {
%tmp = call i32 @llvm.cttz.i32( i32 %x, i1 true )
ret i32 %tmp
-; CHECK: cttz_i32:
+; CHECK-LABEL: cttz_i32:
; CHECK: bsfl
; CHECK-NOT: cmov
; CHECK: ret
define i64 @cttz_i64(i64 %x) {
%tmp = call i64 @llvm.cttz.i64( i64 %x, i1 true )
ret i64 %tmp
-; CHECK: cttz_i64:
+; CHECK-LABEL: cttz_i64:
; CHECK: bsfq
; CHECK-NOT: cmov
; CHECK: ret
entry:
%tmp2 = call i8 @llvm.ctlz.i8( i8 %x, i1 true )
ret i8 %tmp2
-; CHECK: ctlz_i8:
+; CHECK-LABEL: ctlz_i8:
; CHECK: bsrl
; CHECK-NOT: cmov
; CHECK: xorl $7,
entry:
%tmp2 = call i16 @llvm.ctlz.i16( i16 %x, i1 true )
ret i16 %tmp2
-; CHECK: ctlz_i16:
+; CHECK-LABEL: ctlz_i16:
; CHECK: bsrw
; CHECK-NOT: cmov
; CHECK: xorl $15,
define i32 @ctlz_i32(i32 %x) {
%tmp = call i32 @llvm.ctlz.i32( i32 %x, i1 true )
ret i32 %tmp
-; CHECK: ctlz_i32:
+; CHECK-LABEL: ctlz_i32:
; CHECK: bsrl
; CHECK-NOT: cmov
; CHECK: xorl $31,
define i64 @ctlz_i64(i64 %x) {
%tmp = call i64 @llvm.ctlz.i64( i64 %x, i1 true )
ret i64 %tmp
-; CHECK: ctlz_i64:
+; CHECK-LABEL: ctlz_i64:
; CHECK: bsrq
; CHECK-NOT: cmov
; CHECK: xorq $63,
define i32 @ctlz_i32_cmov(i32 %n) {
entry:
; Generate a cmov to handle zero inputs when necessary.
-; CHECK: ctlz_i32_cmov:
+; CHECK-LABEL: ctlz_i32_cmov:
; CHECK: bsrl
; CHECK: cmov
; CHECK: xorl $31,
; Don't generate the cmovne when the source is known non-zero (and bsr would
; not set ZF).
; rdar://9490949
-; CHECK: ctlz_i32_fold_cmov:
+; CHECK-LABEL: ctlz_i32_fold_cmov:
; CHECK: bsrl
; CHECK-NOT: cmov
; CHECK: xorl $31,
entry:
; Don't generate any xors when a 'ctlz' intrinsic is actually used to compute
; the most significant bit, which is what 'bsr' does natively.
-; CHECK: ctlz_bsr:
+; CHECK-LABEL: ctlz_bsr:
; CHECK: bsrl
; CHECK-NOT: xorl
; CHECK: ret
entry:
; Same as ctlz_bsr, but ensure this happens even when there is a potential
; zero.
-; CHECK: ctlz_bsr_cmov:
+; CHECK-LABEL: ctlz_bsr_cmov:
; CHECK: bsrl
; CHECK-NOT: xorl
; CHECK: ret
ret void
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: movss 12([[THIS:%[a-zA-Z0-9]+]]), [[REGISTER:%[a-zA-Z0-9]+]]
; CHECK-NEXT: movss [[REGISTER]], 60([[THIS]])
define i32 @foo() nounwind readonly {
entry:
-; CHECK-SMALL: foo:
+; CHECK-SMALL-LABEL: foo:
; CHECK-SMALL: movl data(%rip), %eax
-; CHECK-KERNEL: foo:
+; CHECK-KERNEL-LABEL: foo:
; CHECK-KERNEL: movl data, %eax
%0 = load i32* getelementptr ([0 x i32]* @data, i64 0, i64 0), align 4 ; <i32> [#uses=1]
ret i32 %0
define i32 @foo2() nounwind readonly {
entry:
-; CHECK-SMALL: foo2:
+; CHECK-SMALL-LABEL: foo2:
; CHECK-SMALL: movl data+40(%rip), %eax
-; CHECK-KERNEL: foo2:
+; CHECK-KERNEL-LABEL: foo2:
; CHECK-KERNEL: movl data+40, %eax
%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 10), align 4 ; <i32> [#uses=1]
ret i32 %0
define i32 @foo3() nounwind readonly {
entry:
-; CHECK-SMALL: foo3:
+; CHECK-SMALL-LABEL: foo3:
; CHECK-SMALL: movl data-40(%rip), %eax
-; CHECK-KERNEL: foo3:
+; CHECK-KERNEL-LABEL: foo3:
; CHECK-KERNEL: movq $-40, %rax
%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -10), align 4 ; <i32> [#uses=1]
ret i32 %0
define i32 @foo4() nounwind readonly {
entry:
; FIXME: We really can use movabsl here!
-; CHECK-SMALL: foo4:
+; CHECK-SMALL-LABEL: foo4:
; CHECK-SMALL: movl $16777216, %eax
; CHECK-SMALL: movl data(%rax), %eax
-; CHECK-KERNEL: foo4:
+; CHECK-KERNEL-LABEL: foo4:
; CHECK-KERNEL: movl data+16777216, %eax
%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194304), align 4 ; <i32> [#uses=1]
ret i32 %0
define i32 @foo1() nounwind readonly {
entry:
-; CHECK-SMALL: foo1:
+; CHECK-SMALL-LABEL: foo1:
; CHECK-SMALL: movl data+16777212(%rip), %eax
-; CHECK-KERNEL: foo1:
+; CHECK-KERNEL-LABEL: foo1:
; CHECK-KERNEL: movl data+16777212, %eax
%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 4194303), align 4 ; <i32> [#uses=1]
ret i32 %0
}
define i32 @foo5() nounwind readonly {
entry:
-; CHECK-SMALL: foo5:
+; CHECK-SMALL-LABEL: foo5:
; CHECK-SMALL: movl data-16777216(%rip), %eax
-; CHECK-KERNEL: foo5:
+; CHECK-KERNEL-LABEL: foo5:
; CHECK-KERNEL: movq $-16777216, %rax
%0 = load i32* getelementptr ([0 x i32]* @data, i32 0, i64 -4194304), align 4 ; <i32> [#uses=1]
ret i32 %0
declare void @ext(i32)
define i32 @t1(i32 %X, i32 %Y) nounwind {
-; LINUX: t1:
+; LINUX-LABEL: t1:
; LINUX: movl 4(%esp), %eax
; LINUX: movl 8(%esp), %ecx
; LINUX: addl %eax, %ecx
}
define i32 @t2(i32 %X, i32 %Y) nounwind {
-; LINUX: t2:
+; LINUX-LABEL: t2:
; LINUX: movl 4(%esp), %eax
; LINUX: movl 8(%esp), %ecx
; LINUX: xorl %eax, %ecx
define %0 @t3(i32 %lb, i8 zeroext %has_lb, i8 zeroext %lb_inclusive, i32 %ub, i8 zeroext %has_ub, i8 zeroext %ub_inclusive) nounwind {
entry:
-; DARWIN: t3:
+; DARWIN-LABEL: t3:
; DARWIN: shll $16
; DARWIN: shlq $32, %rcx
; DARWIN-NOT: leaq
; Convert oeq and une to ole/oge/ule/uge when comparing with infinity
; and negative infinity, because those are more efficient on x86.
-; CHECK: oeq_inff:
+; CHECK-LABEL: oeq_inff:
; CHECK: ucomiss
; CHECK: jb
define float @oeq_inff(float %x, float %y) nounwind readonly {
ret float %t1
}
-; CHECK: oeq_inf:
+; CHECK-LABEL: oeq_inf:
; CHECK: ucomisd
; CHECK: jb
define double @oeq_inf(double %x, double %y) nounwind readonly {
ret double %t1
}
-; CHECK: une_inff:
+; CHECK-LABEL: une_inff:
; CHECK: ucomiss
; CHECK: jae
define float @une_inff(float %x, float %y) nounwind readonly {
ret float %t1
}
-; CHECK: une_inf:
+; CHECK-LABEL: une_inf:
; CHECK: ucomisd
; CHECK: jae
define double @une_inf(double %x, double %y) nounwind readonly {
ret double %t1
}
-; CHECK: oeq_neg_inff:
+; CHECK-LABEL: oeq_neg_inff:
; CHECK: ucomiss
; CHECK: jb
define float @oeq_neg_inff(float %x, float %y) nounwind readonly {
ret float %t1
}
-; CHECK: oeq_neg_inf:
+; CHECK-LABEL: oeq_neg_inf:
; CHECK: ucomisd
; CHECK: jb
define double @oeq_neg_inf(double %x, double %y) nounwind readonly {
ret double %t1
}
-; CHECK: une_neg_inff:
+; CHECK-LABEL: une_neg_inff:
; CHECK: ucomiss
; CHECK: jae
define float @une_neg_inff(float %x, float %y) nounwind readonly {
ret float %t1
}
-; CHECK: une_neg_inf:
+; CHECK-LABEL: une_neg_inf:
; CHECK: ucomisd
; CHECK: jae
define double @une_neg_inf(double %x, double %y) nounwind readonly {
; RUN: llc < %s -march=x86-64 -mattr=+sse2 -mcpu=core2 | FileCheck %s
define i32 @t(<2 x i64>* %val) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK-NOT: movd
; CHECK: movl 8(
; CHECK-NEXT: ret
; Case where extractelement of load ends up as undef.
; (Making sure this doesn't crash.)
define i32 @t2(<8 x i32>* %xp) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: ret
%x = load <8 x i32>* %xp
%Shuff68 = shufflevector <8 x i32> %x, <8 x i32> undef, <8 x i32> <i32
; SSE2: xor
; SSE2-NOT: xor
-; CHECK: doo:
+; CHECK-LABEL: doo:
; CHECK: xor
define double @doo(double %x) nounwind {
%y = fsub double -0.0, %x
ret double %y
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: xor
define float @foo(float %x) nounwind {
%y = fsub float -0.0, %x
store i32 %2, i32* @src
ret i32 %2
; This should fold one of the loads into the add.
-; CHECK: loadgv:
+; CHECK-LABEL: loadgv:
; CHECK: movl L_src$non_lazy_ptr, %ecx
; CHECK: movl (%ecx), %eax
; CHECK: addl (%ecx), %eax
define zeroext i8 @test1(i32 %y) nounwind {
%conv = trunc i32 %y to i8
ret i8 %conv
- ; CHECK: test1:
+ ; CHECK-LABEL: test1:
; CHECK: movzbl {{.*}}, %eax
}
define signext i8 @test2(i32 %y) nounwind {
%conv = trunc i32 %y to i8
ret i8 %conv
- ; CHECK: test2:
+ ; CHECK-LABEL: test2:
; CHECK: movsbl {{.*}}, %eax
}
define zeroext i16 @test3(i32 %y) nounwind {
%conv = trunc i32 %y to i16
ret i16 %conv
- ; CHECK: test3:
+ ; CHECK-LABEL: test3:
; CHECK: movzwl {{.*}}, %eax
}
define signext i16 @test4(i32 %y) nounwind {
%conv = trunc i32 %y to i16
ret i16 %conv
- ; CHECK: test4:
+ ; CHECK-LABEL: test4:
; CHECK: {{(movswl.%.x, %eax|cwtl)}}
}
define zeroext i1 @test5(i32 %y) nounwind {
%conv = trunc i32 %y to i1
ret i1 %conv
- ; CHECK: test5:
+ ; CHECK-LABEL: test5:
; CHECK: andb $1
; CHECK: movzbl {{.*}}, %eax
}
ret i32 %s
}
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: leal v@TLSGD
; CHECK: __tls_get_addr
ret i32 %s
}
-; CHECK: f_alias:
+; CHECK-LABEL: f_alias:
; CHECK: leal v@TLSGD
; CHECK: __tls_get_addr
@llvm.used = appending global [1 x i8*] [i8* bitcast (i32 (i32)* @longest_match to i8*)] ; <[1 x i8*]*> [#uses=0]
define fastcc i32 @longest_match(i32 %cur_match) nounwind {
-; CHECK: longest_match:
+; CHECK-LABEL: longest_match:
; CHECK-NOT: ret
; CHECK: cmpb $0, (%r{{.*}},%r{{.*}})
; CHECK: ret
; RUN: llc < %s -march=x86 | FileCheck %s
define i32 @t1(i8* %X, i32 %i) {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK-NOT: and
; CHECK: movzbl
; CHECK: movl (%{{...}},%{{...}},4),
}
define i32 @t2(i16* %X, i32 %i) {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK-NOT: and
; CHECK: movzwl
; CHECK: movl (%{{...}},%{{...}},4),
; To make matters worse, because of the two-phase zext of %i and their reuse in
; the function, the DAG can get confusing trying to re-use both of them and
; prevent easy analysis of the mask in order to match this.
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK-NOT: and
; CHECK: shrl
; CHECK: addl (%{{...}},%{{...}},4),
define i32 @t4(i16* %i.ptr, i32* %arr) {
; A version of @t3 that has more zero extends and more re-use of intermediate
; values. This exercise slightly different bits of canonicalization.
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK-NOT: and
; CHECK: shrl
; CHECK: addl (%{{...}},%{{...}},4),
define <2 x double> @foo() nounwind {
ret <2 x double> bitcast (<2 x i64><i64 -1, i64 -1> to <2 x double>)
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: pcmpeqd %xmm0, %xmm0
; CHECK-NOT: %xmm
; CHECK: ret
}
define <2 x double> @bar() nounwind {
ret <2 x double> bitcast (<2 x i64><i64 0, i64 0> to <2 x double>)
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: xorps %xmm0, %xmm0
; CHECK-NOT: %xmm
; CHECK: ret
; CHECK: .space 16,255
; No pcmpeqd instructions, everybody uses the constant pool.
-; CHECK: program_1:
+; CHECK-LABEL: program_1:
; CHECK-NOT: pcmpeqd
%struct.__ImageExecInfo = type <{ <4 x i32>, <4 x float>, <2 x i64>, i8*, i8*, i8*, i32, i32, i32, i32, i32 }>
}
define i64 @g(i32 %i) nounwind {
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: pushl %ebp
; CHECK-NEXT: movl %esp, %ebp
; CHECK-NEXT: pushl
; RUN: llc < %s -mtriple x86_64-apple-darwin | FileCheck %s
define void @bar(i32 %argc) #0 {
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: pushq %rbp
entry:
%conv = sitofp i32 %argc to double
}
define void @qux(i32 %argc) #1 {
-; CHECK: qux:
+; CHECK-LABEL: qux:
; CHECK-NOT: pushq %rbp
entry:
%conv = sitofp i32 %argc to double
define i32 @t1() nounwind readnone {
entry:
-; FP-ELIM: t1:
+; FP-ELIM-LABEL: t1:
; FP-ELIM-NEXT: movl
; FP-ELIM-NEXT: ret
-; NO-ELIM: t1:
+; NO-ELIM-LABEL: t1:
; NO-ELIM-NEXT: pushl %ebp
; NO-ELIM: popl %ebp
; NO-ELIM-NEXT: ret
-; NON-LEAF: t1:
+; NON-LEAF-LABEL: t1:
; NON-LEAF-NEXT: movl
; NON-LEAF-NEXT: ret
ret i32 10
define void @t2() nounwind {
entry:
-; FP-ELIM: t2:
+; FP-ELIM-LABEL: t2:
; FP-ELIM-NOT: pushl %ebp
; FP-ELIM: ret
-; NO-ELIM: t2:
+; NO-ELIM-LABEL: t2:
; NO-ELIM-NEXT: pushl %ebp
; NO-ELIM: popl %ebp
; NO-ELIM-NEXT: ret
-; NON-LEAF: t2:
+; NON-LEAF-LABEL: t2:
; NON-LEAF-NEXT: pushl %ebp
; NON-LEAF: popl %ebp
; NON-LEAF-NEXT: ret
%tmp.1 = fadd double %P, 1.230000e+02 ; <double> [#uses=1]
ret double %tmp.1
}
-; CHECK: foo_add:
+; CHECK-LABEL: foo_add:
; CHECK: fadd DWORD PTR
define double @foo_mul(double %P) {
%tmp.1 = fmul double %P, 1.230000e+02 ; <double> [#uses=1]
ret double %tmp.1
}
-; CHECK: foo_mul:
+; CHECK-LABEL: foo_mul:
; CHECK: fmul DWORD PTR
define double @foo_sub(double %P) {
%tmp.1 = fsub double %P, 1.230000e+02 ; <double> [#uses=1]
ret double %tmp.1
}
-; CHECK: foo_sub:
+; CHECK-LABEL: foo_sub:
; CHECK: fadd DWORD PTR
define double @foo_subr(double %P) {
%tmp.1 = fsub double 1.230000e+02, %P ; <double> [#uses=1]
ret double %tmp.1
}
-; CHECK: foo_subr:
+; CHECK-LABEL: foo_subr:
; CHECK: fsub QWORD PTR
define double @foo_div(double %P) {
%tmp.1 = fdiv double %P, 1.230000e+02 ; <double> [#uses=1]
ret double %tmp.1
}
-; CHECK: foo_div:
+; CHECK-LABEL: foo_div:
; CHECK: fdiv DWORD PTR
define double @foo_divr(double %P) {
%tmp.1 = fdiv double 1.230000e+02, %P ; <double> [#uses=1]
ret double %tmp.1
}
-; CHECK: foo_divr:
+; CHECK-LABEL: foo_divr:
; CHECK: fdiv QWORD PTR
; of h registers yet, due to x86 encoding complications.
define void @bar64(i64 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar64:
+; X86-64-LABEL: bar64:
; X86-64: shrq $8, %rdi
; X86-64: incb %dil
; See FIXME: on regclass GR8.
; It could be optimally transformed like; incb %ch; movb %ch, (%rdx)
-; WIN64: bar64:
+; WIN64-LABEL: bar64:
; WIN64: shrq $8, %rcx
; WIN64: incb %cl
-; X86-32: bar64:
+; X86-32-LABEL: bar64:
; X86-32: incb %ah
%t0 = lshr i64 %x, 8
%t1 = trunc i64 %t0 to i8
}
define void @bar32(i32 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar32:
+; X86-64-LABEL: bar32:
; X86-64: shrl $8, %edi
; X86-64: incb %dil
-; WIN64: bar32:
+; WIN64-LABEL: bar32:
; WIN64: shrl $8, %ecx
; WIN64: incb %cl
-; X86-32: bar32:
+; X86-32-LABEL: bar32:
; X86-32: incb %ah
%t0 = lshr i32 %x, 8
%t1 = trunc i32 %t0 to i8
}
define void @bar16(i16 inreg %x, i8* inreg %p) nounwind {
-; X86-64: bar16:
+; X86-64-LABEL: bar16:
; X86-64: shrl $8, %edi
; X86-64: incb %dil
-; WIN64: bar16:
+; WIN64-LABEL: bar16:
; WIN64: shrl $8, %ecx
; WIN64: incb %cl
-; X86-32: bar16:
+; X86-32-LABEL: bar16:
; X86-32: incb %ah
%t0 = lshr i16 %x, 8
%t1 = trunc i16 %t0 to i8
}
define i64 @qux64(i64 inreg %x) nounwind {
-; X86-64: qux64:
+; X86-64-LABEL: qux64:
; X86-64: movq %rdi, %rax
; X86-64: movzbl %ah, %eax
-; WIN64: qux64:
+; WIN64-LABEL: qux64:
; WIN64: movzbl %ch, %eax
-; X86-32: qux64:
+; X86-32-LABEL: qux64:
; X86-32: movzbl %ah, %eax
%t0 = lshr i64 %x, 8
%t1 = and i64 %t0, 255
}
define i32 @qux32(i32 inreg %x) nounwind {
-; X86-64: qux32:
+; X86-64-LABEL: qux32:
; X86-64: movl %edi, %eax
; X86-64: movzbl %ah, %eax
-; WIN64: qux32:
+; WIN64-LABEL: qux32:
; WIN64: movzbl %ch, %eax
-; X86-32: qux32:
+; X86-32-LABEL: qux32:
; X86-32: movzbl %ah, %eax
%t0 = lshr i32 %x, 8
%t1 = and i32 %t0, 255
}
define i16 @qux16(i16 inreg %x) nounwind {
-; X86-64: qux16:
+; X86-64-LABEL: qux16:
; X86-64: movl %edi, %eax
; X86-64: movzbl %ah, %eax
-; WIN64: qux16:
+; WIN64-LABEL: qux16:
; WIN64: movzbl %ch, %eax
-; X86-32: qux16:
+; X86-32-LABEL: qux16:
; X86-32: movzbl %ah, %eax
%t0 = lshr i16 %x, 8
ret i16 %t0
; non-address use(s).
define i32 @foo(i8* %x, i32 %y) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK-NOT: ret
; CHECK: movzbl %{{[abcd]h}},
; CHECK-NOT: ret
; RUN: llc < %s -march=x86-64 -mattr=+sse3,-avx | FileCheck %s -check-prefix=SSE3
; RUN: llc < %s -march=x86-64 -mattr=-sse3,+avx | FileCheck %s -check-prefix=AVX
-; SSE3: haddpd1:
+; SSE3-LABEL: haddpd1:
; SSE3-NOT: vhaddpd
; SSE3: haddpd
-; AVX: haddpd1:
+; AVX-LABEL: haddpd1:
; AVX: vhaddpd
define <2 x double> @haddpd1(<2 x double> %x, <2 x double> %y) {
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
ret <2 x double> %r
}
-; SSE3: haddpd2:
+; SSE3-LABEL: haddpd2:
; SSE3-NOT: vhaddpd
; SSE3: haddpd
-; AVX: haddpd2:
+; AVX-LABEL: haddpd2:
; AVX: vhaddpd
define <2 x double> @haddpd2(<2 x double> %x, <2 x double> %y) {
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 1, i32 2>
ret <2 x double> %r
}
-; SSE3: haddpd3:
+; SSE3-LABEL: haddpd3:
; SSE3-NOT: vhaddpd
; SSE3: haddpd
-; AVX: haddpd3:
+; AVX-LABEL: haddpd3:
; AVX: vhaddpd
define <2 x double> @haddpd3(<2 x double> %x) {
%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
ret <2 x double> %r
}
-; SSE3: haddps1:
+; SSE3-LABEL: haddps1:
; SSE3-NOT: vhaddps
; SSE3: haddps
-; AVX: haddps1:
+; AVX-LABEL: haddps1:
; AVX: vhaddps
define <4 x float> @haddps1(<4 x float> %x, <4 x float> %y) {
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x float> %r
}
-; SSE3: haddps2:
+; SSE3-LABEL: haddps2:
; SSE3-NOT: vhaddps
; SSE3: haddps
-; AVX: haddps2:
+; AVX-LABEL: haddps2:
; AVX: vhaddps
define <4 x float> @haddps2(<4 x float> %x, <4 x float> %y) {
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
ret <4 x float> %r
}
-; SSE3: haddps3:
+; SSE3-LABEL: haddps3:
; SSE3-NOT: vhaddps
; SSE3: haddps
-; AVX: haddps3:
+; AVX-LABEL: haddps3:
; AVX: vhaddps
define <4 x float> @haddps3(<4 x float> %x) {
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
ret <4 x float> %r
}
-; SSE3: haddps4:
+; SSE3-LABEL: haddps4:
; SSE3-NOT: vhaddps
; SSE3: haddps
-; AVX: haddps4:
+; AVX-LABEL: haddps4:
; AVX: vhaddps
define <4 x float> @haddps4(<4 x float> %x) {
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
ret <4 x float> %r
}
-; SSE3: haddps5:
+; SSE3-LABEL: haddps5:
; SSE3-NOT: vhaddps
; SSE3: haddps
-; AVX: haddps5:
+; AVX-LABEL: haddps5:
; AVX: vhaddps
define <4 x float> @haddps5(<4 x float> %x) {
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
ret <4 x float> %r
}
-; SSE3: haddps6:
+; SSE3-LABEL: haddps6:
; SSE3-NOT: vhaddps
; SSE3: haddps
-; AVX: haddps6:
+; AVX-LABEL: haddps6:
; AVX: vhaddps
define <4 x float> @haddps6(<4 x float> %x) {
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x float> %r
}
-; SSE3: haddps7:
+; SSE3-LABEL: haddps7:
; SSE3-NOT: vhaddps
; SSE3: haddps
-; AVX: haddps7:
+; AVX-LABEL: haddps7:
; AVX: vhaddps
define <4 x float> @haddps7(<4 x float> %x) {
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
ret <4 x float> %r
}
-; SSE3: hsubpd1:
+; SSE3-LABEL: hsubpd1:
; SSE3-NOT: vhsubpd
; SSE3: hsubpd
-; AVX: hsubpd1:
+; AVX-LABEL: hsubpd1:
; AVX: vhsubpd
define <2 x double> @hsubpd1(<2 x double> %x, <2 x double> %y) {
%a = shufflevector <2 x double> %x, <2 x double> %y, <2 x i32> <i32 0, i32 2>
ret <2 x double> %r
}
-; SSE3: hsubpd2:
+; SSE3-LABEL: hsubpd2:
; SSE3-NOT: vhsubpd
; SSE3: hsubpd
-; AVX: hsubpd2:
+; AVX-LABEL: hsubpd2:
; AVX: vhsubpd
define <2 x double> @hsubpd2(<2 x double> %x) {
%a = shufflevector <2 x double> %x, <2 x double> undef, <2 x i32> <i32 0, i32 undef>
ret <2 x double> %r
}
-; SSE3: hsubps1:
+; SSE3-LABEL: hsubps1:
; SSE3-NOT: vhsubps
; SSE3: hsubps
-; AVX: hsubps1:
+; AVX-LABEL: hsubps1:
; AVX: vhsubps
define <4 x float> @hsubps1(<4 x float> %x, <4 x float> %y) {
%a = shufflevector <4 x float> %x, <4 x float> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x float> %r
}
-; SSE3: hsubps2:
+; SSE3-LABEL: hsubps2:
; SSE3-NOT: vhsubps
; SSE3: hsubps
-; AVX: hsubps2:
+; AVX-LABEL: hsubps2:
; AVX: vhsubps
define <4 x float> @hsubps2(<4 x float> %x) {
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
ret <4 x float> %r
}
-; SSE3: hsubps3:
+; SSE3-LABEL: hsubps3:
; SSE3-NOT: vhsubps
; SSE3: hsubps
-; AVX: hsubps3:
+; AVX-LABEL: hsubps3:
; AVX: vhsubps
define <4 x float> @hsubps3(<4 x float> %x) {
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
ret <4 x float> %r
}
-; SSE3: hsubps4:
+; SSE3-LABEL: hsubps4:
; SSE3-NOT: vhsubps
; SSE3: hsubps
-; AVX: hsubps4:
+; AVX-LABEL: hsubps4:
; AVX: vhsubps
define <4 x float> @hsubps4(<4 x float> %x) {
%a = shufflevector <4 x float> %x, <4 x float> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x float> %r
}
-; SSE3: vhaddps1:
+; SSE3-LABEL: vhaddps1:
; SSE3-NOT: vhaddps
; SSE3: haddps
; SSE3: haddps
-; AVX: vhaddps1:
+; AVX-LABEL: vhaddps1:
; AVX: vhaddps
define <8 x float> @vhaddps1(<8 x float> %x, <8 x float> %y) {
%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
ret <8 x float> %r
}
-; SSE3: vhaddps2:
+; SSE3-LABEL: vhaddps2:
; SSE3-NOT: vhaddps
; SSE3: haddps
; SSE3: haddps
-; AVX: vhaddps2:
+; AVX-LABEL: vhaddps2:
; AVX: vhaddps
define <8 x float> @vhaddps2(<8 x float> %x, <8 x float> %y) {
%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 1, i32 2, i32 9, i32 10, i32 5, i32 6, i32 13, i32 14>
ret <8 x float> %r
}
-; SSE3: vhaddps3:
+; SSE3-LABEL: vhaddps3:
; SSE3-NOT: vhaddps
; SSE3: haddps
; SSE3: haddps
-; AVX: vhaddps3:
+; AVX-LABEL: vhaddps3:
; AVX: vhaddps
define <8 x float> @vhaddps3(<8 x float> %x) {
%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
ret <8 x float> %r
}
-; SSE3: vhsubps1:
+; SSE3-LABEL: vhsubps1:
; SSE3-NOT: vhsubps
; SSE3: hsubps
; SSE3: hsubps
-; AVX: vhsubps1:
+; AVX-LABEL: vhsubps1:
; AVX: vhsubps
define <8 x float> @vhsubps1(<8 x float> %x, <8 x float> %y) {
%a = shufflevector <8 x float> %x, <8 x float> %y, <8 x i32> <i32 0, i32 2, i32 8, i32 10, i32 4, i32 6, i32 12, i32 14>
ret <8 x float> %r
}
-; SSE3: vhsubps3:
+; SSE3-LABEL: vhsubps3:
; SSE3-NOT: vhsubps
; SSE3: hsubps
; SSE3: hsubps
-; AVX: vhsubps3:
+; AVX-LABEL: vhsubps3:
; AVX: vhsubps
define <8 x float> @vhsubps3(<8 x float> %x) {
%a = shufflevector <8 x float> %x, <8 x float> undef, <8 x i32> <i32 undef, i32 2, i32 8, i32 10, i32 4, i32 6, i32 undef, i32 14>
ret <8 x float> %r
}
-; SSE3: vhaddpd1:
+; SSE3-LABEL: vhaddpd1:
; SSE3-NOT: vhaddpd
; SSE3: haddpd
; SSE3: haddpd
-; AVX: vhaddpd1:
+; AVX-LABEL: vhaddpd1:
; AVX: vhaddpd
define <4 x double> @vhaddpd1(<4 x double> %x, <4 x double> %y) {
%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
ret <4 x double> %r
}
-; SSE3: vhsubpd1:
+; SSE3-LABEL: vhsubpd1:
; SSE3-NOT: vhsubpd
; SSE3: hsubpd
; SSE3: hsubpd
-; AVX: vhsubpd1:
+; AVX-LABEL: vhsubpd1:
; AVX: vhsubpd
define <4 x double> @vhsubpd1(<4 x double> %x, <4 x double> %y) {
%a = shufflevector <4 x double> %x, <4 x double> %y, <4 x i32> <i32 0, i32 4, i32 2, i32 6>
define i32 @t() nounwind readonly {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movl _x, %eax
; CHECK: .comm _x,4
%0 = load i32* @x, align 4 ; <i32> [#uses=1]
define weak hidden void @t1() nounwind {
; LINUX: .hidden t1
-; LINUX: t1:
+; LINUX-LABEL: t1:
; DARWIN: .private_extern _t1
-; DARWIN: t1:
+; DARWIN-LABEL: t1:
-; WINDOWS: t1:
+; WINDOWS-LABEL: t1:
; WINDOWS-NOT: hidden
ret void
}
declare void @dummy_use(i32*, i32)
define {i32, i32} @test_basic(i32 %hp, i32 %p) {
- ; X32-Linux: test_basic:
+ ; X32-Linux-LABEL: test_basic:
; X32-Linux-NOT: calll inc_stack_0
- ; X64-Linux: test_basic:
+ ; X64-Linux-LABEL: test_basic:
; X64-Linux-NOT: callq inc_stack_0
%mem = alloca i32, i32 10
}
define cc 11 {i32, i32} @test_basic_hipecc(i32 %hp, i32 %p) {
- ; X32-Linux: test_basic_hipecc:
+ ; X32-Linux-LABEL: test_basic_hipecc:
; X32-Linux: leal -156(%esp), %ebx
; X32-Linux-NEXT: cmpl 76(%ebp), %ebx
; X32-Linux-NEXT: jb .LBB1_1
; X32-Linux: .LBB1_1:
; X32-Linux-NEXT: calll inc_stack_0
- ; X64-Linux: test_basic_hipecc:
+ ; X64-Linux-LABEL: test_basic_hipecc:
; X64-Linux: leaq -232(%rsp), %r14
; X64-Linux-NEXT: cmpq 144(%rbp), %r14
; X64-Linux-NEXT: jb .LBB1_1
}
define cc 11 {i32,i32,i32} @test_nocall_hipecc(i32 %hp,i32 %p,i32 %x,i32 %y) {
- ; X32-Linux: test_nocall_hipecc:
+ ; X32-Linux-LABEL: test_nocall_hipecc:
; X32-Linux-NOT: calll inc_stack_0
- ; X64-Linux: test_nocall_hipecc:
+ ; X64-Linux-LABEL: test_nocall_hipecc:
; X64-Linux-NOT: callq inc_stack_0
%1 = add i32 %x, %y
define zeroext i1 @t(i32 %c) nounwind ssp {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: xorl %eax, %eax
; CHECK: test
; CHECK: je
; trigger correctly.
define i128 @test1(i128 %x) {
- ; CHECK: test1:
+ ; CHECK-LABEL: test1:
; CHECK-NOT: call
%tmp = sdiv i128 %x, 73786976294838206464
ret i128 %tmp
}
define i128 @test2(i128 %x) {
- ; CHECK: test2:
+ ; CHECK-LABEL: test2:
; CHECK-NOT: call
%tmp = sdiv i128 %x, -73786976294838206464
ret i128 %tmp
}
define i128 @test3(i128 %x) {
- ; CHECK: test3:
+ ; CHECK-LABEL: test3:
; CHECK: call
%tmp = sdiv i128 %x, -73786976294838206467
ret i128 %tmp
define void @udiv8(i8* %quotient, i16 zeroext %a, i8 zeroext %b, i8 zeroext %c, i8* %remainder) nounwind ssp {
entry:
-; CHECK: udiv8:
+; CHECK-LABEL: udiv8:
; CHECK-NOT: movb %ah, (%r8)
%a_addr = alloca i16, align 2 ; <i16*> [#uses=2]
%b_addr = alloca i8, align 1 ; <i8*> [#uses=2]
%tmp = alloca %struct.s1, align 4
call void @f(%struct.s1* inreg sret %tmp, i32 inreg 41, i32 inreg 42, i32 43)
ret void
- ; DAG: g1:
+ ; DAG-LABEL: g1:
; DAG: subl $[[AMT:.*]], %esp
; DAG-NEXT: $43, (%esp)
; DAG-NEXT: leal 16(%esp), %eax
; DAG-NEXT: addl $[[AMT]], %esp
; DAG-NEXT: ret
- ; FAST: g1:
+ ; FAST-LABEL: g1:
; FAST: subl $[[AMT:.*]], %esp
; FAST-NEXT: leal 8(%esp), %eax
; FAST-NEXT: movl $41, %edx
define fastcc i32 @t() nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movzwl 0, %eax
; CHECK: orl $2, %eax
; CHECK: movw %ax, 0
define i32 @f(i32 %X) {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: jns
%tmp1 = add i32 %X, 1 ; <i32> [#uses=1]
%tmp = icmp slt i32 %tmp1, 0 ; <i1> [#uses=1]
; rdar://11355268
define i32 @g(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK-NOT: test
; CHECK: cmovs
%sub = sub nsw i32 %a, %b
; rdar://10734411
define i32 @h(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: h:
+; CHECK-LABEL: h:
; CHECK-NOT: cmp
; CHECK: cmov
; CHECK-NOT: movl
}
define i32 @i(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: i:
+; CHECK-LABEL: i:
; CHECK-NOT: cmp
; CHECK: cmov
; CHECK-NOT: movl
}
define i32 @j(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: j:
+; CHECK-LABEL: j:
; CHECK-NOT: cmp
; CHECK: cmov
; CHECK-NOT: movl
}
define i32 @k(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: k:
+; CHECK-LABEL: k:
; CHECK-NOT: cmp
; CHECK: cmov
; CHECK-NOT: movl
; redundant cmp instruction
define i32 @l(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: l:
+; CHECK-LABEL: l:
; CHECK-NOT: cmp
%cmp = icmp slt i32 %b, %a
%sub = sub nsw i32 %a, %b
}
define i32 @m(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: m:
+; CHECK-LABEL: m:
; CHECK-NOT: cmp
%cmp = icmp sgt i32 %a, %b
%sub = sub nsw i32 %a, %b
; a swapped sub.
define i32 @l2(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: l2:
+; CHECK-LABEL: l2:
; CHECK: cmp
%cmp = icmp eq i32 %b, %a
%sub = sub nsw i32 %a, %b
}
define i32 @l3(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: l3:
+; CHECK-LABEL: l3:
; CHECK: sub
; CHECK-NOT: cmp
; CHECK: jge
; When Movr0 is between sub and cmp, we need to move "Movr0" before sub.
define i32 @l4(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: l4:
+; CHECK-LABEL: l4:
; CHECK: xor
; CHECK: sub
; CHECK-NOT: cmp
; rdar://11540023
define i32 @n(i32 %x, i32 %y) nounwind {
entry:
-; CHECK: n:
+; CHECK-LABEL: n:
; CHECK-NOT: sub
; CHECK: cmp
%sub = sub nsw i32 %x, %y
br i1 undef, label %if.then44, label %if.end29
if.end29: ; preds = %sw.bb
-; CHECK: o:
+; CHECK-LABEL: o:
; CHECK: cmp
%1 = urem i16 %0, 10
%cmp25 = icmp eq i16 %1, 0
; rdar://11855129
define i32 @p(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: p:
+; CHECK-LABEL: p:
; CHECK-NOT: test
; CHECK: cmovs
%add = add nsw i32 %b, %a
; If we have sub a, b and cmp b, a and the result of cmp is used
; by sbb, we should not optimize cmp away.
define i32 @q(i32 %j.4, i32 %w, i32 %el) {
-; CHECK: q:
+; CHECK-LABEL: q:
; CHECK: cmp
; CHECK-NEXT: sbb
%tmp532 = add i32 %j.4, %w
; rdar://11873276
define i8* @r(i8* %base, i32* nocapture %offset, i32 %size) nounwind {
entry:
-; CHECK: r:
+; CHECK-LABEL: r:
; CHECK: sub
; CHECK-NOT: cmp
; CHECK: j
; Test optimizations of dec/inc.
define i32 @dec(i32 %a) nounwind {
entry:
-; CHECK: dec:
+; CHECK-LABEL: dec:
; CHECK: decl
; CHECK-NOT: test
; CHECK: cmovsl
define i32 @inc(i32 %a) nounwind {
entry:
-; CHECK: inc:
+; CHECK-LABEL: inc:
; CHECK: incl
; CHECK-NOT: test
; CHECK: cmovsl
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: addq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x01,0x37]
; CHECK: ret
define void @f1(i64* %a, i64 %b) nounwind {
ret void
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: subq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x29,0x37]
; CHECK: ret
define void @f2(i64* %a, i64 %b) nounwind {
ret void
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: andq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x21,0x37]
; CHECK: ret
define void @f3(i64* %a, i64 %b) nounwind {
ret void
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: orq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x09,0x37]
; CHECK: ret
define void @f4(i64* %a, i64 %b) nounwind {
ret void
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: xorq %{{.*}}, ({{.*}}){{.*}}encoding: [0xf0,0x48,0x31,0x37]
; CHECK: ret
define void @f5(i64* %a, i64 %b) nounwind {
; CodeGen should insert a branch into the middle of the loop in
; order to avoid a branch within the loop.
-; CHECK: simple:
+; CHECK-LABEL: simple:
; CHECK: jmp .LBB0_1
; CHECK-NEXT: align
; CHECK-NEXT: .LBB0_2:
; CodeGen should move block_a to the top of the loop so that it
; falls through into the loop, avoiding a branch within the loop.
-; CHECK: slightly_more_involved:
+; CHECK-LABEL: slightly_more_involved:
; CHECK: jmp .LBB1_1
; CHECK-NEXT: align
; CHECK-NEXT: .LBB1_4:
; fallthrough edges which should be preserved.
; "callq block_a_merge_func" is tail duped.
-; CHECK: yet_more_involved:
+; CHECK-LABEL: yet_more_involved:
; CHECK: jmp .LBB2_1
; CHECK-NEXT: align
; CHECK-NEXT: .LBB2_5:
; conveniently fit anywhere so that they are at least contiguous with the
; loop.
-; CHECK: cfg_islands:
+; CHECK-LABEL: cfg_islands:
; CHECK: jmp .LBB3_1
; CHECK-NEXT: align
; CHECK-NEXT: .LBB3_7:
; RUN: llc -mtriple=x86_64-darwin -mcpu=generic < %s | FileCheck %s
; RUN: llc -mtriple=x86_64-darwin -mcpu=atom < %s | FileCheck -check-prefix=ATOM %s
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: decq
; CHECK-NEXT: movl (%r9,%rax,4), %eax
; CHECK-NEXT: jne
-; ATOM: t:
+; ATOM-LABEL: t:
; ATOM: movl (%r9,%rax,4), %eax
; ATOM-NEXT: decq
; ATOM-NEXT: jne
; is equal to the stride.
; It must not fold (cmp (add iv, 1), 1) --> (cmp iv, 0).
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: %for.body
; CHECK: incl [[IV:%e..]]
; CHECK: cmpl $1, [[IV]]
; CHECK: jne
; CHECK: ret
-; ATOM: f:
+; ATOM-LABEL: f:
; ATOM: %for.body
; ATOM: incl [[IV:%e..]]
; ATOM: cmpl $1, [[IV]]
; Instruction selection should use the FLAGS value from the dec for
; the branch. Scheduling should push the adds upwards.
-; CHECK: full_me_0:
+; CHECK-LABEL: full_me_0:
; CHECK: movsd (%rsi), %xmm0
; CHECK: mulsd (%rdx), %xmm0
; CHECK: movsd %xmm0, (%rdi)
; would be better on x86-64, since the start value would be 0 instead of
; 2048.
-; CHECK: mostly_full_me_0:
+; CHECK-LABEL: mostly_full_me_0:
; CHECK: movsd -2048(%rsi), %xmm0
; CHECK: mulsd -2048(%rdx), %xmm0
; CHECK: movsd %xmm0, -2048(%rdi)
; A minor variation on mostly_full_me_0.
; Prefer to start the indvar at 0.
-; CHECK: mostly_full_me_1:
+; CHECK-LABEL: mostly_full_me_1:
; CHECK: movsd (%rsi), %xmm0
; CHECK: mulsd (%rdx), %xmm0
; CHECK: movsd %xmm0, (%rdi)
; A slightly less minor variation on mostly_full_me_0.
-; CHECK: mostly_full_me_2:
+; CHECK-LABEL: mostly_full_me_2:
; CHECK: movsd (%rsi), %xmm0
; CHECK: mulsd (%rdx), %xmm0
; CHECK: movsd %xmm0, (%rdi)
; cases away, but it's useful here to verify that LSR's register pressure
; heuristics are working as expected.
-; CHECK: count_me_0:
+; CHECK-LABEL: count_me_0:
; CHECK: movsd (%rsi,%rax,8), %xmm0
; CHECK: mulsd (%rdx,%rax,8), %xmm0
; CHECK: movsd %xmm0, (%rdi,%rax,8)
; would not reduce register pressure.
; (though it would reduce register pressure inside the loop...)
-; CHECK: count_me_1:
+; CHECK-LABEL: count_me_1:
; CHECK: movsd (%rsi,%rax,8), %xmm0
; CHECK: mulsd (%rdx,%rax,8), %xmm0
; CHECK: movsd %xmm0, (%rdi,%rax,8)
; Full strength reduction doesn't save any registers here because the
; loop tripcount is a constant.
-; CHECK: count_me_2:
+; CHECK-LABEL: count_me_2:
; CHECK: movl $10, %eax
; CHECK: align
; CHECK: BB6_1:
; This should be fully strength-reduced to reduce register pressure.
-; CHECK: full_me_1:
+; CHECK-LABEL: full_me_1:
; CHECK: align
; CHECK: BB7_1:
; CHECK: movsd (%rdi), %xmm0
; This is a variation on full_me_0 in which the 0,+,1 induction variable
; has a non-address use, pinning that value in a register.
-; CHECK: count_me_3:
+; CHECK-LABEL: count_me_3:
; CHECK: call
; CHECK: movsd (%r{{[^,]*}},%r{{[^,]*}},8), %xmm0
; CHECK: mulsd (%r{{[^,]*}},%r{{[^,]*}},8), %xmm0
; LSR should use only one indvar for the inner loop.
; rdar://7657764
-; CHECK: asd:
+; CHECK-LABEL: asd:
; CHECK: BB9_4:
; CHECK-NEXT: addl (%r{{[^,]*}},%rdi,4), %e
; CHECK-NEXT: incq %rdi
define i8 @t1(i8 %x) nounwind {
%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 false )
ret i8 %tmp
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: lzcntl
}
define i16 @t2(i16 %x) nounwind {
%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 false )
ret i16 %tmp
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: lzcntw
}
define i32 @t3(i32 %x) nounwind {
%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 false )
ret i32 %tmp
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: lzcntl
}
define i64 @t4(i64 %x) nounwind {
%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 false )
ret i64 %tmp
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: lzcntq
}
define i8 @t5(i8 %x) nounwind {
%tmp = tail call i8 @llvm.ctlz.i8( i8 %x, i1 true )
ret i8 %tmp
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: lzcntl
}
define i16 @t6(i16 %x) nounwind {
%tmp = tail call i16 @llvm.ctlz.i16( i16 %x, i1 true )
ret i16 %tmp
-; CHECK: t6:
+; CHECK-LABEL: t6:
; CHECK: lzcntw
}
define i32 @t7(i32 %x) nounwind {
%tmp = tail call i32 @llvm.ctlz.i32( i32 %x, i1 true )
ret i32 %tmp
-; CHECK: t7:
+; CHECK-LABEL: t7:
; CHECK: lzcntl
}
define i64 @t8(i64 %x) nounwind {
%tmp = tail call i64 @llvm.ctlz.i64( i64 %x, i1 true )
ret i64 %tmp
-; CHECK: t8:
+; CHECK-LABEL: t8:
; CHECK: lzcntq
}
; rdar://10640363
define i32 @t1(i32 %a, i32 %b) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: je [[LABEL:.*BB.*]]
%cmp1 = icmp eq i32 %b, 0
br i1 %cmp1, label %while.end, label %while.body
; rdar://10428165
define <8 x i16> @t2(<8 x i16> %T0, <8 x i16> %T1) nounwind readnone {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK-NOT: movdqa
%tmp8 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 undef, i32 undef, i32 7, i32 2, i32 8, i32 undef, i32 undef , i32 undef >
ret <8 x i16> %tmp8
define fastcc i8* @t(i32 %base) nounwind {
entry:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: leaq (%rax,%rax,4)
%0 = zext i32 %base to i64
%1 = getelementptr inbounds %struct.s2* null, i64 %0
declare void @printf(...) nounwind
define void @commute(i32 %test_case, i32 %scale) nounwind ssp {
-; CHECK: commute:
+; CHECK-LABEL: commute:
entry:
switch i32 %test_case, label %sw.bb307 [
i32 1, label %sw.bb
; rdar://10660865
define i32 @cross_mbb_phys_cse(i32 %a, i32 %b) nounwind ssp {
entry:
-; CHECK: cross_mbb_phys_cse:
+; CHECK-LABEL: cross_mbb_phys_cse:
; CHECK: cmpl
; CHECK: ja
%cmp = icmp ugt i32 %a, %b
b:
ret i32 0
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: t2_global@GOTPCREL(%rip)
; CHECK-NOT: t2_global@GOTPCREL(%rip)
}
%conv = sext i16 %ax to i32
ret i32 %conv
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: cwtl ## encoding: [0x98]
}
%conv = sext i32 %eax to i64
ret i64 %conv
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: cltq ## encoding: [0x48,0x98]
}
return: ; preds = %entry
ret void
-; CHECK: memcmp2:
+; CHECK-LABEL: memcmp2:
; CHECK: movw ([[A0:%rdi|%rcx]]), %ax
; CHECK: cmpw ([[A1:%rsi|%rdx]]), %ax
-; NOBUILTIN: memcmp2:
+; NOBUILTIN-LABEL: memcmp2:
; NOBUILTIN: callq
}
return: ; preds = %entry
ret void
-; CHECK: memcmp2a:
+; CHECK-LABEL: memcmp2a:
; CHECK: cmpw $28527, ([[A0]])
}
return: ; preds = %entry
ret void
-; CHECK: memcmp4:
+; CHECK-LABEL: memcmp4:
; CHECK: movl ([[A0]]), %eax
; CHECK: cmpl ([[A1]]), %eax
}
return: ; preds = %entry
ret void
-; CHECK: memcmp4a:
+; CHECK-LABEL: memcmp4a:
; CHECK: cmpl $1869573999, ([[A0]])
}
return: ; preds = %entry
ret void
-; CHECK: memcmp8:
+; CHECK-LABEL: memcmp8:
; CHECK: movq ([[A0]]), %rax
; CHECK: cmpq ([[A1]]), %rax
}
return: ; preds = %entry
ret void
-; CHECK: memcmp8a:
+; CHECK-LABEL: memcmp8a:
; CHECK: movabsq $8029759185026510694, %rax
; CHECK: cmpq %rax, ([[A0]])
}
define void @t1(i32 %argc, i8** %argv) nounwind {
entry:
-; SSE2-Darwin: t1:
+; SSE2-Darwin-LABEL: t1:
; SSE2-Darwin: movsd _.str+16, %xmm0
; SSE2-Darwin: movsd %xmm0, 16(%esp)
; SSE2-Darwin: movaps _.str, %xmm0
; SSE2-Darwin: movaps %xmm0
; SSE2-Darwin: movb $0, 24(%esp)
-; SSE2-Mingw32: t1:
+; SSE2-Mingw32-LABEL: t1:
; SSE2-Mingw32: movsd _.str+16, %xmm0
; SSE2-Mingw32: movsd %xmm0, 16(%esp)
; SSE2-Mingw32: movaps _.str, %xmm0
; SSE2-Mingw32: movups %xmm0
; SSE2-Mingw32: movb $0, 24(%esp)
-; SSE1: t1:
+; SSE1-LABEL: t1:
; SSE1: movaps _.str, %xmm0
; SSE1: movaps %xmm0
; SSE1: movb $0, 24(%esp)
; SSE1: movl $0, 20(%esp)
; SSE1: movl $0, 16(%esp)
-; NOSSE: t1:
+; NOSSE-LABEL: t1:
; NOSSE: movb $0
; NOSSE: movl $0
; NOSSE: movl $0
; NOSSE: movl $101
; NOSSE: movl $1734438249
-; X86-64: t1:
+; X86-64-LABEL: t1:
; X86-64: movaps _.str(%rip), %xmm0
; X86-64: movaps %xmm0
; X86-64: movb $0
define void @t2(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp {
entry:
-; SSE2-Darwin: t2:
+; SSE2-Darwin-LABEL: t2:
; SSE2-Darwin: movaps (%eax), %xmm0
; SSE2-Darwin: movaps %xmm0, (%eax)
-; SSE2-Mingw32: t2:
+; SSE2-Mingw32-LABEL: t2:
; SSE2-Mingw32: movaps (%eax), %xmm0
; SSE2-Mingw32: movaps %xmm0, (%eax)
-; SSE1: t2:
+; SSE1-LABEL: t2:
; SSE1: movaps (%eax), %xmm0
; SSE1: movaps %xmm0, (%eax)
-; NOSSE: t2:
+; NOSSE-LABEL: t2:
; NOSSE: movl
; NOSSE: movl
; NOSSE: movl
; NOSSE: movl
; NOSSE: movl
-; X86-64: t2:
+; X86-64-LABEL: t2:
; X86-64: movaps (%rsi), %xmm0
; X86-64: movaps %xmm0, (%rdi)
%tmp2 = bitcast %struct.s0* %a to i8* ; <i8*> [#uses=1]
define void @t3(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp {
entry:
-; SSE2-Darwin: t3:
+; SSE2-Darwin-LABEL: t3:
; SSE2-Darwin: movsd (%eax), %xmm0
; SSE2-Darwin: movsd 8(%eax), %xmm1
; SSE2-Darwin: movsd %xmm1, 8(%eax)
; SSE2-Darwin: movsd %xmm0, (%eax)
-; SSE2-Mingw32: t3:
+; SSE2-Mingw32-LABEL: t3:
; SSE2-Mingw32: movsd (%eax), %xmm0
; SSE2-Mingw32: movsd 8(%eax), %xmm1
; SSE2-Mingw32: movsd %xmm1, 8(%eax)
; SSE2-Mingw32: movsd %xmm0, (%eax)
-; SSE1: t3:
+; SSE1-LABEL: t3:
; SSE1: movl
; SSE1: movl
; SSE1: movl
; SSE1: movl
; SSE1: movl
-; NOSSE: t3:
+; NOSSE-LABEL: t3:
; NOSSE: movl
; NOSSE: movl
; NOSSE: movl
; NOSSE: movl
; NOSSE: movl
-; X86-64: t3:
+; X86-64-LABEL: t3:
; X86-64: movq (%rsi), %rax
; X86-64: movq 8(%rsi), %rcx
; X86-64: movq %rcx, 8(%rdi)
define void @t4() nounwind {
entry:
-; SSE2-Darwin: t4:
+; SSE2-Darwin-LABEL: t4:
; SSE2-Darwin: movw $120
; SSE2-Darwin: movl $2021161080
; SSE2-Darwin: movl $2021161080
; SSE2-Darwin: movl $2021161080
; SSE2-Darwin: movl $2021161080
-; SSE2-Mingw32: t4:
+; SSE2-Mingw32-LABEL: t4:
; SSE2-Mingw32: movw $120
; SSE2-Mingw32: movl $2021161080
; SSE2-Mingw32: movl $2021161080
; SSE2-Mingw32: movl $2021161080
; SSE2-Mingw32: movl $2021161080
-; SSE1: t4:
+; SSE1-LABEL: t4:
; SSE1: movw $120
; SSE1: movl $2021161080
; SSE1: movl $2021161080
; SSE1: movl $2021161080
; SSE1: movl $2021161080
-; NOSSE: t4:
+; NOSSE-LABEL: t4:
; NOSSE: movw $120
; NOSSE: movl $2021161080
; NOSSE: movl $2021161080
; NOSSE: movl $2021161080
; NOSSE: movl $2021161080
-; X86-64: t4:
+; X86-64-LABEL: t4:
; X86-64: movabsq $8680820740569200760, %rax
; X86-64: movq %rax
; X86-64: movq %rax
define fastcc void @t1() nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: calll _memset
call void @llvm.memset.p0i8.i32(i8* null, i8 0, i32 188, i32 1, i1 false)
unreachable
define fastcc void @t2(i8 signext %c) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: calll _memset
call void @llvm.memset.p0i8.i32(i8* undef, i8 %c, i32 76, i32 1, i1 false)
unreachable
entry:
tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 8, i32 1, i1 false)
ret void
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: imull $16843009
}
entry:
tail call void @llvm.memset.p0i8.i32(i8* %s, i8 %a, i32 15, i32 1, i1 false)
ret void
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: imull $16843009
; CHECK-NOT: imul
; CHECK: ret
store x86_mmx %v1, x86_mmx* @u1, align 8
ret void
-; X86-32: t1:
+; X86-32-LABEL: t1:
; X86-32: movq %mm0
-; X86-64: t1:
+; X86-64-LABEL: t1:
; X86-64: movdq2q %xmm0
; X86-64: movq %mm0
}
store x86_mmx %tmp, x86_mmx* @u2, align 8
ret void
-; X86-32: t2:
+; X86-32-LABEL: t2:
; X86-32: movl 4(%esp)
; X86-32: movl 8(%esp)
-; X86-64: t2:
+; X86-64-LABEL: t2:
; X86-64: movq %rdi
}
%retval1112 = bitcast x86_mmx %tmp6 to i64
ret i64 %retval1112
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: psllq $32
}
%retval1112 = bitcast x86_mmx %tmp7 to i64
ret i64 %retval1112
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: psrad
}
%retval1314 = bitcast x86_mmx %tmp8 to i64
ret i64 %retval1314
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: psrlw
}
%3 = bitcast <4 x i32> %2 to <2 x i64>
ret <2 x i64> %3
-; X32: pmovsxwd_1:
+; X32-LABEL: pmovsxwd_1:
; X32: movl 4(%esp), %eax
; X32: pmovsxwd %gs:(%eax), %xmm0
; X32: ret
-; X64: pmovsxwd_1:
+; X64-LABEL: pmovsxwd_1:
; X64: pmovsxwd %gs:([[A0]]), %xmm0
; X64: ret
}
entry:
; FIXME: This should also use movmskps; we don't form the FGETSIGN node
; in this case, though.
-; CHECK: float_call_signbit:
+; CHECK-LABEL: float_call_signbit:
; CHECK: movd %xmm0, %rdi
; FIXME
%t0 = bitcast double %n to i64
define i32 @t1(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: movmskps
; CHECK-NOT: movslq
%0 = tail call i32 @llvm.x86.sse.movmsk.ps(<4 x float> %x) nounwind
define i32 @t2(<4 x float> %x, i32* nocapture %indexTable) nounwind uwtable readonly ssp {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: movmskpd
; CHECK-NOT: movslq
%0 = bitcast <4 x float> %x to <2 x double>
entry:
call void asm sideeffect inteldialect "call $0", "r,~{dirflag},~{fpsr},~{flags}"(void ()* @t19_helper) nounwind
ret void
-; CHECK: t19:
+; CHECK-LABEL: t19:
; CHECK: movl %esp, %ebp
; CHECK: movl ${{_?}}t19_helper, %eax
; CHECK: {{## InlineAsm Start|#APP}}
call void asm sideeffect inteldialect "mov dword ptr $0, edi", "=*m,~{dirflag},~{fpsr},~{flags}"(i32** %res) nounwind
%0 = load i32** %res, align 4
ret i32* %0
-; CHECK: t30:
+; CHECK-LABEL: t30:
; CHECK: movl %esp, %ebp
; CHECK: {{## InlineAsm Start|#APP}}
; CHECK: .intel_syntax
store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
ret void
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: orb $1
; CHECK-NEXT: ret
}
store i32 %1, i32* bitcast (i16* getelementptr (%struct.bf* @bfi, i32 0, i32 1) to i32*), align 8
ret void
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: orl $16842752
; CHECK-NEXT: ret
}
; PR12545
define void @f(i32 %x, i32 %y) nounwind uwtable ssp {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK-NOT: neg
; CHECK: add
%sub = sub i32 0, %y
declare void @lazy() nonlazybind
declare void @not()
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: callq _not
; CHECK: callq *_lazy@GOTPCREL(%rip)
define void @foo() nounwind {
ret void
}
-; CHECK: tail_call_regular:
+; CHECK-LABEL: tail_call_regular:
; CHECK: jmp _not
define void @tail_call_regular() nounwind {
tail call void @not()
ret void
}
-; CHECK: tail_call_eager:
+; CHECK-LABEL: tail_call_eager:
; CHECK: jmpq *_lazy@GOTPCREL(%rip)
define void @tail_call_eager() nounwind {
tail call void @lazy()
; LSR's OptimizeMax should eliminate the select (max).
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK-NOT: cmov
; CHECK: jle
; OptimizeMax should handle this case.
; PR7454
-; CHECK: _Z18GenerateStatusPagei:
+; CHECK-LABEL: _Z18GenerateStatusPagei:
; CHECK: jle
; CHECK-NOT: cmov
define void @t1(<2 x i64> %a, <2 x i64> %b) nounwind ssp {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; palignr $3, %xmm1, %xmm0
%0 = tail call <2 x i64> @llvm.x86.ssse3.palign.r.128(<2 x i64> %a, <2 x i64> %b, i8 24) nounwind readnone
store <2 x i64> %0, <2 x i64>* bitcast ([4 x i32]* @c to <2 x i64>*), align 16
define void @t2() nounwind ssp {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; palignr $4, _b, %xmm0
%0 = load <2 x i64>* bitcast ([4 x i32]* @b to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
%1 = load <2 x i64>* bitcast ([4 x i32]* @a to <2 x i64>*), align 16 ; <<2 x i64>> [#uses=1]
ret { i8*, i64, i64* } %2
}
-; CHECK: copy_3:
+; CHECK-LABEL: copy_3:
; CHECK-NOT: (%rdi)
; CHECK: ret
; LLVM should omit the testl and use the flags result from the orl.
-; CHECK: or:
+; CHECK-LABEL: or:
define void @or(float* %A, i32 %IA, i32 %N) nounwind {
entry:
%0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
return: ; preds = %entry
ret void
}
-; CHECK: xor:
+; CHECK-LABEL: xor:
define void @xor(float* %A, i32 %IA, i32 %N) nounwind {
entry:
%0 = ptrtoint float* %A to i32 ; <i32> [#uses=1]
return: ; preds = %entry
ret void
}
-; CHECK: and:
+; CHECK-LABEL: and:
define void @and(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
entry:
store i8 0, i8* %p
declare void @foo(i32)
declare void @foo64(i64)
-; CHECK: neg:
+; CHECK-LABEL: neg:
; CHECK: negl %edi
; CHECK-NEXT: je
; CHECK: jmp foo
ret void
}
-; CHECK: sar:
+; CHECK-LABEL: sar:
; CHECK: sarl %edi
; CHECK-NEXT: je
; CHECK: jmp foo
ret void
}
-; CHECK: shr:
+; CHECK-LABEL: shr:
; CHECK: shrl %edi
; CHECK-NEXT: je
; CHECK: jmp foo
ret void
}
-; CHECK: shri:
+; CHECK-LABEL: shri:
; CHECK: shrl $3, %edi
; CHECK-NEXT: je
; CHECK: jmp foo
ret void
}
-; CHECK: shl:
+; CHECK-LABEL: shl:
; CHECK: addl %edi, %edi
; CHECK-NEXT: je
; CHECK: jmp foo
ret void
}
-; CHECK: shli:
+; CHECK-LABEL: shli:
; CHECK: shll $4, %edi
; CHECK-NEXT: je
; CHECK: jmp foo
ret void
}
-; CHECK: adc:
+; CHECK-LABEL: adc:
; CHECK: movabsq $-9223372036854775808, %rax
; CHECK-NEXT: addq %rdi, %rax
; CHECK-NEXT: adcq $0, %rsi
ret i1 %cmp
}
-; CHECK: sbb:
+; CHECK-LABEL: sbb:
; CHECK: cmpq %rdx, %rdi
; CHECK-NEXT: sbbq %rcx, %rsi
; CHECK-NEXT: setns %al
ret i1 %cmp
}
-; CHECK: andn:
+; CHECK-LABEL: andn:
; CHECK: andnl %esi, %edi, %edi
; CHECK-NEXT: je
; CHECK: jmp foo
ret void
}
-; CHECK: bextr:
+; CHECK-LABEL: bextr:
; CHECK: bextrl %esi, %edi, %edi
; CHECK-NEXT: je
; CHECK: jmp foo
ret void
}
-; CHECK: popcnt:
+; CHECK-LABEL: popcnt:
; CHECK: popcntl
; CHECK-NEXT: je
; CHECK: jmp foo
; RUN: llc < %s -march=x86-64 -mattr=+ssse3,-avx | FileCheck %s -check-prefix=SSSE3
; RUN: llc < %s -march=x86-64 -mattr=-ssse3,+avx | FileCheck %s -check-prefix=AVX
-; SSSE3: phaddw1:
+; SSSE3-LABEL: phaddw1:
; SSSE3-NOT: vphaddw
; SSSE3: phaddw
-; AVX: phaddw1:
+; AVX-LABEL: phaddw1:
; AVX: vphaddw
define <8 x i16> @phaddw1(<8 x i16> %x, <8 x i16> %y) {
%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
ret <8 x i16> %r
}
-; SSSE3: phaddw2:
+; SSSE3-LABEL: phaddw2:
; SSSE3-NOT: vphaddw
; SSSE3: phaddw
-; AVX: phaddw2:
+; AVX-LABEL: phaddw2:
; AVX: vphaddw
define <8 x i16> @phaddw2(<8 x i16> %x, <8 x i16> %y) {
%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 1, i32 2, i32 5, i32 6, i32 9, i32 10, i32 13, i32 14>
ret <8 x i16> %r
}
-; SSSE3: phaddd1:
+; SSSE3-LABEL: phaddd1:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
-; AVX: phaddd1:
+; AVX-LABEL: phaddd1:
; AVX: vphaddd
define <4 x i32> @phaddd1(<4 x i32> %x, <4 x i32> %y) {
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i32> %r
}
-; SSSE3: phaddd2:
+; SSSE3-LABEL: phaddd2:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
-; AVX: phaddd2:
+; AVX-LABEL: phaddd2:
; AVX: vphaddd
define <4 x i32> @phaddd2(<4 x i32> %x, <4 x i32> %y) {
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 2, i32 5, i32 6>
ret <4 x i32> %r
}
-; SSSE3: phaddd3:
+; SSSE3-LABEL: phaddd3:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
-; AVX: phaddd3:
+; AVX-LABEL: phaddd3:
; AVX: vphaddd
define <4 x i32> @phaddd3(<4 x i32> %x) {
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
ret <4 x i32> %r
}
-; SSSE3: phaddd4:
+; SSSE3-LABEL: phaddd4:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
-; AVX: phaddd4:
+; AVX-LABEL: phaddd4:
; AVX: vphaddd
define <4 x i32> @phaddd4(<4 x i32> %x) {
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
ret <4 x i32> %r
}
-; SSSE3: phaddd5:
+; SSSE3-LABEL: phaddd5:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
-; AVX: phaddd5:
+; AVX-LABEL: phaddd5:
; AVX: vphaddd
define <4 x i32> @phaddd5(<4 x i32> %x) {
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 3, i32 undef, i32 undef>
ret <4 x i32> %r
}
-; SSSE3: phaddd6:
+; SSSE3-LABEL: phaddd6:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
-; AVX: phaddd6:
+; AVX-LABEL: phaddd6:
; AVX: vphaddd
define <4 x i32> @phaddd6(<4 x i32> %x) {
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
ret <4 x i32> %r
}
-; SSSE3: phaddd7:
+; SSSE3-LABEL: phaddd7:
; SSSE3-NOT: vphaddd
; SSSE3: phaddd
-; AVX: phaddd7:
+; AVX-LABEL: phaddd7:
; AVX: vphaddd
define <4 x i32> @phaddd7(<4 x i32> %x) {
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 3, i32 undef, i32 undef>
ret <4 x i32> %r
}
-; SSSE3: phsubw1:
+; SSSE3-LABEL: phsubw1:
; SSSE3-NOT: vphsubw
; SSSE3: phsubw
-; AVX: phsubw1:
+; AVX-LABEL: phsubw1:
; AVX: vphsubw
define <8 x i16> @phsubw1(<8 x i16> %x, <8 x i16> %y) {
%a = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
ret <8 x i16> %r
}
-; SSSE3: phsubd1:
+; SSSE3-LABEL: phsubd1:
; SSSE3-NOT: vphsubd
; SSSE3: phsubd
-; AVX: phsubd1:
+; AVX-LABEL: phsubd1:
; AVX: vphsubd
define <4 x i32> @phsubd1(<4 x i32> %x, <4 x i32> %y) {
%a = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
ret <4 x i32> %r
}
-; SSSE3: phsubd2:
+; SSSE3-LABEL: phsubd2:
; SSSE3-NOT: vphsubd
; SSSE3: phsubd
-; AVX: phsubd2:
+; AVX-LABEL: phsubd2:
; AVX: vphsubd
define <4 x i32> @phsubd2(<4 x i32> %x) {
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 undef, i32 2, i32 4, i32 6>
ret <4 x i32> %r
}
-; SSSE3: phsubd3:
+; SSSE3-LABEL: phsubd3:
; SSSE3-NOT: vphsubd
; SSSE3: phsubd
-; AVX: phsubd3:
+; AVX-LABEL: phsubd3:
; AVX: vphsubd
define <4 x i32> @phsubd3(<4 x i32> %x) {
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 2, i32 undef, i32 undef>
ret <4 x i32> %r
}
-; SSSE3: phsubd4:
+; SSSE3-LABEL: phsubd4:
; SSSE3-NOT: vphsubd
; SSSE3: phsubd
-; AVX: phsubd4:
+; AVX-LABEL: phsubd4:
; AVX: vphsubd
define <4 x i32> @phsubd4(<4 x i32> %x) {
%a = shufflevector <4 x i32> %x, <4 x i32> undef, <4 x i32> <i32 0, i32 undef, i32 undef, i32 undef>
; 336L %vreg15<def> = SAR32rCL %vreg15, %EFLAGS<imp-def,dead>, %CL<imp-use,kill>; GR32:%vreg15
define void @foo(i32* nocapture %quadrant, i32* nocapture %ptr, i32 %bbSize, i32 %bbStart, i32 %shifts) nounwind ssp {
-; CHECK: foo:
+; CHECK-LABEL: foo:
entry:
%j.03 = add i32 %bbSize, -1 ; <i32> [#uses=2]
%0 = icmp sgt i32 %j.03, -1 ; <i1> [#uses=1]
define i8 @cnt8(i8 %x) nounwind readnone {
%cnt = tail call i8 @llvm.ctpop.i8(i8 %x)
ret i8 %cnt
-; CHECK: cnt8:
+; CHECK-LABEL: cnt8:
; CHECK: popcntw
; CHECK: ret
}
define i16 @cnt16(i16 %x) nounwind readnone {
%cnt = tail call i16 @llvm.ctpop.i16(i16 %x)
ret i16 %cnt
-; CHECK: cnt16:
+; CHECK-LABEL: cnt16:
; CHECK: popcntw
; CHECK: ret
}
define i32 @cnt32(i32 %x) nounwind readnone {
%cnt = tail call i32 @llvm.ctpop.i32(i32 %x)
ret i32 %cnt
-; CHECK: cnt32:
+; CHECK-LABEL: cnt32:
; CHECK: popcntl
; CHECK: ret
}
define i64 @cnt64(i64 %x) nounwind readnone {
%cnt = tail call i64 @llvm.ctpop.i64(i64 %x)
ret i64 %cnt
-; CHECK: cnt64:
+; CHECK-LABEL: cnt64:
; CHECK: popcntq
; CHECK: ret
}
@.str24 = external constant [4 x i8], align 1 ; <[4 x i8]*> [#uses=1]
define i32 @t1(i32 %c, i8** nocapture %v) nounwind ssp {
-; X86-32: t1:
+; X86-32-LABEL: t1:
entry:
br i1 undef, label %bb, label %bb3
@map_4_to_16 = external constant [16 x i16], align 32 ; <[16 x i16]*> [#uses=2]
define void @t2(i8* nocapture %bufp, i8* nocapture %data, i32 %dsize) nounwind ssp {
-; X86-64: t2:
+; X86-64-LABEL: t2:
entry:
br i1 undef, label %return, label %bb.nph
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
define zeroext i1 @f1(i8* %x) {
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: movb (%rdi), %al
; CHECK-NEXT: ret
}
define zeroext i1 @f2(i8* %x) {
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: movb (%rdi), %al
; CHECK-NEXT: ret
; check that we don't build a "trunc" from i1 to i1, which would assert.
define zeroext i1 @f3(i1 %x) {
-; CHECK: f3:
+; CHECK-LABEL: f3:
entry:
%tobool = icmp ne i1 %x, 0
; check that we don't build a trunc when other bits are needed
define zeroext i1 @f4(i32 %x) {
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: and
entry:
; RUN: llc < %s -mtriple=x86_64-pc-linux | FileCheck %s
-; CHECK: pr13209:
+; CHECK-LABEL: pr13209:
; CHECK-NOT: mov
; CHECK: .size pr13209
; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK: pushl %esi
; CHECK-NEXT: movl $-12, %eax
; CHECK-NEXT: movl $-1, %edx
@x = weak global i32 0 ; <i32*> [#uses=8]
define void @loop_2() nounwind {
-; CHECK: loop_2:
+; CHECK-LABEL: loop_2:
; CHECK-NOT: ret
; CHECK: addl $3, (%{{.*}})
; CHECK-NEXT: addl $3, (%{{.*}})
@foo = global i8 127
define i32 @main() nounwind {
-; CHECK: main:
+; CHECK-LABEL: main:
; CHECK-NOT: ret
; CHECK: sar{{.}} $5
; CHECK: ret
%1 = load i32* @baz, align 4
ret i32 %1
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: callq .Lfoo
; CHECK: movl .Lbaz(%rip)
}
define signext i16 @foo(i16 signext %x) nounwind {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK-NOT: movzwl
; CHECK: movswl 4(%esp), %eax
; CHECK: xorl $21998, %eax
define signext i16 @bar(i16 signext %x) nounwind {
entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK-NOT: movzwl
; CHECK: movswl 4(%esp), %eax
; CHECK: xorl $-10770, %eax
store i16 %randval, i16* %random_val
%isvalid = extractvalue {i16, i32} %call, 1
ret i32 %isvalid
-; CHECK: _rdrand16_step:
+; CHECK-LABEL: _rdrand16_step:
; CHECK: rdrandw %ax
; CHECK: movw %ax, (%r[[A0:di|cx]])
; CHECK: movzwl %ax, %ecx
store i32 %randval, i32* %random_val
%isvalid = extractvalue {i32, i32} %call, 1
ret i32 %isvalid
-; CHECK: _rdrand32_step:
+; CHECK-LABEL: _rdrand32_step:
; CHECK: rdrandl %e[[T0:[a-z]+]]
; CHECK: movl %e[[T0]], (%r[[A0]])
; CHECK: movl $1, %eax
store i64 %randval, i64* %random_val
%isvalid = extractvalue {i64, i32} %call, 1
ret i32 %isvalid
-; CHECK: _rdrand64_step:
+; CHECK-LABEL: _rdrand64_step:
; CHECK: rdrandq %r[[T1:[a-z]+]]
; CHECK: movq %r[[T1]], (%r[[A0]])
; CHECK: movl $1, %eax
%v2 = extractvalue { i32, i32 } %rand2, 0
%add = add i32 %v2, %v1
ret i32 %add
-; CHECK: CSE:
+; CHECK-LABEL: CSE:
; CHECK: rdrandl
; CHECK: rdrandl
}
while.end: ; preds = %while.body, %entry
ret void
-; CHECK: loop:
+; CHECK-LABEL: loop:
; CHECK-NOT: rdrandl
; CHECK: This Inner Loop Header: Depth=1
; CHECK: rdrandl
store i16 %randval, i16* %random_val
%isvalid = extractvalue {i16, i32} %call, 1
ret i32 %isvalid
-; CHECK: _rdseed16_step:
+; CHECK-LABEL: _rdseed16_step:
; CHECK: rdseedw %ax
; CHECK: movw %ax, (%r[[A0:di|cx]])
; CHECK: movzwl %ax, %ecx
store i32 %randval, i32* %random_val
%isvalid = extractvalue {i32, i32} %call, 1
ret i32 %isvalid
-; CHECK: _rdseed32_step:
+; CHECK-LABEL: _rdseed32_step:
; CHECK: rdseedl %e[[T0:[a-z]+]]
; CHECK: movl %e[[T0]], (%r[[A0]])
; CHECK: movl $1, %eax
store i64 %randval, i64* %random_val
%isvalid = extractvalue {i64, i32} %call, 1
ret i32 %isvalid
-; CHECK: _rdseed64_step:
+; CHECK-LABEL: _rdseed64_step:
; CHECK: rdseedq %r[[T1:[a-z]+]]
; CHECK: movq %r[[T1]], (%r[[A0]])
; CHECK: movl $1, %eax
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
; First without noredzone.
-; CHECK: f0:
+; CHECK-LABEL: f0:
; CHECK: -4(%rsp)
; CHECK: -4(%rsp)
; CHECK: ret
}
; Then with noredzone.
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: subq $4, %rsp
; CHECK: (%rsp)
; CHECK: (%rsp)
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux | FileCheck %s
-; CHECK: f0:
+; CHECK-LABEL: f0:
; CHECK: subq
; CHECK: addq
declare void @foo(i64 %p)
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: xorl %e[[A0:di|cx]], %e
; CHECK: xorl %e[[A0]], %e[[A0]]
define void @bar() nounwind {
ret void
}
-; CHECK: bat:
+; CHECK-LABEL: bat:
; CHECK: movq $-1, %r[[A0]]
; CHECK: movq $-1, %r[[A0]]
define void @bat() nounwind {
ret void
}
-; CHECK: bau:
+; CHECK-LABEL: bau:
; CHECK: movl $1, %e[[A0]]
; CHECK: movl $1, %e[[A0]]
define void @bau() nounwind {
%call = call <1 x i64> @return_v1di() ; <<1 x i64>> [#uses=0]
store <1 x i64> %call, <1 x i64>* @g_v1di
ret void
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: callq
; CHECK-NEXT: movq _g_v1di
; CHECK-NEXT: movq %rax,
define <1 x i64> @t2() nounwind {
ret <1 x i64> <i64 1>
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: movl $1
; CHECK-NEXT: ret
}
define <2 x i32> @t3() nounwind {
ret <2 x i32> <i32 1, i32 0>
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: movl $1
; CHECK: movd {{.*}}, %xmm0
}
define double @t4() nounwind {
ret double bitcast (<2 x i32> <i32 1, i32 0> to double)
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: movl $1
; CHECK: movd {{.*}}, %xmm0
}
define i16 @foo(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: rolw %cl
%0 = shl i16 %x, %z
%1 = sub i16 16, %z
define i16 @bar(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: shldw %cl
%0 = shl i16 %y, %z
%1 = sub i16 16, %z
define i16 @un(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
-; CHECK: un:
+; CHECK-LABEL: un:
; CHECK: rorw %cl
%0 = lshr i16 %x, %z
%1 = sub i16 16, %z
define i16 @bu(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
-; CHECK: bu:
+; CHECK-LABEL: bu:
; CHECK: shrdw
%0 = lshr i16 %y, %z
%1 = sub i16 16, %z
define i16 @xfoo(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
-; CHECK: xfoo:
+; CHECK-LABEL: xfoo:
; CHECK: rolw $5
%0 = lshr i16 %x, 11
%1 = shl i16 %x, 5
define i16 @xbar(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
-; CHECK: xbar:
+; CHECK-LABEL: xbar:
; CHECK: shldw $5
%0 = shl i16 %y, 5
%1 = lshr i16 %x, 11
define i16 @xun(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
-; CHECK: xun:
+; CHECK-LABEL: xun:
; CHECK: rolw $11
%0 = lshr i16 %x, 5
%1 = shl i16 %x, 11
define i16 @xbu(i16 %x, i16 %y, i16 %z) nounwind readnone {
entry:
-; CHECK: xbu:
+; CHECK-LABEL: xbu:
; CHECK: shldw $11
%0 = lshr i16 %y, 5
%1 = shl i16 %x, 11
define i32 @foo(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: roll %cl
%0 = shl i32 %x, %z
%1 = sub i32 32, %z
define i32 @bar(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: shldl %cl
%0 = shl i32 %y, %z
%1 = sub i32 32, %z
define i32 @un(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
-; CHECK: un:
+; CHECK-LABEL: un:
; CHECK: rorl %cl
%0 = lshr i32 %x, %z
%1 = sub i32 32, %z
define i32 @bu(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
-; CHECK: bu:
+; CHECK-LABEL: bu:
; CHECK: shrdl %cl
%0 = lshr i32 %y, %z
%1 = sub i32 32, %z
define i32 @xfoo(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
-; CHECK: xfoo:
+; CHECK-LABEL: xfoo:
; CHECK: roll $7
-; BMI2: xfoo:
+; BMI2-LABEL: xfoo:
; BMI2: rorxl $25
%0 = lshr i32 %x, 25
%1 = shl i32 %x, 7
define i32 @xfoop(i32* %p) nounwind readnone {
entry:
-; BMI2: xfoop:
+; BMI2-LABEL: xfoop:
; BMI2: rorxl $25, ({{.+}}), %{{.+}}
%x = load i32* %p
%a = lshr i32 %x, 25
define i32 @xbar(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
-; CHECK: xbar:
+; CHECK-LABEL: xbar:
; CHECK: shldl $7
%0 = shl i32 %y, 7
%1 = lshr i32 %x, 25
define i32 @xun(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
-; CHECK: xun:
+; CHECK-LABEL: xun:
; CHECK: roll $25
-; BMI2: xun:
+; BMI2-LABEL: xun:
; BMI2: rorxl $7
%0 = lshr i32 %x, 7
%1 = shl i32 %x, 25
define i32 @xunp(i32* %p) nounwind readnone {
entry:
-; BMI2: xunp:
+; BMI2-LABEL: xunp:
; BMI2: rorxl $7, ({{.+}}), %{{.+}}
%x = load i32* %p
%a = lshr i32 %x, 7
define i32 @xbu(i32 %x, i32 %y, i32 %z) nounwind readnone {
entry:
-; CHECK: xbu:
+; CHECK-LABEL: xbu:
; CHECK: shldl
%0 = lshr i32 %y, 7
%1 = shl i32 %x, 25
define i64 @xfoo(i64 %x, i64 %y, i64 %z) nounwind readnone {
entry:
-; BMI2: xfoo:
+; BMI2-LABEL: xfoo:
; BMI2: rorxq $57
%0 = lshr i64 %x, 57
%1 = shl i64 %x, 7
define i64 @xfoop(i64* %p) nounwind readnone {
entry:
-; BMI2: xfoop:
+; BMI2-LABEL: xfoop:
; BMI2: rorxq $57, ({{.+}}), %{{.+}}
%x = load i64* %p
%a = lshr i64 %x, 57
define i64 @xun(i64 %x, i64 %y, i64 %z) nounwind readnone {
entry:
-; BMI2: xun:
+; BMI2-LABEL: xun:
; BMI2: rorxq $7
%0 = lshr i64 %x, 7
%1 = shl i64 %x, 57
define i64 @xunp(i64* %p) nounwind readnone {
entry:
-; BMI2: xunp:
+; BMI2-LABEL: xunp:
; BMI2: rorxq $7, ({{.+}}), %{{.+}}
%x = load i64* %p
%a = lshr i64 %x, 7
%call = tail call float @floorf(float %x) nounwind readnone
ret float %call
-; CHECK-SSE: test1:
+; CHECK-SSE-LABEL: test1:
; CHECK-SSE: roundss $1
-; CHECK-AVX: test1:
+; CHECK-AVX-LABEL: test1:
; CHECK-AVX: vroundss $1
}
%call = tail call double @floor(double %x) nounwind readnone
ret double %call
-; CHECK-SSE: test2:
+; CHECK-SSE-LABEL: test2:
; CHECK-SSE: roundsd $1
-; CHECK-AVX: test2:
+; CHECK-AVX-LABEL: test2:
; CHECK-AVX: vroundsd $1
}
%call = tail call float @nearbyintf(float %x) nounwind readnone
ret float %call
-; CHECK-SSE: test3:
+; CHECK-SSE-LABEL: test3:
; CHECK-SSE: roundss $12
-; CHECK-AVX: test3:
+; CHECK-AVX-LABEL: test3:
; CHECK-AVX: vroundss $12
}
%call = tail call double @nearbyint(double %x) nounwind readnone
ret double %call
-; CHECK-SSE: test4:
+; CHECK-SSE-LABEL: test4:
; CHECK-SSE: roundsd $12
-; CHECK-AVX: test4:
+; CHECK-AVX-LABEL: test4:
; CHECK-AVX: vroundsd $12
}
%call = tail call float @ceilf(float %x) nounwind readnone
ret float %call
-; CHECK-SSE: test5:
+; CHECK-SSE-LABEL: test5:
; CHECK-SSE: roundss $2
-; CHECK-AVX: test5:
+; CHECK-AVX-LABEL: test5:
; CHECK-AVX: vroundss $2
}
%call = tail call double @ceil(double %x) nounwind readnone
ret double %call
-; CHECK-SSE: test6:
+; CHECK-SSE-LABEL: test6:
; CHECK-SSE: roundsd $2
-; CHECK-AVX: test6:
+; CHECK-AVX-LABEL: test6:
; CHECK-AVX: vroundsd $2
}
%call = tail call float @rintf(float %x) nounwind readnone
ret float %call
-; CHECK-SSE: test7:
+; CHECK-SSE-LABEL: test7:
; CHECK-SSE: roundss $4
-; CHECK-AVX: test7:
+; CHECK-AVX-LABEL: test7:
; CHECK-AVX: vroundss $4
}
%call = tail call double @rint(double %x) nounwind readnone
ret double %call
-; CHECK-SSE: test8:
+; CHECK-SSE-LABEL: test8:
; CHECK-SSE: roundsd $4
-; CHECK-AVX: test8:
+; CHECK-AVX-LABEL: test8:
; CHECK-AVX: vroundsd $4
}
%call = tail call float @truncf(float %x) nounwind readnone
ret float %call
-; CHECK-SSE: test9:
+; CHECK-SSE-LABEL: test9:
; CHECK-SSE: roundss $3
-; CHECK-AVX: test9:
+; CHECK-AVX-LABEL: test9:
; CHECK-AVX: vroundss $3
}
%call = tail call double @trunc(double %x) nounwind readnone
ret double %call
-; CHECK-SSE: test10:
+; CHECK-SSE-LABEL: test10:
; CHECK-SSE: roundsd $3
-; CHECK-AVX: test10:
+; CHECK-AVX-LABEL: test10:
; CHECK-AVX: vroundsd $3
}
call void @dummy_use (i32* %mem, i32 10)
ret void
-; X32-Linux: test_basic:
+; X32-Linux-LABEL: test_basic:
; X32-Linux: cmpl %gs:48, %esp
; X32-Linux-NEXT: ja .LBB0_2
; X32-Linux-NEXT: calll __morestack
; X32-Linux-NEXT: ret
-; X64-Linux: test_basic:
+; X64-Linux-LABEL: test_basic:
; X64-Linux: cmpq %fs:112, %rsp
; X64-Linux-NEXT: ja .LBB0_2
; X64-Linux-NEXT: callq __morestack
; X64-Linux-NEXT: ret
-; X32-Darwin: test_basic:
+; X32-Darwin-LABEL: test_basic:
; X32-Darwin: movl $432, %ecx
; X32-Darwin-NEXT: cmpl %gs:(%ecx), %esp
; X32-Darwin-NEXT: calll ___morestack
; X32-Darwin-NEXT: ret
-; X64-Darwin: test_basic:
+; X64-Darwin-LABEL: test_basic:
; X64-Darwin: cmpq %gs:816, %rsp
; X64-Darwin-NEXT: ja LBB0_2
; X64-Darwin-NEXT: callq ___morestack
; X64-Darwin-NEXT: ret
-; X32-MinGW: test_basic:
+; X32-MinGW-LABEL: test_basic:
; X32-MinGW: cmpl %fs:20, %esp
; X32-MinGW-NEXT: ja LBB0_2
; X32-MinGW-NEXT: calll ___morestack
; X32-MinGW-NEXT: ret
-; X64-FreeBSD: test_basic:
+; X64-FreeBSD-LABEL: test_basic:
; X64-FreeBSD: cmpq %fs:24, %rsp
; X64-FreeBSD-NEXT: ja .LBB0_2
call void @dummy_use (i32* %mem, i32 10)
ret void
-; X32-Linux: test_fastcc:
+; X32-Linux-LABEL: test_fastcc:
; X32-Linux: cmpl %gs:48, %esp
; X32-Linux-NEXT: ja .LBB3_2
; X32-Linux-NEXT: calll __morestack
; X32-Linux-NEXT: ret
-; X64-Linux: test_fastcc:
+; X64-Linux-LABEL: test_fastcc:
; X64-Linux: cmpq %fs:112, %rsp
; X64-Linux-NEXT: ja .LBB3_2
; X64-Linux-NEXT: callq __morestack
; X64-Linux-NEXT: ret
-; X32-Darwin: test_fastcc:
+; X32-Darwin-LABEL: test_fastcc:
; X32-Darwin: movl $432, %eax
; X32-Darwin-NEXT: cmpl %gs:(%eax), %esp
; X32-Darwin-NEXT: calll ___morestack
; X32-Darwin-NEXT: ret
-; X64-Darwin: test_fastcc:
+; X64-Darwin-LABEL: test_fastcc:
; X64-Darwin: cmpq %gs:816, %rsp
; X64-Darwin-NEXT: ja LBB3_2
; X64-Darwin-NEXT: callq ___morestack
; X64-Darwin-NEXT: ret
-; X32-MinGW: test_fastcc:
+; X32-MinGW-LABEL: test_fastcc:
; X32-MinGW: cmpl %fs:20, %esp
; X32-MinGW-NEXT: ja LBB3_2
; X32-MinGW-NEXT: calll ___morestack
; X32-MinGW-NEXT: ret
-; X64-FreeBSD: test_fastcc:
+; X64-FreeBSD-LABEL: test_fastcc:
; X64-FreeBSD: cmpq %fs:24, %rsp
; X64-FreeBSD-NEXT: ja .LBB3_2
call void @dummy_use (i32* %mem, i32 0)
ret void
-; X32-Linux: test_fastcc_large:
+; X32-Linux-LABEL: test_fastcc_large:
; X32-Linux: leal -40012(%esp), %eax
; X32-Linux-NEXT: cmpl %gs:48, %eax
; X32-Linux-NEXT: calll __morestack
; X32-Linux-NEXT: ret
-; X64-Linux: test_fastcc_large:
+; X64-Linux-LABEL: test_fastcc_large:
; X64-Linux: leaq -40008(%rsp), %r11
; X64-Linux-NEXT: cmpq %fs:112, %r11
; X64-Linux-NEXT: callq __morestack
; X64-Linux-NEXT: ret
-; X32-Darwin: test_fastcc_large:
+; X32-Darwin-LABEL: test_fastcc_large:
; X32-Darwin: leal -40012(%esp), %eax
; X32-Darwin-NEXT: movl $432, %ecx
; X32-Darwin-NEXT: calll ___morestack
; X32-Darwin-NEXT: ret
-; X64-Darwin: test_fastcc_large:
+; X64-Darwin-LABEL: test_fastcc_large:
; X64-Darwin: leaq -40008(%rsp), %r11
; X64-Darwin-NEXT: cmpq %gs:816, %r11
; X64-Darwin-NEXT: callq ___morestack
; X64-Darwin-NEXT: ret
-; X32-MinGW: test_fastcc_large:
+; X32-MinGW-LABEL: test_fastcc_large:
; X32-MinGW: leal -40008(%esp), %eax
; X32-MinGW-NEXT: cmpl %fs:20, %eax
; X32-MinGW-NEXT: calll ___morestack
; X32-MinGW-NEXT: ret
-; X64-FreeBSD: test_fastcc_large:
+; X64-FreeBSD-LABEL: test_fastcc_large:
; X64-FreeBSD: leaq -40008(%rsp), %r11
; X64-FreeBSD-NEXT: cmpq %fs:24, %r11
; This is testing that the Mac implementation preserves ecx
-; X32-Darwin: test_fastcc_large_with_ecx_arg:
+; X32-Darwin-LABEL: test_fastcc_large_with_ecx_arg:
; X32-Darwin: leal -40012(%esp), %eax
; X32-Darwin-NEXT: pushl %ecx
define zeroext i16 @t1(i16 zeroext %x) nounwind readnone ssp {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: seta %al
; CHECK: movzbl %al, %eax
; CHECK: shll $5, %eax
define zeroext i16 @t2(i16 zeroext %x) nounwind readnone ssp {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: sbbl %eax, %eax
; CHECK: andl $32, %eax
%0 = icmp ult i16 %x, 26 ; <i1> [#uses=1]
define i64 @t3(i64 %x) nounwind readnone ssp {
entry:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: sbbq %rax, %rax
; CHECK: andq $64, %rax
%0 = icmp ult i64 %x, 18 ; <i1> [#uses=1]
define i32 @t1(i32 %x) nounwind readnone ssp {
entry:
-; 32: t1:
+; 32-LABEL: t1:
; 32: cmpl $1
; 32: sbbl
-; 64: t1:
+; 64-LABEL: t1:
; 64: cmpl $1
; 64: sbbl
%0 = icmp eq i32 %x, 0
define i32 @t2(i32 %x) nounwind readnone ssp {
entry:
-; 32: t2:
+; 32-LABEL: t2:
; 32: cmpl $1
; 32: sbbl
-; 64: t2:
+; 64-LABEL: t2:
; 64: cmpl $1
; 64: sbbl
%0 = icmp eq i32 %x, 0
define i32 @t3() nounwind readonly {
entry:
-; 32: t3:
+; 32-LABEL: t3:
; 32: cmpl $1
; 32: sbbl
; 32: cmpl
; 32: xorl
-; 64: t3:
+; 64-LABEL: t3:
; 64: cmpl $1
; 64: sbbq
; 64: cmpq
; rdar://7529457
define i64 @t(i64 %A, i64 %B, i32* %P, i64 *%P2) nounwind {
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: movslq %e{{.*}}, %rax
; CHECK: movq %rax
; CHECK: movl %eax
; RUN: llc < %s -mtriple=x86_64-apple-macosx | FileCheck %s --check-prefix=X64
define i32 @t1(i32 %t, i32 %val) nounwind {
-; X32: t1:
+; X32-LABEL: t1:
; X32-NOT: andl
; X32: shll
-; X64: t1:
+; X64-LABEL: t1:
; X64-NOT: andl
; X64: shll
%shamt = and i32 %t, 31
}
define i32 @t2(i32 %t, i32 %val) nounwind {
-; X32: t2:
+; X32-LABEL: t2:
; X32-NOT: andl
; X32: shll
-; X64: t2:
+; X64-LABEL: t2:
; X64-NOT: andl
; X64: shll
%shamt = and i32 %t, 63
@X = internal global i16 0
define void @t3(i16 %t) nounwind {
-; X32: t3:
+; X32-LABEL: t3:
; X32-NOT: andl
; X32: sarw
-; X64: t3:
+; X64-LABEL: t3:
; X64-NOT: andl
; X64: sarw
%shamt = and i16 %t, 31
}
define i64 @t4(i64 %t, i64 %val) nounwind {
-; X64: t4:
+; X64-LABEL: t4:
; X64-NOT: and
; X64: shrq
%shamt = and i64 %t, 63
}
define i64 @t5(i64 %t, i64 %val) nounwind {
-; X64: t5:
+; X64-LABEL: t5:
; X64-NOT: and
; X64: shrq
%shamt = and i64 %t, 191
; rdar://11866926
define i64 @t6(i64 %key, i64* nocapture %val) nounwind {
entry:
-; X64: t6:
+; X64-LABEL: t6:
; X64-NOT: movabsq
; X64: decq
; X64: andq
define void @fn1() {
-; CHECK: fn1:
+; CHECK-LABEL: fn1:
; CHECK-NOT: ret
; CHECK-NOT: lea
; CHECK: shll $3
}
define i32 @fn2(i32 %X, i32 %Y) {
-; CHECK: fn2:
+; CHECK-LABEL: fn2:
; CHECK-NOT: ret
; CHECK-NOT: lea
; CHECK: shll $3
ret void
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
declare void @bar(i64)
%tmp456 = sext i16 %tmp45 to i32 ; <i32> [#uses=1]
ret i32 %tmp456
-; CHECK: test1:
+; CHECK-LABEL: test1:
; CHECK: movl 8(%esp), %eax
; CHECK: shrl %eax
; CHECK: cwtl
define void @t1(i8* nocapture %value) nounwind {
entry:
-; 32: t1:
+; 32-LABEL: t1:
; 32: jmpl *4(%esp)
-; 64: t1:
+; 64-LABEL: t1:
; 64: jmpq *%rdi
%0 = bitcast i8* %value to void ()*
tail call void %0() nounwind
define void @t2(i32 %a, i8* nocapture %value) nounwind {
entry:
-; 32: t2:
+; 32-LABEL: t2:
; 32: jmpl *8(%esp)
-; 64: t2:
+; 64-LABEL: t2:
; 64: jmpq *%rsi
%0 = bitcast i8* %value to void ()*
tail call void %0() nounwind
define void @t3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i8* nocapture %value) nounwind {
entry:
-; 32: t3:
+; 32-LABEL: t3:
; 32: jmpl *28(%esp)
-; 64: t3:
+; 64-LABEL: t3:
; 64: jmpq *8(%rsp)
%0 = bitcast i8* %value to void ()*
tail call void %0() nounwind
define void @t4(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i8* nocapture %value) nounwind {
entry:
-; 32: t4:
+; 32-LABEL: t4:
; 32: jmpl *32(%esp)
-; 64: t4:
+; 64-LABEL: t4:
; 64: jmpq *16(%rsp)
%0 = bitcast i8* %value to void ()*
tail call void %0() nounwind
; PR7193
define void @t1(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: calll 0
tail call void null(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind
ret void
}
define void @t2(i8* inreg %dst, i8* inreg %src, i8* inreg %len) nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: jmpl
tail call void null(i8* inreg %dst, i8* inreg %src) nounwind
ret void
define cc10 void @t(i32* %Base_Arg, i32* %Sp_Arg, i32* %Hp_Arg, i32 %R1_Arg) nounwind {
cm1:
-; CHECK: t:
+; CHECK-LABEL: t:
; CHECK: jmpl *%eax
%nm3 = getelementptr i32* %Sp_Arg, i32 1
%nm9 = load i32* %Sp_Arg
define double @foo(double %a) nounwind readonly ssp {
entry:
-; X32: foo:
+; X32-LABEL: foo:
; X32: jmp _sin$stub
-; X64: foo:
+; X64-LABEL: foo:
; X64: jmp _sin
%0 = tail call double @sin(double %a) nounwind readonly
ret double %0
}
define float @bar(float %a) nounwind readonly ssp {
-; X32: bar:
+; X32-LABEL: bar:
; X32: jmp _sinf$stub
-; X64: bar:
+; X64-LABEL: bar:
; X64: jmp _sinf
entry:
%0 = tail call float @sinf(float %a) nounwind readonly
define void @t1(i32 %x) nounwind ssp {
entry:
-; 32: t1:
+; 32-LABEL: t1:
; 32: jmp {{_?}}foo
-; 64: t1:
+; 64-LABEL: t1:
; 64: jmp {{_?}}foo
tail call void @foo() nounwind
ret void
define void @t2() nounwind ssp {
entry:
-; 32: t2:
+; 32-LABEL: t2:
; 32: jmp {{_?}}foo2
-; 64: t2:
+; 64-LABEL: t2:
; 64: jmp {{_?}}foo2
%0 = tail call i32 @foo2() nounwind
ret void
define void @t3() nounwind ssp {
entry:
-; 32: t3:
+; 32-LABEL: t3:
; 32: jmp {{_?}}foo3
-; 64: t3:
+; 64-LABEL: t3:
; 64: jmp {{_?}}foo3
%0 = tail call i32 @foo3() nounwind
ret void
define void @t4(void (i32)* nocapture %x) nounwind ssp {
entry:
-; 32: t4:
+; 32-LABEL: t4:
; 32: calll *
; FIXME: gcc can generate a tailcall for this. But it's tricky.
-; 64: t4:
+; 64-LABEL: t4:
; 64-NOT: call
; 64: jmpq *
tail call void %x(i32 0) nounwind
define void @t5(void ()* nocapture %x) nounwind ssp {
entry:
-; 32: t5:
+; 32-LABEL: t5:
; 32-NOT: call
; 32: jmpl *4(%esp)
-; 64: t5:
+; 64-LABEL: t5:
; 64-NOT: call
; 64: jmpq *%rdi
tail call void %x() nounwind
define i32 @t6(i32 %x) nounwind ssp {
entry:
-; 32: t6:
+; 32-LABEL: t6:
; 32: calll {{_?}}t6
; 32: jmp {{_?}}bar
-; 64: t6:
+; 64-LABEL: t6:
; 64: jmp {{_?}}t6
; 64: jmp {{_?}}bar
%0 = icmp slt i32 %x, 10
define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
entry:
-; 32: t7:
+; 32-LABEL: t7:
; 32: jmp {{_?}}bar2
-; 64: t7:
+; 64-LABEL: t7:
; 64: jmp {{_?}}bar2
%0 = tail call i32 @bar2(i32 %a, i32 %b, i32 %c) nounwind
ret i32 %0
define signext i16 @t8() nounwind ssp {
entry:
-; 32: t8:
+; 32-LABEL: t8:
; 32: calll {{_?}}bar3
-; 64: t8:
+; 64-LABEL: t8:
; 64: callq {{_?}}bar3
%0 = tail call signext i16 @bar3() nounwind ; <i16> [#uses=1]
ret i16 %0
define signext i16 @t9(i32 (i32)* nocapture %x) nounwind ssp {
entry:
-; 32: t9:
+; 32-LABEL: t9:
; 32: calll *
-; 64: t9:
+; 64-LABEL: t9:
; 64: callq *
%0 = bitcast i32 (i32)* %x to i16 (i32)*
%1 = tail call signext i16 %0(i32 0) nounwind
define void @t10() nounwind ssp {
entry:
-; 32: t10:
+; 32-LABEL: t10:
; 32: calll
-; 64: t10:
+; 64-LABEL: t10:
; 64: callq
%0 = tail call i32 @foo4() noreturn nounwind
unreachable
; In 32-bit mode, it's emitting a bunch of dead loads that are not being
; eliminated currently.
-; 32: t11:
+; 32-LABEL: t11:
; 32-NOT: subl ${{[0-9]+}}, %esp
; 32: je
; 32-NOT: movl
; 32-NOT: addl ${{[0-9]+}}, %esp
; 32: jmp {{_?}}foo5
-; 64: t11:
+; 64-LABEL: t11:
; 64-NOT: subq ${{[0-9]+}}, %esp
; 64-NOT: addq ${{[0-9]+}}, %esp
; 64: jmp {{_?}}foo5
%struct.t = type { i32, i32, i32, i32, i32 }
define i32 @t12(i32 %x, i32 %y, %struct.t* byval align 4 %z) nounwind ssp {
-; 32: t12:
+; 32-LABEL: t12:
; 32-NOT: subl ${{[0-9]+}}, %esp
; 32-NOT: addl ${{[0-9]+}}, %esp
; 32: jmp {{_?}}foo6
-; 64: t12:
+; 64-LABEL: t12:
; 64-NOT: subq ${{[0-9]+}}, %esp
; 64-NOT: addq ${{[0-9]+}}, %esp
; 64: jmp {{_?}}foo6
%struct.cp = type { float, float, float, float, float }
define %struct.ns* @t13(%struct.cp* %yy) nounwind ssp {
-; 32: t13:
+; 32-LABEL: t13:
; 32-NOT: jmp
; 32: calll
; 32: ret
-; 64: t13:
+; 64-LABEL: t13:
; 64-NOT: jmp
; 64: callq
; 64: ret
define void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp {
entry:
-; 64: t14:
+; 64-LABEL: t14:
; 64: movq 32(%rdi)
; 64-NOT: movq 16(%rdi)
; 64: jmpq *16({{%rdi|%rax}})
%struct.foo = type { [4 x i32] }
define void @t15(%struct.foo* noalias sret %agg.result) nounwind {
-; 32: t15:
+; 32-LABEL: t15:
; 32: calll {{_?}}f
; 32: ret $4
-; 64: t15:
+; 64-LABEL: t15:
; 64: callq {{_?}}f
; 64: ret
tail call fastcc void @f(%struct.foo* noalias sret %agg.result) nounwind
define void @t16() nounwind ssp {
entry:
-; 32: t16:
+; 32-LABEL: t16:
; 32: calll {{_?}}bar4
; 32: fstp
-; 64: t16:
+; 64-LABEL: t16:
; 64: jmp {{_?}}bar4
%0 = tail call double @bar4() nounwind
ret void
; rdar://6283267
define void @t17() nounwind ssp {
entry:
-; 32: t17:
+; 32-LABEL: t17:
; 32: jmp {{_?}}bar5
-; 64: t17:
+; 64-LABEL: t17:
; 64: xorl %eax, %eax
; 64: jmp {{_?}}bar5
tail call void (...)* @bar5() nounwind
; rdar://7774847
define void @t18() nounwind ssp {
entry:
-; 32: t18:
+; 32-LABEL: t18:
; 32: calll {{_?}}bar6
; 32: fstp %st(0)
-; 64: t18:
+; 64-LABEL: t18:
; 64: xorl %eax, %eax
; 64: jmp {{_?}}bar6
%0 = tail call double (...)* @bar6() nounwind
define void @t19() alignstack(32) nounwind {
entry:
-; CHECK: t19:
+; CHECK-LABEL: t19:
; CHECK: andl $-32
; CHECK: calll {{_?}}foo
tail call void @foo() nounwind
define double @t20(double %x) nounwind {
entry:
-; 32: t20:
+; 32-LABEL: t20:
; 32: calll {{_?}}foo20
; 32: fldl (%esp)
-; 64: t20:
+; 64-LABEL: t20:
; 64: jmp {{_?}}foo20
%0 = tail call fastcc double @foo20(double %x) nounwind
ret double %0
; evaluated, however with MachineSink we can sink the other side so
; that it's conditionally evaluated.
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne
; CHECK-NEXT: divsd
; the conditional branch.
; rdar://8454886
-; CHECK: split:
+; CHECK-LABEL: split:
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: jne
; CHECK-NEXT: movaps
; Hoist floating-point constant-pool loads out of loops.
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: movsd
; CHECK: align
define void @bar(double* nocapture %p, i64 %n) nounwind {
; Codegen should hoist and CSE these constants.
-; CHECK: vv:
+; CHECK-LABEL: vv:
; CHECK: LCPI3_0(%rip), %xmm0
; CHECK: LCPI3_1(%rip), %xmm1
; CHECK: LCPI3_2(%rip), %xmm2
; CodeGen should use the correct register class when extracting
; a load from a zero-extending load for hoisting.
-; CHECK: default_get_pch_validity:
+; CHECK-LABEL: default_get_pch_validity:
; CHECK: movl cl_options_count(%rip), %ecx
@cl_options_count = external constant i32 ; <i32*> [#uses=2]
define <2 x i64> @t2() nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: pshufd $85, (%esp), %xmm0
%array = alloca [8 x float], align 4
%arrayidx = getelementptr inbounds [8 x float]* %array, i32 0, i32 1
; RUN: llc < %s -march=x86-64 -mcpu=nehalem | FileCheck %s
-; CHECK: a:
+; CHECK-LABEL: a:
; CHECK: movdqu
; CHECK: pshufd
define <4 x float> @a(<4 x float>* %y) nounwind {
ret <4 x float> %s
}
-; CHECK: b:
+; CHECK-LABEL: b:
; CHECK: movups
; CHECK: unpckhps
define <4 x float> @b(<4 x float>* %y, <4 x float> %z) nounwind {
ret <4 x float> %s
}
-; CHECK: c:
+; CHECK-LABEL: c:
; CHECK: movupd
; CHECK: shufpd
define <2 x double> @c(<2 x double>* %y) nounwind {
ret <2 x double> %r
}
-; CHECK: d:
+; CHECK-LABEL: d:
; CHECK: movupd
; CHECK: unpckhpd
define <2 x double> @d(<2 x double>* %y, <2 x double> %z) nounwind {
ret <4 x float> %z
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: movups
; CHECK: ret
ret <2 x double> %z
}
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: movupd
; CHECK: ret
; Commute the comparison to avoid a move.
; PR7500.
-; CHECK: a:
+; CHECK-LABEL: a:
; CHECK-NOT: mov
; CHECK: pcmpeqd
define <2 x double> @a(<2 x double>, <2 x double>) nounwind readnone {
; _y: use -0.0 instead of %y
; _inverse : swap the arms of the select.
-; CHECK: ogt:
+; CHECK-LABEL: ogt:
; CHECK-NEXT: maxsd %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ogt:
+; UNSAFE-LABEL: ogt:
; UNSAFE-NEXT: maxsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ogt:
+; FINITE-LABEL: ogt:
; FINITE-NEXT: maxsd %xmm1, %xmm0
; FINITE-NEXT: ret
define double @ogt(double %x, double %y) nounwind {
ret double %d
}
-; CHECK: olt:
+; CHECK-LABEL: olt:
; CHECK-NEXT: minsd %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: olt:
+; UNSAFE-LABEL: olt:
; UNSAFE-NEXT: minsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: olt:
+; FINITE-LABEL: olt:
; FINITE-NEXT: minsd %xmm1, %xmm0
; FINITE-NEXT: ret
define double @olt(double %x, double %y) nounwind {
ret double %d
}
-; CHECK: ogt_inverse:
+; CHECK-LABEL: ogt_inverse:
; CHECK-NEXT: minsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ogt_inverse:
+; UNSAFE-LABEL: ogt_inverse:
; UNSAFE-NEXT: minsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ogt_inverse:
+; FINITE-LABEL: ogt_inverse:
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: olt_inverse:
+; CHECK-LABEL: olt_inverse:
; CHECK-NEXT: maxsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: olt_inverse:
+; UNSAFE-LABEL: olt_inverse:
; UNSAFE-NEXT: maxsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: olt_inverse:
+; FINITE-LABEL: olt_inverse:
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: oge:
+; CHECK-LABEL: oge:
; CHECK-NEXT: ucomisd %xmm1, %xmm0
-; UNSAFE: oge:
+; UNSAFE-LABEL: oge:
; UNSAFE-NEXT: maxsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: oge:
+; FINITE-LABEL: oge:
; FINITE-NEXT: maxsd %xmm1, %xmm0
; FINITE-NEXT: ret
define double @oge(double %x, double %y) nounwind {
ret double %d
}
-; CHECK: ole:
+; CHECK-LABEL: ole:
; CHECK-NEXT: ucomisd %xmm0, %xmm1
-; UNSAFE: ole:
+; UNSAFE-LABEL: ole:
; UNSAFE-NEXT: minsd %xmm1, %xmm0
-; FINITE: ole:
+; FINITE-LABEL: ole:
; FINITE-NEXT: minsd %xmm1, %xmm0
define double @ole(double %x, double %y) nounwind {
%c = fcmp ole double %x, %y
ret double %d
}
-; CHECK: oge_inverse:
+; CHECK-LABEL: oge_inverse:
; CHECK-NEXT: ucomisd %xmm1, %xmm0
-; UNSAFE: oge_inverse:
+; UNSAFE-LABEL: oge_inverse:
; UNSAFE-NEXT: minsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: oge_inverse:
+; FINITE-LABEL: oge_inverse:
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ole_inverse:
+; CHECK-LABEL: ole_inverse:
; CHECK-NEXT: ucomisd %xmm0, %xmm1
-; UNSAFE: ole_inverse:
+; UNSAFE-LABEL: ole_inverse:
; UNSAFE-NEXT: maxsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ole_inverse:
+; FINITE-LABEL: ole_inverse:
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ogt_x:
+; CHECK-LABEL: ogt_x:
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; CHECK-NEXT: maxsd %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ogt_x:
+; UNSAFE-LABEL: ogt_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: maxsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ogt_x:
+; FINITE-LABEL: ogt_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: maxsd %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: olt_x:
+; CHECK-LABEL: olt_x:
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; CHECK-NEXT: minsd %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: olt_x:
+; UNSAFE-LABEL: olt_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: minsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: olt_x:
+; FINITE-LABEL: olt_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: minsd %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ogt_inverse_x:
+; CHECK-LABEL: ogt_inverse_x:
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; CHECK-NEXT: minsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ogt_inverse_x:
+; UNSAFE-LABEL: ogt_inverse_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: minsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ogt_inverse_x:
+; FINITE-LABEL: ogt_inverse_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: olt_inverse_x:
+; CHECK-LABEL: olt_inverse_x:
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; CHECK-NEXT: maxsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: olt_inverse_x:
+; UNSAFE-LABEL: olt_inverse_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: maxsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: olt_inverse_x:
+; FINITE-LABEL: olt_inverse_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: oge_x:
+; CHECK-LABEL: oge_x:
; CHECK: ucomisd %xmm1, %xmm0
-; UNSAFE: oge_x:
+; UNSAFE-LABEL: oge_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: maxsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: oge_x:
+; FINITE-LABEL: oge_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: maxsd %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ole_x:
+; CHECK-LABEL: ole_x:
; CHECK: ucomisd %xmm0, %xmm1
-; UNSAFE: ole_x:
+; UNSAFE-LABEL: ole_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: minsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ole_x:
+; FINITE-LABEL: ole_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: minsd %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: oge_inverse_x:
+; CHECK-LABEL: oge_inverse_x:
; CHECK: ucomisd %xmm
-; UNSAFE: oge_inverse_x:
+; UNSAFE-LABEL: oge_inverse_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: minsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: oge_inverse_x:
+; FINITE-LABEL: oge_inverse_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ole_inverse_x:
+; CHECK-LABEL: ole_inverse_x:
; CHECK: ucomisd %xmm
-; UNSAFE: ole_inverse_x:
+; UNSAFE-LABEL: ole_inverse_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: maxsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ole_inverse_x:
+; FINITE-LABEL: ole_inverse_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ugt:
+; CHECK-LABEL: ugt:
; CHECK: ucomisd %xmm0, %xmm1
-; UNSAFE: ugt:
+; UNSAFE-LABEL: ugt:
; UNSAFE-NEXT: maxsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ugt:
+; FINITE-LABEL: ugt:
; FINITE-NEXT: maxsd %xmm1, %xmm0
; FINITE-NEXT: ret
define double @ugt(double %x, double %y) nounwind {
ret double %d
}
-; CHECK: ult:
+; CHECK-LABEL: ult:
; CHECK: ucomisd %xmm1, %xmm0
-; UNSAFE: ult:
+; UNSAFE-LABEL: ult:
; UNSAFE-NEXT: minsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ult:
+; FINITE-LABEL: ult:
; FINITE-NEXT: minsd %xmm1, %xmm0
; FINITE-NEXT: ret
define double @ult(double %x, double %y) nounwind {
ret double %d
}
-; CHECK: ugt_inverse:
+; CHECK-LABEL: ugt_inverse:
; CHECK: ucomisd %xmm0, %xmm1
-; UNSAFE: ugt_inverse:
+; UNSAFE-LABEL: ugt_inverse:
; UNSAFE-NEXT: minsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ugt_inverse:
+; FINITE-LABEL: ugt_inverse:
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ult_inverse:
+; CHECK-LABEL: ult_inverse:
; CHECK: ucomisd %xmm1, %xmm0
-; UNSAFE: ult_inverse:
+; UNSAFE-LABEL: ult_inverse:
; UNSAFE-NEXT: maxsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ult_inverse:
+; FINITE-LABEL: ult_inverse:
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: uge:
+; CHECK-LABEL: uge:
; CHECK-NEXT: maxsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: uge:
+; UNSAFE-LABEL: uge:
; UNSAFE-NEXT: maxsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: uge:
+; FINITE-LABEL: uge:
; FINITE-NEXT: maxsd %xmm1, %xmm0
; FINITE-NEXT: ret
define double @uge(double %x, double %y) nounwind {
ret double %d
}
-; CHECK: ule:
+; CHECK-LABEL: ule:
; CHECK-NEXT: minsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ule:
+; UNSAFE-LABEL: ule:
; UNSAFE-NEXT: minsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ule:
+; FINITE-LABEL: ule:
; FINITE-NEXT: minsd %xmm1, %xmm0
; FINITE-NEXT: ret
define double @ule(double %x, double %y) nounwind {
ret double %d
}
-; CHECK: uge_inverse:
+; CHECK-LABEL: uge_inverse:
; CHECK-NEXT: minsd %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: uge_inverse:
+; UNSAFE-LABEL: uge_inverse:
; UNSAFE-NEXT: minsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: uge_inverse:
+; FINITE-LABEL: uge_inverse:
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ule_inverse:
+; CHECK-LABEL: ule_inverse:
; CHECK-NEXT: maxsd %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ule_inverse:
+; UNSAFE-LABEL: ule_inverse:
; UNSAFE-NEXT: maxsd %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ule_inverse:
+; FINITE-LABEL: ule_inverse:
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ugt_x:
+; CHECK-LABEL: ugt_x:
; CHECK: ucomisd %xmm0, %xmm1
-; UNSAFE: ugt_x:
+; UNSAFE-LABEL: ugt_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: maxsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ugt_x:
+; FINITE-LABEL: ugt_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: maxsd %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ult_x:
+; CHECK-LABEL: ult_x:
; CHECK: ucomisd %xmm1, %xmm0
-; UNSAFE: ult_x:
+; UNSAFE-LABEL: ult_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: minsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ult_x:
+; FINITE-LABEL: ult_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: minsd %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ugt_inverse_x:
+; CHECK-LABEL: ugt_inverse_x:
; CHECK: ucomisd %xmm
-; UNSAFE: ugt_inverse_x:
+; UNSAFE-LABEL: ugt_inverse_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: minsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ugt_inverse_x:
+; FINITE-LABEL: ugt_inverse_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ult_inverse_x:
+; CHECK-LABEL: ult_inverse_x:
; CHECK: ucomisd %xmm
-; UNSAFE: ult_inverse_x:
+; UNSAFE-LABEL: ult_inverse_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: maxsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ult_inverse_x:
+; FINITE-LABEL: ult_inverse_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: uge_x:
+; CHECK-LABEL: uge_x:
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; CHECK-NEXT: maxsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: uge_x:
+; UNSAFE-LABEL: uge_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: maxsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: uge_x:
+; FINITE-LABEL: uge_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: maxsd %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: ule_x:
+; CHECK-LABEL: ule_x:
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; CHECK-NEXT: minsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ule_x:
+; UNSAFE-LABEL: ule_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: minsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ule_x:
+; FINITE-LABEL: ule_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: minsd %xmm1, %xmm0
; FINITE-NEXT: ret
ret double %d
}
-; CHECK: uge_inverse_x:
+; CHECK-LABEL: uge_inverse_x:
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; CHECK-NEXT: minsd %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: uge_inverse_x:
+; UNSAFE-LABEL: uge_inverse_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: minsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: uge_inverse_x:
+; FINITE-LABEL: uge_inverse_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ule_inverse_x:
+; CHECK-LABEL: ule_inverse_x:
; CHECK-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; CHECK-NEXT: maxsd %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ule_inverse_x:
+; UNSAFE-LABEL: ule_inverse_x:
; UNSAFE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; UNSAFE-NEXT: maxsd %xmm0, %xmm1
; UNSAFE-NEXT: movap{{[sd]}} %xmm1, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ule_inverse_x:
+; FINITE-LABEL: ule_inverse_x:
; FINITE-NEXT: xorp{{[sd]}} %xmm1, %xmm1
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ogt_y:
+; CHECK-LABEL: ogt_y:
; CHECK-NEXT: maxsd {{[^,]*}}, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ogt_y:
+; UNSAFE-LABEL: ogt_y:
; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ogt_y:
+; FINITE-LABEL: ogt_y:
; FINITE-NEXT: maxsd {{[^,]*}}, %xmm0
; FINITE-NEXT: ret
define double @ogt_y(double %x) nounwind {
ret double %d
}
-; CHECK: olt_y:
+; CHECK-LABEL: olt_y:
; CHECK-NEXT: minsd {{[^,]*}}, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: olt_y:
+; UNSAFE-LABEL: olt_y:
; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: olt_y:
+; FINITE-LABEL: olt_y:
; FINITE-NEXT: minsd {{[^,]*}}, %xmm0
; FINITE-NEXT: ret
define double @olt_y(double %x) nounwind {
ret double %d
}
-; CHECK: ogt_inverse_y:
+; CHECK-LABEL: ogt_inverse_y:
; CHECK-NEXT: movsd {{[^,]*}}, %xmm1
; CHECK-NEXT: minsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ogt_inverse_y:
+; UNSAFE-LABEL: ogt_inverse_y:
; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ogt_inverse_y:
+; FINITE-LABEL: ogt_inverse_y:
; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: olt_inverse_y:
+; CHECK-LABEL: olt_inverse_y:
; CHECK-NEXT: movsd {{[^,]*}}, %xmm1
; CHECK-NEXT: maxsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: olt_inverse_y:
+; UNSAFE-LABEL: olt_inverse_y:
; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: olt_inverse_y:
+; FINITE-LABEL: olt_inverse_y:
; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: oge_y:
+; CHECK-LABEL: oge_y:
; CHECK: ucomisd %xmm1, %xmm0
-; UNSAFE: oge_y:
+; UNSAFE-LABEL: oge_y:
; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: oge_y:
+; FINITE-LABEL: oge_y:
; FINITE-NEXT: maxsd {{[^,]*}}, %xmm0
; FINITE-NEXT: ret
define double @oge_y(double %x) nounwind {
ret double %d
}
-; CHECK: ole_y:
+; CHECK-LABEL: ole_y:
; CHECK: ucomisd %xmm0, %xmm1
-; UNSAFE: ole_y:
+; UNSAFE-LABEL: ole_y:
; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ole_y:
+; FINITE-LABEL: ole_y:
; FINITE-NEXT: minsd {{[^,]*}}, %xmm0
; FINITE-NEXT: ret
define double @ole_y(double %x) nounwind {
ret double %d
}
-; CHECK: oge_inverse_y:
+; CHECK-LABEL: oge_inverse_y:
; CHECK: ucomisd %xmm
-; UNSAFE: oge_inverse_y:
+; UNSAFE-LABEL: oge_inverse_y:
; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: oge_inverse_y:
+; FINITE-LABEL: oge_inverse_y:
; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ole_inverse_y:
+; CHECK-LABEL: ole_inverse_y:
; CHECK: ucomisd %xmm
-; UNSAFE: ole_inverse_y:
+; UNSAFE-LABEL: ole_inverse_y:
; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ole_inverse_y:
+; FINITE-LABEL: ole_inverse_y:
; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ugt_y:
+; CHECK-LABEL: ugt_y:
; CHECK: ucomisd %xmm0, %xmm1
-; UNSAFE: ugt_y:
+; UNSAFE-LABEL: ugt_y:
; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ugt_y:
+; FINITE-LABEL: ugt_y:
; FINITE-NEXT: maxsd {{[^,]*}}, %xmm0
; FINITE-NEXT: ret
define double @ugt_y(double %x) nounwind {
ret double %d
}
-; CHECK: ult_y:
+; CHECK-LABEL: ult_y:
; CHECK: ucomisd %xmm1, %xmm0
-; UNSAFE: ult_y:
+; UNSAFE-LABEL: ult_y:
; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ult_y:
+; FINITE-LABEL: ult_y:
; FINITE-NEXT: minsd {{[^,]*}}, %xmm0
; FINITE-NEXT: ret
define double @ult_y(double %x) nounwind {
ret double %d
}
-; CHECK: ugt_inverse_y:
+; CHECK-LABEL: ugt_inverse_y:
; CHECK: ucomisd %xmm
-; UNSAFE: ugt_inverse_y:
+; UNSAFE-LABEL: ugt_inverse_y:
; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ugt_inverse_y:
+; FINITE-LABEL: ugt_inverse_y:
; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ult_inverse_y:
+; CHECK-LABEL: ult_inverse_y:
; CHECK: ucomisd %xmm
-; UNSAFE: ult_inverse_y:
+; UNSAFE-LABEL: ult_inverse_y:
; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ult_inverse_y:
+; FINITE-LABEL: ult_inverse_y:
; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: uge_y:
+; CHECK-LABEL: uge_y:
; CHECK-NEXT: movsd {{[^,]*}}, %xmm1
; CHECK-NEXT: maxsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: uge_y:
+; UNSAFE-LABEL: uge_y:
; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: uge_y:
+; FINITE-LABEL: uge_y:
; FINITE-NEXT: maxsd {{[^,]*}}, %xmm0
; FINITE-NEXT: ret
define double @uge_y(double %x) nounwind {
ret double %d
}
-; CHECK: ule_y:
+; CHECK-LABEL: ule_y:
; CHECK-NEXT: movsd {{[^,]*}}, %xmm1
; CHECK-NEXT: minsd %xmm0, %xmm1
; CHECK-NEXT: movap{{[sd]}} %xmm1, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ule_y:
+; UNSAFE-LABEL: ule_y:
; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ule_y:
+; FINITE-LABEL: ule_y:
; FINITE-NEXT: minsd {{[^,]*}}, %xmm0
; FINITE-NEXT: ret
define double @ule_y(double %x) nounwind {
ret double %d
}
-; CHECK: uge_inverse_y:
+; CHECK-LABEL: uge_inverse_y:
; CHECK-NEXT: minsd {{[^,]*}}, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: uge_inverse_y:
+; UNSAFE-LABEL: uge_inverse_y:
; UNSAFE-NEXT: minsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: uge_inverse_y:
+; FINITE-LABEL: uge_inverse_y:
; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
; FINITE-NEXT: minsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
ret double %d
}
-; CHECK: ule_inverse_y:
+; CHECK-LABEL: ule_inverse_y:
; CHECK-NEXT: maxsd {{[^,]*}}, %xmm0
; CHECK-NEXT: ret
-; UNSAFE: ule_inverse_y:
+; UNSAFE-LABEL: ule_inverse_y:
; UNSAFE-NEXT: maxsd {{[^,]*}}, %xmm0
; UNSAFE-NEXT: ret
-; FINITE: ule_inverse_y:
+; FINITE-LABEL: ule_inverse_y:
; FINITE-NEXT: movsd {{[^,]*}}, %xmm1
; FINITE-NEXT: maxsd %xmm0, %xmm1
; FINITE-NEXT: movap{{[sd]}} %xmm1, %xmm0
}
; Test a few more misc. cases.
-; CHECK: clampTo3k_a:
+; CHECK-LABEL: clampTo3k_a:
; CHECK: minsd
-; UNSAFE: clampTo3k_a:
+; UNSAFE-LABEL: clampTo3k_a:
; UNSAFE: minsd
-; FINITE: clampTo3k_a:
+; FINITE-LABEL: clampTo3k_a:
; FINITE: minsd
define double @clampTo3k_a(double %x) nounwind readnone {
entry:
ret double %x_addr.0
}
-; CHECK: clampTo3k_b:
+; CHECK-LABEL: clampTo3k_b:
; CHECK: minsd
-; UNSAFE: clampTo3k_b:
+; UNSAFE-LABEL: clampTo3k_b:
; UNSAFE: minsd
-; FINITE: clampTo3k_b:
+; FINITE-LABEL: clampTo3k_b:
; FINITE: minsd
define double @clampTo3k_b(double %x) nounwind readnone {
entry:
ret double %x_addr.0
}
-; CHECK: clampTo3k_c:
+; CHECK-LABEL: clampTo3k_c:
; CHECK: maxsd
-; UNSAFE: clampTo3k_c:
+; UNSAFE-LABEL: clampTo3k_c:
; UNSAFE: maxsd
-; FINITE: clampTo3k_c:
+; FINITE-LABEL: clampTo3k_c:
; FINITE: maxsd
define double @clampTo3k_c(double %x) nounwind readnone {
entry:
ret double %x_addr.0
}
-; CHECK: clampTo3k_d:
+; CHECK-LABEL: clampTo3k_d:
; CHECK: maxsd
-; UNSAFE: clampTo3k_d:
+; UNSAFE-LABEL: clampTo3k_d:
; UNSAFE: maxsd
-; FINITE: clampTo3k_d:
+; FINITE-LABEL: clampTo3k_d:
; FINITE: maxsd
define double @clampTo3k_d(double %x) nounwind readnone {
entry:
ret double %x_addr.0
}
-; CHECK: clampTo3k_e:
+; CHECK-LABEL: clampTo3k_e:
; CHECK: maxsd
-; UNSAFE: clampTo3k_e:
+; UNSAFE-LABEL: clampTo3k_e:
; UNSAFE: maxsd
-; FINITE: clampTo3k_e:
+; FINITE-LABEL: clampTo3k_e:
; FINITE: maxsd
define double @clampTo3k_e(double %x) nounwind readnone {
entry:
ret double %x_addr.0
}
-; CHECK: clampTo3k_f:
+; CHECK-LABEL: clampTo3k_f:
; CHECK: maxsd
-; UNSAFE: clampTo3k_f:
+; UNSAFE-LABEL: clampTo3k_f:
; UNSAFE: maxsd
-; FINITE: clampTo3k_f:
+; FINITE-LABEL: clampTo3k_f:
; FINITE: maxsd
define double @clampTo3k_f(double %x) nounwind readnone {
entry:
ret double %x_addr.0
}
-; CHECK: clampTo3k_g:
+; CHECK-LABEL: clampTo3k_g:
; CHECK: minsd
-; UNSAFE: clampTo3k_g:
+; UNSAFE-LABEL: clampTo3k_g:
; UNSAFE: minsd
-; FINITE: clampTo3k_g:
+; FINITE-LABEL: clampTo3k_g:
; FINITE: minsd
define double @clampTo3k_g(double %x) nounwind readnone {
entry:
ret double %x_addr.0
}
-; CHECK: clampTo3k_h:
+; CHECK-LABEL: clampTo3k_h:
; CHECK: minsd
-; UNSAFE: clampTo3k_h:
+; UNSAFE-LABEL: clampTo3k_h:
; UNSAFE: minsd
-; FINITE: clampTo3k_h:
+; FINITE-LABEL: clampTo3k_h:
; FINITE: minsd
define double @clampTo3k_h(double %x) nounwind readnone {
entry:
ret double %x_addr.0
}
-; UNSAFE: maxpd:
+; UNSAFE-LABEL: maxpd:
; UNSAFE: maxpd
define <2 x double> @maxpd(<2 x double> %x, <2 x double> %y) {
%max_is_x = fcmp oge <2 x double> %x, %y
ret <2 x double> %max
}
-; UNSAFE: minpd:
+; UNSAFE-LABEL: minpd:
; UNSAFE: minpd
define <2 x double> @minpd(<2 x double> %x, <2 x double> %y) {
%min_is_x = fcmp ole <2 x double> %x, %y
ret <2 x double> %min
}
-; UNSAFE: maxps:
+; UNSAFE-LABEL: maxps:
; UNSAFE: maxps
define <4 x float> @maxps(<4 x float> %x, <4 x float> %y) {
%max_is_x = fcmp oge <4 x float> %x, %y
ret <4 x float> %max
}
-; UNSAFE: minps:
+; UNSAFE-LABEL: minps:
; UNSAFE: minps
define <4 x float> @minps(<4 x float> %x, <4 x float> %y) {
%min_is_x = fcmp ole <4 x float> %x, %y
store <8 x i16> %tmp6, <8 x i16>* %dest
ret void
-; X64: t0:
+; X64-LABEL: t0:
; X64: movdqa (%rsi), %xmm0
; X64: pslldq $2, %xmm0
; X64: movdqa %xmm0, (%rdi)
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> < i32 8, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7 >
ret <8 x i16> %tmp3
-; X64: t1:
+; X64-LABEL: t1:
; X64: movdqa (%rdi), %xmm0
; X64: pinsrw $0, (%rsi), %xmm0
; X64: ret
define <8 x i16> @t2(<8 x i16> %A, <8 x i16> %B) nounwind {
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 9, i32 1, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7 >
ret <8 x i16> %tmp
-; X64: t2:
+; X64-LABEL: t2:
; X64: pextrw $1, %xmm1, %eax
; X64: pinsrw $0, %eax, %xmm0
; X64: pinsrw $3, %eax, %xmm0
define <8 x i16> @t3(<8 x i16> %A, <8 x i16> %B) nounwind {
%tmp = shufflevector <8 x i16> %A, <8 x i16> %A, <8 x i32> < i32 8, i32 3, i32 2, i32 13, i32 7, i32 6, i32 5, i32 4 >
ret <8 x i16> %tmp
-; X64: t3:
+; X64-LABEL: t3:
; X64: pextrw $5, %xmm0, %eax
; X64: pshuflw $44, %xmm0, %xmm0
; X64: pshufhw $27, %xmm0, %xmm0
define <8 x i16> @t4(<8 x i16> %A, <8 x i16> %B) nounwind {
%tmp = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 0, i32 7, i32 2, i32 3, i32 1, i32 5, i32 6, i32 5 >
ret <8 x i16> %tmp
-; X64: t4:
+; X64-LABEL: t4:
; X64: pextrw $7, [[XMM0:%xmm[0-9]+]], %eax
; X64: pshufhw $100, [[XMM0]], [[XMM1:%xmm[0-9]+]]
; X64: pinsrw $1, %eax, [[XMM1]]
%tmp7 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 1, i32 8, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef , i32 undef >
ret <8 x i16> %tmp7
-; X64: t11:
+; X64-LABEL: t11:
; X64: movd %xmm1, %eax
; X64: movlhps %xmm0, %xmm0
; X64: pshuflw $1, %xmm0, %xmm0
%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 0, i32 1, i32 undef, i32 undef, i32 3, i32 11, i32 undef , i32 undef >
ret <8 x i16> %tmp9
-; X64: t12:
+; X64-LABEL: t12:
; X64: pextrw $3, %xmm1, %eax
; X64: movlhps %xmm0, %xmm0
; X64: pshufhw $3, %xmm0, %xmm0
entry:
%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 11, i32 3, i32 undef , i32 undef >
ret <8 x i16> %tmp9
-; X64: t13:
+; X64-LABEL: t13:
; X64: punpcklqdq %xmm0, %xmm1
; X64: pextrw $3, %xmm1, %eax
; X64: pshufd $52, %xmm1, %xmm0
entry:
%tmp9 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> < i32 8, i32 9, i32 undef, i32 undef, i32 undef, i32 2, i32 undef , i32 undef >
ret <8 x i16> %tmp9
-; X64: t14:
+; X64-LABEL: t14:
; X64: punpcklqdq %xmm0, %xmm1
; X64: pshufhw $8, %xmm1, %xmm0
; X64: ret
; rdar://8520311
define <4 x i32> @t17() nounwind {
entry:
-; X64: t17:
+; X64-LABEL: t17:
; X64: movddup (%rax), %xmm0
%tmp1 = load <4 x float>* undef, align 16
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
define <4 x i32> @pinsrd_1(i32 %s, <4 x i32> %tmp) nounwind {
%tmp1 = insertelement <4 x i32> %tmp, i32 %s, i32 1
ret <4 x i32> %tmp1
-; X32: pinsrd_1:
+; X32-LABEL: pinsrd_1:
; X32: pinsrd $1, 4(%esp), %xmm0
-; X64: pinsrd_1:
+; X64-LABEL: pinsrd_1:
; X64: pinsrd $1, %edi, %xmm0
}
define <16 x i8> @pinsrb_1(i8 %s, <16 x i8> %tmp) nounwind {
%tmp1 = insertelement <16 x i8> %tmp, i8 %s, i32 1
ret <16 x i8> %tmp1
-; X32: pinsrb_1:
+; X32-LABEL: pinsrb_1:
; X32: pinsrb $1, 4(%esp), %xmm0
-; X64: pinsrb_1:
+; X64-LABEL: pinsrb_1:
; X64: pinsrb $1, %edi, %xmm0
}
%tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
%tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
ret <2 x float> %tmp9
-; X32: buildvector:
+; X32-LABEL: buildvector:
; X32-NOT: insertps $0
; X32: insertps $16
; X32-NOT: insertps $0
; X32: ret
-; X64: buildvector:
+; X64-LABEL: buildvector:
; X64-NOT: insertps $0
; X64: insertps $16
; X64-NOT: insertps $0
; destination of rsqrtss are the same.
define void @t1(<4 x float> %a) nounwind uwtable ssp {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: rsqrtss %xmm0, %xmm0
%0 = tail call <4 x float> @llvm.x86.sse.rsqrt.ss(<4 x float> %a) nounwind
%a.addr.0.extract = extractelement <4 x float> %0, i32 0
define void @t2(<4 x float> %a) nounwind uwtable ssp {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: rcpss %xmm0, %xmm0
%0 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %a) nounwind
%a.addr.0.extract = extractelement <4 x float> %0, i32 0
; Requires no protector.
define void @test1a(i8* %a) nounwind uwtable {
entry:
-; LINUX-I386: test1a:
+; LINUX-I386-LABEL: test1a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test1a:
+; LINUX-X64-LABEL: test1a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test1a:
+; LINUX-KERNEL-X64-LABEL: test1a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test1a:
+; DARWIN-X64-LABEL: test1a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test1b(i8* %a) nounwind uwtable ssp {
entry:
-; LINUX-I386: test1b:
+; LINUX-I386-LABEL: test1b:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test1b:
+; LINUX-X64-LABEL: test1b:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test1b:
+; LINUX-KERNEL-X64-LABEL: test1b:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test1b:
+; DARWIN-X64-LABEL: test1b:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
-; OPENBSD-AMD64: test1b:
+; OPENBSD-AMD64-LABEL: test1b:
; OPENBSD-AMD64: movq __guard_local(%rip)
; OPENBSD-AMD64: callq __stack_smash_handler
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test1c(i8* %a) nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test1c:
+; LINUX-I386-LABEL: test1c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test1c:
+; LINUX-X64-LABEL: test1c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test1c:
+; LINUX-KERNEL-X64-LABEL: test1c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test1c:
+; DARWIN-X64-LABEL: test1c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test1d(i8* %a) nounwind uwtable sspreq {
entry:
-; LINUX-I386: test1d:
+; LINUX-I386-LABEL: test1d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test1d:
+; LINUX-X64-LABEL: test1d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test1d:
+; LINUX-KERNEL-X64-LABEL: test1d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test1d:
+; DARWIN-X64-LABEL: test1d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test2a(i8* %a) nounwind uwtable {
entry:
-; LINUX-I386: test2a:
+; LINUX-I386-LABEL: test2a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test2a:
+; LINUX-X64-LABEL: test2a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test2a:
+; LINUX-KERNEL-X64-LABEL: test2a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test2a:
+; DARWIN-X64-LABEL: test2a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test2b(i8* %a) nounwind uwtable ssp {
entry:
-; LINUX-I386: test2b:
+; LINUX-I386-LABEL: test2b:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test2b:
+; LINUX-X64-LABEL: test2b:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test2b:
+; LINUX-KERNEL-X64-LABEL: test2b:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test2b:
+; DARWIN-X64-LABEL: test2b:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test2c(i8* %a) nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test2c:
+; LINUX-I386-LABEL: test2c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test2c:
+; LINUX-X64-LABEL: test2c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test2c:
+; LINUX-KERNEL-X64-LABEL: test2c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test2c:
+; DARWIN-X64-LABEL: test2c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test2d(i8* %a) nounwind uwtable sspreq {
entry:
-; LINUX-I386: test2d:
+; LINUX-I386-LABEL: test2d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test2d:
+; LINUX-X64-LABEL: test2d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test2d:
+; LINUX-KERNEL-X64-LABEL: test2d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test2d:
+; DARWIN-X64-LABEL: test2d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test3a(i8* %a) nounwind uwtable {
entry:
-; LINUX-I386: test3a:
+; LINUX-I386-LABEL: test3a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test3a:
+; LINUX-X64-LABEL: test3a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test3a:
+; LINUX-KERNEL-X64-LABEL: test3a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test3a:
+; DARWIN-X64-LABEL: test3a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test3b(i8* %a) nounwind uwtable ssp {
entry:
-; LINUX-I386: test3b:
+; LINUX-I386-LABEL: test3b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test3b:
+; LINUX-X64-LABEL: test3b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test3b:
+; LINUX-KERNEL-X64-LABEL: test3b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test3b:
+; DARWIN-X64-LABEL: test3b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test3c(i8* %a) nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test3c:
+; LINUX-I386-LABEL: test3c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test3c:
+; LINUX-X64-LABEL: test3c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test3c:
+; LINUX-KERNEL-X64-LABEL: test3c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test3c:
+; DARWIN-X64-LABEL: test3c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test3d(i8* %a) nounwind uwtable sspreq {
entry:
-; LINUX-I386: test3d:
+; LINUX-I386-LABEL: test3d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test3d:
+; LINUX-X64-LABEL: test3d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test3d:
+; LINUX-KERNEL-X64-LABEL: test3d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test3d:
+; DARWIN-X64-LABEL: test3d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test4a(i8* %a) nounwind uwtable {
entry:
-; LINUX-I386: test4a:
+; LINUX-I386-LABEL: test4a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test4a:
+; LINUX-X64-LABEL: test4a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test4a:
+; LINUX-KERNEL-X64-LABEL: test4a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test4a:
+; DARWIN-X64-LABEL: test4a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test4b(i8* %a) nounwind uwtable ssp {
entry:
-; LINUX-I386: test4b:
+; LINUX-I386-LABEL: test4b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test4b:
+; LINUX-X64-LABEL: test4b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test4b:
+; LINUX-KERNEL-X64-LABEL: test4b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test4b:
+; DARWIN-X64-LABEL: test4b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test4c(i8* %a) nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test4c:
+; LINUX-I386-LABEL: test4c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test4c:
+; LINUX-X64-LABEL: test4c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test4c:
+; LINUX-KERNEL-X64-LABEL: test4c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test4c:
+; DARWIN-X64-LABEL: test4c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test4d(i8* %a) nounwind uwtable sspreq {
entry:
-; LINUX-I386: test4d:
+; LINUX-I386-LABEL: test4d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test4d:
+; LINUX-X64-LABEL: test4d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test4d:
+; LINUX-KERNEL-X64-LABEL: test4d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test4d:
+; DARWIN-X64-LABEL: test4d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test5a(i8* %a) nounwind uwtable {
entry:
-; LINUX-I386: test5a:
+; LINUX-I386-LABEL: test5a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test5a:
+; LINUX-X64-LABEL: test5a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test5a:
+; LINUX-KERNEL-X64-LABEL: test5a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test5a:
+; DARWIN-X64-LABEL: test5a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test5b(i8* %a) nounwind uwtable ssp {
entry:
-; LINUX-I386: test5b:
+; LINUX-I386-LABEL: test5b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test5b:
+; LINUX-X64-LABEL: test5b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test5b:
+; LINUX-KERNEL-X64-LABEL: test5b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test5b:
+; DARWIN-X64-LABEL: test5b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test5c(i8* %a) nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test5c:
+; LINUX-I386-LABEL: test5c:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test5c:
+; LINUX-X64-LABEL: test5c:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test5c:
+; LINUX-KERNEL-X64-LABEL: test5c:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test5c:
+; DARWIN-X64-LABEL: test5c:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a.addr = alloca i8*, align 8
; Requires protector.
define void @test5d(i8* %a) nounwind uwtable sspreq {
entry:
-; LINUX-I386: test5d:
+; LINUX-I386-LABEL: test5d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test5d:
+; LINUX-X64-LABEL: test5d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test5d:
+; LINUX-KERNEL-X64-LABEL: test5d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test5d:
+; DARWIN-X64-LABEL: test5d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a.addr = alloca i8*, align 8
; Requires no protector.
define void @test6a() nounwind uwtable {
entry:
-; LINUX-I386: test6a:
+; LINUX-I386-LABEL: test6a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test6a:
+; LINUX-X64-LABEL: test6a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test6a:
+; LINUX-KERNEL-X64-LABEL: test6a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test6a:
+; DARWIN-X64-LABEL: test6a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%retval = alloca i32, align 4
; Requires no protector.
define void @test6b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test6b:
+; LINUX-I386-LABEL: test6b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test6b:
+; LINUX-X64-LABEL: test6b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test6b:
+; LINUX-KERNEL-X64-LABEL: test6b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test6b:
+; DARWIN-X64-LABEL: test6b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%retval = alloca i32, align 4
; Requires protector.
define void @test6c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test6c:
+; LINUX-I386-LABEL: test6c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test6c:
+; LINUX-X64-LABEL: test6c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test6c:
+; LINUX-KERNEL-X64-LABEL: test6c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test6c:
+; DARWIN-X64-LABEL: test6c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%retval = alloca i32, align 4
; Requires protector.
define void @test6d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test6d:
+; LINUX-I386-LABEL: test6d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test6d:
+; LINUX-X64-LABEL: test6d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test6d:
+; LINUX-KERNEL-X64-LABEL: test6d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test6d:
+; DARWIN-X64-LABEL: test6d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%retval = alloca i32, align 4
; Requires no protector.
define void @test7a() nounwind uwtable readnone {
entry:
-; LINUX-I386: test7a:
+; LINUX-I386-LABEL: test7a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test7a:
+; LINUX-X64-LABEL: test7a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test7a:
+; LINUX-KERNEL-X64-LABEL: test7a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test7a:
+; DARWIN-X64-LABEL: test7a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires no protector.
define void @test7b() nounwind uwtable readnone ssp {
entry:
-; LINUX-I386: test7b:
+; LINUX-I386-LABEL: test7b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test7b:
+; LINUX-X64-LABEL: test7b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test7b:
+; LINUX-KERNEL-X64-LABEL: test7b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test7b:
+; DARWIN-X64-LABEL: test7b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires protector.
define void @test7c() nounwind uwtable readnone sspstrong {
entry:
-; LINUX-I386: test7c:
+; LINUX-I386-LABEL: test7c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test7c:
+; LINUX-X64-LABEL: test7c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test7c:
+; LINUX-KERNEL-X64-LABEL: test7c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test7c:
+; DARWIN-X64-LABEL: test7c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires protector.
define void @test7d() nounwind uwtable readnone sspreq {
entry:
-; LINUX-I386: test7d:
+; LINUX-I386-LABEL: test7d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test7d:
+; LINUX-X64-LABEL: test7d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test7d:
+; LINUX-KERNEL-X64-LABEL: test7d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test7d:
+; DARWIN-X64-LABEL: test7d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires no protector.
define void @test8a() nounwind uwtable {
entry:
-; LINUX-I386: test8a:
+; LINUX-I386-LABEL: test8a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test8a:
+; LINUX-X64-LABEL: test8a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test8a:
+; LINUX-KERNEL-X64-LABEL: test8a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test8a:
+; DARWIN-X64-LABEL: test8a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%b = alloca i32, align 4
; Requires no protector.
define void @test8b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test8b:
+; LINUX-I386-LABEL: test8b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test8b:
+; LINUX-X64-LABEL: test8b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test8b:
+; LINUX-KERNEL-X64-LABEL: test8b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test8b:
+; DARWIN-X64-LABEL: test8b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%b = alloca i32, align 4
; Requires protector.
define void @test8c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test8c:
+; LINUX-I386-LABEL: test8c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test8c:
+; LINUX-X64-LABEL: test8c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test8c:
+; LINUX-KERNEL-X64-LABEL: test8c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test8c:
+; DARWIN-X64-LABEL: test8c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%b = alloca i32, align 4
; Requires protector.
define void @test8d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test8d:
+; LINUX-I386-LABEL: test8d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test8d:
+; LINUX-X64-LABEL: test8d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test8d:
+; LINUX-KERNEL-X64-LABEL: test8d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test8d:
+; DARWIN-X64-LABEL: test8d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%b = alloca i32, align 4
; Requires no protector.
define void @test9a() nounwind uwtable {
entry:
-; LINUX-I386: test9a:
+; LINUX-I386-LABEL: test9a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test9a:
+; LINUX-X64-LABEL: test9a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test9a:
+; LINUX-KERNEL-X64-LABEL: test9a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test9a:
+; DARWIN-X64-LABEL: test9a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%x = alloca double, align 8
; Requires no protector.
define void @test9b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test9b:
+; LINUX-I386-LABEL: test9b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test9b:
+; LINUX-X64-LABEL: test9b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test9b:
+; LINUX-KERNEL-X64-LABEL: test9b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test9b:
+; DARWIN-X64-LABEL: test9b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%x = alloca double, align 8
; Requires protector.
define void @test9c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test9c:
+; LINUX-I386-LABEL: test9c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test9c:
+; LINUX-X64-LABEL: test9c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test9c:
+; LINUX-KERNEL-X64-LABEL: test9c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test9c:
+; DARWIN-X64-LABEL: test9c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%x = alloca double, align 8
; Requires protector.
define void @test9d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test9d:
+; LINUX-I386-LABEL: test9d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test9d:
+; LINUX-X64-LABEL: test9d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test9d:
+; LINUX-KERNEL-X64-LABEL: test9d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test9d:
+; DARWIN-X64-LABEL: test9d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%x = alloca double, align 8
; Requires no protector.
define void @test10a() nounwind uwtable {
entry:
-; LINUX-I386: test10a:
+; LINUX-I386-LABEL: test10a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test10a:
+; LINUX-X64-LABEL: test10a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test10a:
+; LINUX-KERNEL-X64-LABEL: test10a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test10a:
+; DARWIN-X64-LABEL: test10a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%x = alloca double, align 8
; Requires no protector.
define void @test10b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test10b:
+; LINUX-I386-LABEL: test10b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test10b:
+; LINUX-X64-LABEL: test10b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test10b:
+; LINUX-KERNEL-X64-LABEL: test10b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test10b:
+; DARWIN-X64-LABEL: test10b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%x = alloca double, align 8
; Requires protector.
define void @test10c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test10c:
+; LINUX-I386-LABEL: test10c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test10c:
+; LINUX-X64-LABEL: test10c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test10c:
+; LINUX-KERNEL-X64-LABEL: test10c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test10c:
+; DARWIN-X64-LABEL: test10c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%x = alloca double, align 8
; Requires protector.
define void @test10d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test10d:
+; LINUX-I386-LABEL: test10d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test10d:
+; LINUX-X64-LABEL: test10d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test10d:
+; LINUX-KERNEL-X64-LABEL: test10d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test10d:
+; DARWIN-X64-LABEL: test10d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%x = alloca double, align 8
; Requires no protector.
define void @test11a() nounwind uwtable {
entry:
-; LINUX-I386: test11a:
+; LINUX-I386-LABEL: test11a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test11a:
+; LINUX-X64-LABEL: test11a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test11a:
+; LINUX-KERNEL-X64-LABEL: test11a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test11a:
+; DARWIN-X64-LABEL: test11a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.pair, align 4
; Requires no protector.
define void @test11b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test11b:
+; LINUX-I386-LABEL: test11b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test11b:
+; LINUX-X64-LABEL: test11b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test11b:
+; LINUX-KERNEL-X64-LABEL: test11b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test11b:
+; DARWIN-X64-LABEL: test11b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.pair, align 4
; Requires protector.
define void @test11c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test11c:
+; LINUX-I386-LABEL: test11c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test11c:
+; LINUX-X64-LABEL: test11c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test11c:
+; LINUX-KERNEL-X64-LABEL: test11c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test11c:
+; DARWIN-X64-LABEL: test11c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.pair, align 4
; Requires protector.
define void @test11d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test11d:
+; LINUX-I386-LABEL: test11d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test11d:
+; LINUX-X64-LABEL: test11d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test11d:
+; LINUX-KERNEL-X64-LABEL: test11d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test11d:
+; DARWIN-X64-LABEL: test11d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.pair, align 4
; Requires no protector.
define void @test12a() nounwind uwtable {
entry:
-; LINUX-I386: test12a:
+; LINUX-I386-LABEL: test12a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test12a:
+; LINUX-X64-LABEL: test12a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test12a:
+; LINUX-KERNEL-X64-LABEL: test12a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test12a:
+; DARWIN-X64-LABEL: test12a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.pair, align 4
; Requires no protector.
define void @test12b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test12b:
+; LINUX-I386-LABEL: test12b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test12b:
+; LINUX-X64-LABEL: test12b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test12b:
+; LINUX-KERNEL-X64-LABEL: test12b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test12b:
+; DARWIN-X64-LABEL: test12b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.pair, align 4
; Requires protector.
define void @test12c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test12c:
+; LINUX-I386-LABEL: test12c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test12c:
+; LINUX-X64-LABEL: test12c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test12c:
+; LINUX-KERNEL-X64-LABEL: test12c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test12c:
+; DARWIN-X64-LABEL: test12c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.pair, align 4
; Requires protector.
define void @test12d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test12d:
+; LINUX-I386-LABEL: test12d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test12d:
+; LINUX-X64-LABEL: test12d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test12d:
+; LINUX-KERNEL-X64-LABEL: test12d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test12d:
+; DARWIN-X64-LABEL: test12d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.pair, align 4
; Requires no protector.
define void @test13a() nounwind uwtable {
entry:
-; LINUX-I386: test13a:
+; LINUX-I386-LABEL: test13a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test13a:
+; LINUX-X64-LABEL: test13a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test13a:
+; LINUX-KERNEL-X64-LABEL: test13a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test13a:
+; DARWIN-X64-LABEL: test13a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.pair, align 4
; Requires no protector.
define void @test13b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test13b:
+; LINUX-I386-LABEL: test13b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test13b:
+; LINUX-X64-LABEL: test13b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test13b:
+; LINUX-KERNEL-X64-LABEL: test13b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test13b:
+; DARWIN-X64-LABEL: test13b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.pair, align 4
; Requires protector.
define void @test13c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test13c:
+; LINUX-I386-LABEL: test13c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test13c:
+; LINUX-X64-LABEL: test13c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test13c:
+; LINUX-KERNEL-X64-LABEL: test13c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test13c:
+; DARWIN-X64-LABEL: test13c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.pair, align 4
; Requires protector.
define void @test13d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test13d:
+; LINUX-I386-LABEL: test13d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test13d:
+; LINUX-X64-LABEL: test13d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test13d:
+; LINUX-KERNEL-X64-LABEL: test13d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test13d:
+; DARWIN-X64-LABEL: test13d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.pair, align 4
; Requires no protector.
define void @test14a() nounwind uwtable {
entry:
-; LINUX-I386: test14a:
+; LINUX-I386-LABEL: test14a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test14a:
+; LINUX-X64-LABEL: test14a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test14a:
+; LINUX-KERNEL-X64-LABEL: test14a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test14a:
+; DARWIN-X64-LABEL: test14a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires no protector.
define void @test14b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test14b:
+; LINUX-I386-LABEL: test14b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test14b:
+; LINUX-X64-LABEL: test14b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test14b:
+; LINUX-KERNEL-X64-LABEL: test14b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test14b:
+; DARWIN-X64-LABEL: test14b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires protector.
define void @test14c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test14c:
+; LINUX-I386-LABEL: test14c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test14c:
+; LINUX-X64-LABEL: test14c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test14c:
+; LINUX-KERNEL-X64-LABEL: test14c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test14c:
+; DARWIN-X64-LABEL: test14c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires protector.
define void @test14d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test14d:
+; LINUX-I386-LABEL: test14d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test14d:
+; LINUX-X64-LABEL: test14d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test14d:
+; LINUX-KERNEL-X64-LABEL: test14d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test14d:
+; DARWIN-X64-LABEL: test14d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires no protector.
define void @test15a() nounwind uwtable {
entry:
-; LINUX-I386: test15a:
+; LINUX-I386-LABEL: test15a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test15a:
+; LINUX-X64-LABEL: test15a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test15a:
+; LINUX-KERNEL-X64-LABEL: test15a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test15a:
+; DARWIN-X64-LABEL: test15a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires no protector.
define void @test15b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test15b:
+; LINUX-I386-LABEL: test15b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test15b:
+; LINUX-X64-LABEL: test15b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test15b:
+; LINUX-KERNEL-X64-LABEL: test15b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test15b:
+; DARWIN-X64-LABEL: test15b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires protector.
define void @test15c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test15c:
+; LINUX-I386-LABEL: test15c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test15c:
+; LINUX-X64-LABEL: test15c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test15c:
+; LINUX-KERNEL-X64-LABEL: test15c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test15c:
+; DARWIN-X64-LABEL: test15c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires protector.
define void @test15d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test15d:
+; LINUX-I386-LABEL: test15d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test15d:
+; LINUX-X64-LABEL: test15d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test15d:
+; LINUX-KERNEL-X64-LABEL: test15d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test15d:
+; DARWIN-X64-LABEL: test15d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires no protector.
define void @test16a() nounwind uwtable {
entry:
-; LINUX-I386: test16a:
+; LINUX-I386-LABEL: test16a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test16a:
+; LINUX-X64-LABEL: test16a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test16a:
+; LINUX-KERNEL-X64-LABEL: test16a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test16a:
+; DARWIN-X64-LABEL: test16a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires no protector.
define void @test16b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test16b:
+; LINUX-I386-LABEL: test16b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test16b:
+; LINUX-X64-LABEL: test16b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test16b:
+; LINUX-KERNEL-X64-LABEL: test16b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test16b:
+; DARWIN-X64-LABEL: test16b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires protector.
define void @test16c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test16c:
+; LINUX-I386-LABEL: test16c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test16c:
+; LINUX-X64-LABEL: test16c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test16c:
+; LINUX-KERNEL-X64-LABEL: test16c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test16c:
+; DARWIN-X64-LABEL: test16c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires protector.
define void @test16d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test16d:
+; LINUX-I386-LABEL: test16d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test16d:
+; LINUX-X64-LABEL: test16d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test16d:
+; LINUX-KERNEL-X64-LABEL: test16d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test16d:
+; DARWIN-X64-LABEL: test16d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires no protector.
define void @test17a() nounwind uwtable {
entry:
-; LINUX-I386: test17a:
+; LINUX-I386-LABEL: test17a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test17a:
+; LINUX-X64-LABEL: test17a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test17a:
+; LINUX-KERNEL-X64-LABEL: test17a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test17a:
+; DARWIN-X64-LABEL: test17a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.vec, align 16
; Requires no protector.
define void @test17b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test17b:
+; LINUX-I386-LABEL: test17b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test17b:
+; LINUX-X64-LABEL: test17b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test17b:
+; LINUX-KERNEL-X64-LABEL: test17b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test17b:
+; DARWIN-X64-LABEL: test17b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.vec, align 16
; Requires protector.
define void @test17c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test17c:
+; LINUX-I386-LABEL: test17c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test17c:
+; LINUX-X64-LABEL: test17c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test17c:
+; LINUX-KERNEL-X64-LABEL: test17c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test17c:
+; DARWIN-X64-LABEL: test17c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.vec, align 16
; Requires protector.
define void @test17d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test17d:
+; LINUX-I386-LABEL: test17d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test17d:
+; LINUX-X64-LABEL: test17d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test17d:
+; LINUX-KERNEL-X64-LABEL: test17d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test17d:
+; DARWIN-X64-LABEL: test17d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.vec, align 16
; Requires no protector.
define i32 @test18a() uwtable {
entry:
-; LINUX-I386: test18a:
+; LINUX-I386-LABEL: test18a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test18a:
+; LINUX-X64-LABEL: test18a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test18a:
+; LINUX-KERNEL-X64-LABEL: test18a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test18a:
+; DARWIN-X64-LABEL: test18a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires no protector.
define i32 @test18b() uwtable ssp {
entry:
-; LINUX-I386: test18b:
+; LINUX-I386-LABEL: test18b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test18b:
+; LINUX-X64-LABEL: test18b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test18b:
+; LINUX-KERNEL-X64-LABEL: test18b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test18b:
+; DARWIN-X64-LABEL: test18b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32, align 4
; Requires protector.
define i32 @test18c() uwtable sspstrong {
entry:
-; LINUX-I386: test18c:
+; LINUX-I386-LABEL: test18c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test18c:
+; LINUX-X64-LABEL: test18c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test18c:
+; LINUX-KERNEL-X64-LABEL: test18c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test18c:
+; DARWIN-X64-LABEL: test18c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires protector.
define i32 @test18d() uwtable sspreq {
entry:
-; LINUX-I386: test18d:
+; LINUX-I386-LABEL: test18d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test18d:
+; LINUX-X64-LABEL: test18d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test18d:
+; LINUX-KERNEL-X64-LABEL: test18d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test18d:
+; DARWIN-X64-LABEL: test18d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32, align 4
; Requires no protector.
define i32 @test19a() uwtable {
entry:
-; LINUX-I386: test19a:
+; LINUX-I386-LABEL: test19a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test19a:
+; LINUX-X64-LABEL: test19a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test19a:
+; LINUX-KERNEL-X64-LABEL: test19a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test19a:
+; DARWIN-X64-LABEL: test19a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.pair, align 4
; Requires no protector.
define i32 @test19b() uwtable ssp {
entry:
-; LINUX-I386: test19b:
+; LINUX-I386-LABEL: test19b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test19b:
+; LINUX-X64-LABEL: test19b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test19b:
+; LINUX-KERNEL-X64-LABEL: test19b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test19b:
+; DARWIN-X64-LABEL: test19b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.pair, align 4
; Requires protector.
define i32 @test19c() uwtable sspstrong {
entry:
-; LINUX-I386: test19c:
+; LINUX-I386-LABEL: test19c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test19c:
+; LINUX-X64-LABEL: test19c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test19c:
+; LINUX-KERNEL-X64-LABEL: test19c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test19c:
+; DARWIN-X64-LABEL: test19c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.pair, align 4
; Requires protector.
define i32 @test19d() uwtable sspreq {
entry:
-; LINUX-I386: test19d:
+; LINUX-I386-LABEL: test19d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test19d:
+; LINUX-X64-LABEL: test19d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test19d:
+; LINUX-KERNEL-X64-LABEL: test19d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test19d:
+; DARWIN-X64-LABEL: test19d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%c = alloca %struct.pair, align 4
; Requires no protector.
define void @test20a() nounwind uwtable {
entry:
-; LINUX-I386: test20a:
+; LINUX-I386-LABEL: test20a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test20a:
+; LINUX-X64-LABEL: test20a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test20a:
+; LINUX-KERNEL-X64-LABEL: test20a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test20a:
+; DARWIN-X64-LABEL: test20a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32*, align 8
; Requires no protector.
define void @test20b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test20b:
+; LINUX-I386-LABEL: test20b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test20b:
+; LINUX-X64-LABEL: test20b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test20b:
+; LINUX-KERNEL-X64-LABEL: test20b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test20b:
+; DARWIN-X64-LABEL: test20b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32*, align 8
; Requires protector.
define void @test20c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test20c:
+; LINUX-I386-LABEL: test20c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test20c:
+; LINUX-X64-LABEL: test20c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test20c:
+; LINUX-KERNEL-X64-LABEL: test20c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test20c:
+; DARWIN-X64-LABEL: test20c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32*, align 8
; Requires protector.
define void @test20d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test20d:
+; LINUX-I386-LABEL: test20d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test20d:
+; LINUX-X64-LABEL: test20d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test20d:
+; LINUX-KERNEL-X64-LABEL: test20d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test20d:
+; DARWIN-X64-LABEL: test20d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32*, align 8
; Requires no protector.
define void @test21a() nounwind uwtable {
entry:
-; LINUX-I386: test21a:
+; LINUX-I386-LABEL: test21a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test21a:
+; LINUX-X64-LABEL: test21a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test21a:
+; LINUX-KERNEL-X64-LABEL: test21a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test21a:
+; DARWIN-X64-LABEL: test21a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32*, align 8
; Requires no protector.
define void @test21b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test21b:
+; LINUX-I386-LABEL: test21b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test21b:
+; LINUX-X64-LABEL: test21b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test21b:
+; LINUX-KERNEL-X64-LABEL: test21b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test21b:
+; DARWIN-X64-LABEL: test21b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca i32*, align 8
; Requires protector.
define void @test21c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test21c:
+; LINUX-I386-LABEL: test21c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test21c:
+; LINUX-X64-LABEL: test21c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test21c:
+; LINUX-KERNEL-X64-LABEL: test21c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test21c:
+; DARWIN-X64-LABEL: test21c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32*, align 8
; Requires protector.
define void @test21d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test21d:
+; LINUX-I386-LABEL: test21d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test21d:
+; LINUX-X64-LABEL: test21d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test21d:
+; LINUX-KERNEL-X64-LABEL: test21d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test21d:
+; DARWIN-X64-LABEL: test21d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca i32*, align 8
; Requires no protector.
define signext i8 @test22a() nounwind uwtable {
entry:
-; LINUX-I386: test22a:
+; LINUX-I386-LABEL: test22a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test22a:
+; LINUX-X64-LABEL: test22a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test22a:
+; LINUX-KERNEL-X64-LABEL: test22a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test22a:
+; DARWIN-X64-LABEL: test22a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca %class.A, align 1
; Requires no protector.
define signext i8 @test22b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test22b:
+; LINUX-I386-LABEL: test22b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test22b:
+; LINUX-X64-LABEL: test22b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test22b:
+; LINUX-KERNEL-X64-LABEL: test22b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test22b:
+; DARWIN-X64-LABEL: test22b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca %class.A, align 1
; Requires protector.
define signext i8 @test22c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test22c:
+; LINUX-I386-LABEL: test22c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test22c:
+; LINUX-X64-LABEL: test22c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test22c:
+; LINUX-KERNEL-X64-LABEL: test22c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test22c:
+; DARWIN-X64-LABEL: test22c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca %class.A, align 1
; Requires protector.
define signext i8 @test22d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test22d:
+; LINUX-I386-LABEL: test22d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test22d:
+; LINUX-X64-LABEL: test22d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test22d:
+; LINUX-KERNEL-X64-LABEL: test22d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test22d:
+; DARWIN-X64-LABEL: test22d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca %class.A, align 1
; Requires no protector.
define signext i8 @test23a() nounwind uwtable {
entry:
-; LINUX-I386: test23a:
+; LINUX-I386-LABEL: test23a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test23a:
+; LINUX-X64-LABEL: test23a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test23a:
+; LINUX-KERNEL-X64-LABEL: test23a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test23a:
+; DARWIN-X64-LABEL: test23a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%x = alloca %struct.deep, align 1
; Requires no protector.
define signext i8 @test23b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test23b:
+; LINUX-I386-LABEL: test23b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test23b:
+; LINUX-X64-LABEL: test23b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test23b:
+; LINUX-KERNEL-X64-LABEL: test23b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test23b:
+; DARWIN-X64-LABEL: test23b:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%x = alloca %struct.deep, align 1
; Requires protector.
define signext i8 @test23c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test23c:
+; LINUX-I386-LABEL: test23c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test23c:
+; LINUX-X64-LABEL: test23c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test23c:
+; LINUX-KERNEL-X64-LABEL: test23c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test23c:
+; DARWIN-X64-LABEL: test23c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%x = alloca %struct.deep, align 1
; Requires protector.
define signext i8 @test23d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test23d:
+; LINUX-I386-LABEL: test23d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test23d:
+; LINUX-X64-LABEL: test23d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test23d:
+; LINUX-KERNEL-X64-LABEL: test23d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test23d:
+; DARWIN-X64-LABEL: test23d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%x = alloca %struct.deep, align 1
; Requires no protector.
define void @test24a(i32 %n) nounwind uwtable {
entry:
-; LINUX-I386: test24a:
+; LINUX-I386-LABEL: test24a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test24a:
+; LINUX-X64-LABEL: test24a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test24a:
+; LINUX-KERNEL-X64-LABEL: test24a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test24a:
+; DARWIN-X64-LABEL: test24a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%n.addr = alloca i32, align 4
; Requires protector.
define void @test24b(i32 %n) nounwind uwtable ssp {
entry:
-; LINUX-I386: test24b:
+; LINUX-I386-LABEL: test24b:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test24b:
+; LINUX-X64-LABEL: test24b:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test24b:
+; LINUX-KERNEL-X64-LABEL: test24b:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test24b:
+; DARWIN-X64-LABEL: test24b:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%n.addr = alloca i32, align 4
; Requires protector.
define void @test24c(i32 %n) nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test24c:
+; LINUX-I386-LABEL: test24c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test24c:
+; LINUX-X64-LABEL: test24c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test24c:
+; LINUX-KERNEL-X64-LABEL: test24c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test24c:
+; DARWIN-X64-LABEL: test24c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%n.addr = alloca i32, align 4
; Requires protector.
define void @test24d(i32 %n) nounwind uwtable sspreq {
entry:
-; LINUX-I386: test24d:
+; LINUX-I386-LABEL: test24d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test24d:
+; LINUX-X64-LABEL: test24d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test24d:
+; LINUX-KERNEL-X64-LABEL: test24d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test24d:
+; DARWIN-X64-LABEL: test24d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%n.addr = alloca i32, align 4
; Requires no protector.
define i32 @test25a() nounwind uwtable {
entry:
-; LINUX-I386: test25a:
+; LINUX-I386-LABEL: test25a:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test25a:
+; LINUX-X64-LABEL: test25a:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test25a:
+; LINUX-KERNEL-X64-LABEL: test25a:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test25a:
+; DARWIN-X64-LABEL: test25a:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%a = alloca [4 x i32], align 16
; Requires no protector, except for Darwin which _does_ require a protector.
define i32 @test25b() nounwind uwtable ssp {
entry:
-; LINUX-I386: test25b:
+; LINUX-I386-LABEL: test25b:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test25b:
+; LINUX-X64-LABEL: test25b:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test25b:
+; LINUX-KERNEL-X64-LABEL: test25b:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test25b:
+; DARWIN-X64-LABEL: test25b:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca [4 x i32], align 16
; Requires protector.
define i32 @test25c() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test25c:
+; LINUX-I386-LABEL: test25c:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test25c:
+; LINUX-X64-LABEL: test25c:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test25c:
+; LINUX-KERNEL-X64-LABEL: test25c:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test25c:
+; DARWIN-X64-LABEL: test25c:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca [4 x i32], align 16
; Requires protector.
define i32 @test25d() nounwind uwtable sspreq {
entry:
-; LINUX-I386: test25d:
+; LINUX-I386-LABEL: test25d:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test25d:
+; LINUX-X64-LABEL: test25d:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test25d:
+; LINUX-KERNEL-X64-LABEL: test25d:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test25d:
+; DARWIN-X64-LABEL: test25d:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%a = alloca [4 x i32], align 16
; Requires no protector.
define void @test26() nounwind uwtable sspstrong {
entry:
-; LINUX-I386: test26:
+; LINUX-I386-LABEL: test26:
; LINUX-I386-NOT: calll __stack_chk_fail
; LINUX-I386: .cfi_endproc
-; LINUX-X64: test26:
+; LINUX-X64-LABEL: test26:
; LINUX-X64-NOT: callq __stack_chk_fail
; LINUX-X64: .cfi_endproc
-; LINUX-KERNEL-X64: test26:
+; LINUX-KERNEL-X64-LABEL: test26:
; LINUX-KERNEL-X64-NOT: callq __stack_chk_fail
; LINUX-KERNEL-X64: .cfi_endproc
-; DARWIN-X64: test26:
+; DARWIN-X64-LABEL: test26:
; DARWIN-X64-NOT: callq ___stack_chk_fail
; DARWIN-X64: .cfi_endproc
%c = alloca %struct.nest, align 4
; Requires protector.
define i32 @test27(i32 %arg) nounwind uwtable sspstrong {
bb:
-; LINUX-I386: test27:
+; LINUX-I386-LABEL: test27:
; LINUX-I386: mov{{l|q}} %gs:
; LINUX-I386: calll __stack_chk_fail
-; LINUX-X64: test27:
+; LINUX-X64-LABEL: test27:
; LINUX-X64: mov{{l|q}} %fs:
; LINUX-X64: callq __stack_chk_fail
-; LINUX-KERNEL-X64: test27:
+; LINUX-KERNEL-X64-LABEL: test27:
; LINUX-KERNEL-X64: mov{{l|q}} %gs:
; LINUX-KERNEL-X64: callq __stack_chk_fail
-; DARWIN-X64: test27:
+; DARWIN-X64-LABEL: test27:
; DARWIN-X64: mov{{l|q}} ___stack_chk_guard
; DARWIN-X64: callq ___stack_chk_fail
%tmp = alloca %struct.small*, align 8
%struct.I = type { i32 (...)** }
define x86_stdcallcc void @bar(%struct.I* nocapture %this) ssp align 2 {
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK-NOT: jmp
; CHECK: ret $4
entry:
@X = internal global i16 0 ; <i16*> [#uses=2]
define void @foo() nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK-NOT: mov
; CHECK: add
; CHECK-NEXT: ret
%t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
ret i1 false
-; CHECK: func1:
+; CHECK-LABEL: func1:
; CHECK: subl 20(%esp)
; CHECK-NEXT: jno
}
%t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
ret i1 false
-; CHECK: func2:
+; CHECK-LABEL: func2:
; CHECK: subl 20(%esp)
; CHECK-NEXT: jae
}
%obit = extractvalue {i32, i1} %t, 1
ret i1 %obit
-; CHECK: func3:
+; CHECK-LABEL: func3:
; CHECK: decl
; CHECK-NEXT: seto
}
; BranchFolding should tail-merge the stores since they all precede
; direct branches to the same place.
-; CHECK: tail_merge_me:
+; CHECK-LABEL: tail_merge_me:
; CHECK-NOT: GHJK
; CHECK: movl $0, GHJK(%rip)
; CHECK-NEXT: movl $1, HABC(%rip)
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.
-; CHECK: tail_duplicate_me:
+; CHECK-LABEL: tail_duplicate_me:
; CHECK: movl $0, GHJK(%rip)
; CHECK-NEXT: jmpq *%r
; CHECK: movl $0, GHJK(%rip)
; BranchFolding shouldn't try to merge the tails of two blocks
; with only a branch in common, regardless of the fallthrough situation.
-; CHECK: dont_merge_oddly:
+; CHECK-LABEL: dont_merge_oddly:
; CHECK-NOT: ret
; CHECK: ucomiss %xmm{{[0-2]}}, %xmm{{[0-2]}}
; CHECK-NEXT: jbe .LBB2_3
; Do any-size tail-merging when two candidate blocks will both require
; an unconditional jump to complete a two-way conditional branch.
-; CHECK: c_expand_expr_stmt:
+; CHECK-LABEL: c_expand_expr_stmt:
;
; This test only works when register allocation happens to use %rax for both
; load addresses.
; instructions are involved. This function should have only
; one ret instruction.
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: callq func
; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: popq
; one - One instruction may be tail-duplicated even with optsize.
-; CHECK: one:
+; CHECK-LABEL: one:
; CHECK: movl $0, XYZ(%rip)
; CHECK: movl $0, XYZ(%rip)
; tail instead of one. This is too much to be merged, given
; the optsize attribute.
-; CHECK: two:
+; CHECK-LABEL: two:
; CHECK-NOT: XYZ
; CHECK: ret
; CHECK: movl $0, XYZ(%rip)
; two_nosize - Same as two, but without the optsize attribute.
; Now two instructions are enough to be tail-duplicated.
-; CHECK: two_nosize:
+; CHECK-LABEL: two_nosize:
; CHECK: movl $0, XYZ(%rip)
; CHECK: movl $1, XYZ(%rip)
; CHECK: movl $0, XYZ(%rip)
; Tail-merging should merge the two ret instructions since one side
; can fall-through into the ret and the other side has to branch anyway.
-; CHECK: TESTE:
+; CHECK-LABEL: TESTE:
; CHECK: ret
; CHECK-NOT: ret
; CHECK: size TESTE
; rdar://9147433
define i32 @foo(i32 %x) nounwind ssp {
-; CHECK: foo:
+; CHECK-LABEL: foo:
entry:
switch i32 %x, label %return [
i32 1, label %sw.bb
define hidden %0* @thingWithValue(i8* %self) uwtable ssp {
entry:
-; CHECK: thingWithValue:
+; CHECK-LABEL: thingWithValue:
; CHECK: jmp _bar
br i1 undef, label %if.then.i, label %if.else.i
; FIXME: Win64 does not support byval.
; Expect the entry point.
-; CHECK: tailcaller:
+; CHECK-LABEL: tailcaller:
; Expect 2 rep;movs because of tail call byval lowering.
; CHECK: rep;
declare i32 @putchar(i32)
define fastcc i32 @checktail(i32 %x, i32* %f, i32 %g) nounwind {
-; CHECK: checktail:
+; CHECK-LABEL: checktail:
%tmp1 = icmp sgt i32 %x, 0
br i1 %tmp1, label %if-then, label %if-else
; RUN: llc < %s -mtriple=x86_64-win32 | FileCheck %s --check-prefix=CHECK-64
; RUN: llc < %s -march=x86 | FileCheck %s --check-prefix=CHECK-32
-; CHECK-64: g64xh:
+; CHECK-64-LABEL: g64xh:
; CHECK-64: testb $8, {{%ah|%ch}}
; CHECK-64: ret
-; CHECK-32: g64xh:
+; CHECK-32-LABEL: g64xh:
; CHECK-32: testb $8, %ah
; CHECK-32: ret
define void @g64xh(i64 inreg %x) nounwind {
no:
ret void
}
-; CHECK-64: g64xl:
+; CHECK-64-LABEL: g64xl:
; CHECK-64: testb $8, [[A0L:%dil|%cl]]
; CHECK-64: ret
-; CHECK-32: g64xl:
+; CHECK-32-LABEL: g64xl:
; CHECK-32: testb $8, %al
; CHECK-32: ret
define void @g64xl(i64 inreg %x) nounwind {
no:
ret void
}
-; CHECK-64: g32xh:
+; CHECK-64-LABEL: g32xh:
; CHECK-64: testb $8, {{%ah|%ch}}
; CHECK-64: ret
-; CHECK-32: g32xh:
+; CHECK-32-LABEL: g32xh:
; CHECK-32: testb $8, %ah
; CHECK-32: ret
define void @g32xh(i32 inreg %x) nounwind {
no:
ret void
}
-; CHECK-64: g32xl:
+; CHECK-64-LABEL: g32xl:
; CHECK-64: testb $8, [[A0L]]
; CHECK-64: ret
-; CHECK-32: g32xl:
+; CHECK-32-LABEL: g32xl:
; CHECK-32: testb $8, %al
; CHECK-32: ret
define void @g32xl(i32 inreg %x) nounwind {
no:
ret void
}
-; CHECK-64: g16xh:
+; CHECK-64-LABEL: g16xh:
; CHECK-64: testb $8, {{%ah|%ch}}
; CHECK-64: ret
-; CHECK-32: g16xh:
+; CHECK-32-LABEL: g16xh:
; CHECK-32: testb $8, %ah
; CHECK-32: ret
define void @g16xh(i16 inreg %x) nounwind {
no:
ret void
}
-; CHECK-64: g16xl:
+; CHECK-64-LABEL: g16xl:
; CHECK-64: testb $8, [[A0L]]
; CHECK-64: ret
-; CHECK-32: g16xl:
+; CHECK-32-LABEL: g16xl:
; CHECK-32: testb $8, %al
; CHECK-32: ret
define void @g16xl(i16 inreg %x) nounwind {
no:
ret void
}
-; CHECK-64: g64x16:
+; CHECK-64-LABEL: g64x16:
; CHECK-64: testw $-32640, %[[A0W:di|cx]]
; CHECK-64: ret
-; CHECK-32: g64x16:
+; CHECK-32-LABEL: g64x16:
; CHECK-32: testw $-32640, %ax
; CHECK-32: ret
define void @g64x16(i64 inreg %x) nounwind {
no:
ret void
}
-; CHECK-64: g32x16:
+; CHECK-64-LABEL: g32x16:
; CHECK-64: testw $-32640, %[[A0W]]
; CHECK-64: ret
-; CHECK-32: g32x16:
+; CHECK-32-LABEL: g32x16:
; CHECK-32: testw $-32640, %ax
; CHECK-32: ret
define void @g32x16(i32 inreg %x) nounwind {
no:
ret void
}
-; CHECK-64: g64x32:
+; CHECK-64-LABEL: g64x32:
; CHECK-64: testl $268468352, %e[[A0W]]
; CHECK-64: ret
-; CHECK-32: g64x32:
+; CHECK-32-LABEL: g64x32:
; CHECK-32: testl $268468352, %eax
; CHECK-32: ret
define void @g64x32(i64 inreg %x) nounwind {
ret i32* @x
; FIXME: This function uses a single thread-local variable,
; so we might want to fall back to general-dynamic here.
-; CHECK: get_x:
+; CHECK-LABEL: get_x:
; CHECK: leaq x@TLSLD(%rip), %rdi
; CHECK-NEXT: callq __tls_get_addr@PLT
; CHECK: x@DTPOFF
%cmp = icmp eq i32 %i, 1
br i1 %cmp, label %return, label %if.else
; This bb does not access TLS, so should not call __tls_get_addr.
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK-NOT: __tls_get_addr
; CHECK: je
ret i32* @external_gd
; Non-PIC code can use initial-exec, PIC code has to use general dynamic.
- ; X64: f1:
+ ; X64-LABEL: f1:
; X64: external_gd@GOTTPOFF
- ; X32: f1:
+ ; X32-LABEL: f1:
; X32: external_gd@INDNTPOFF
- ; X64_PIC: f1:
+ ; X64_PIC-LABEL: f1:
; X64_PIC: external_gd@TLSGD
- ; X32_PIC: f1:
+ ; X32_PIC-LABEL: f1:
; X32_PIC: external_gd@TLSGD
- ; DARWIN: f1:
+ ; DARWIN-LABEL: f1:
; DARWIN: _external_gd@TLVP
}
ret i32* @internal_gd
; Non-PIC code can use local exec, PIC code can use local dynamic.
- ; X64: f2:
+ ; X64-LABEL: f2:
; X64: internal_gd@TPOFF
- ; X32: f2:
+ ; X32-LABEL: f2:
; X32: internal_gd@NTPOFF
- ; X64_PIC: f2:
+ ; X64_PIC-LABEL: f2:
; X64_PIC: internal_gd@TLSLD
- ; X32_PIC: f2:
+ ; X32_PIC-LABEL: f2:
; X32_PIC: internal_gd@TLSLDM
- ; DARWIN: f2:
+ ; DARWIN-LABEL: f2:
; DARWIN: _internal_gd@TLVP
}
ret i32* @external_ld
; Non-PIC code can use initial exec, PIC code use local dynamic as specified.
- ; X64: f3:
+ ; X64-LABEL: f3:
; X64: external_ld@GOTTPOFF
- ; X32: f3:
+ ; X32-LABEL: f3:
; X32: external_ld@INDNTPOFF
- ; X64_PIC: f3:
+ ; X64_PIC-LABEL: f3:
; X64_PIC: external_ld@TLSLD
- ; X32_PIC: f3:
+ ; X32_PIC-LABEL: f3:
; X32_PIC: external_ld@TLSLDM
- ; DARWIN: f3:
+ ; DARWIN-LABEL: f3:
; DARWIN: _external_ld@TLVP
}
ret i32* @internal_ld
; Non-PIC code can use local exec, PIC code can use local dynamic.
- ; X64: f4:
+ ; X64-LABEL: f4:
; X64: internal_ld@TPOFF
- ; X32: f4:
+ ; X32-LABEL: f4:
; X32: internal_ld@NTPOFF
- ; X64_PIC: f4:
+ ; X64_PIC-LABEL: f4:
; X64_PIC: internal_ld@TLSLD
- ; X32_PIC: f4:
+ ; X32_PIC-LABEL: f4:
; X32_PIC: internal_ld@TLSLDM
- ; DARWIN: f4:
+ ; DARWIN-LABEL: f4:
; DARWIN: _internal_ld@TLVP
}
ret i32* @external_ie
; Non-PIC and PIC code will use initial exec as specified.
- ; X64: f5:
+ ; X64-LABEL: f5:
; X64: external_ie@GOTTPOFF
- ; X32: f5:
+ ; X32-LABEL: f5:
; X32: external_ie@INDNTPOFF
- ; X64_PIC: f5:
+ ; X64_PIC-LABEL: f5:
; X64_PIC: external_ie@GOTTPOFF
- ; X32_PIC: f5:
+ ; X32_PIC-LABEL: f5:
; X32_PIC: external_ie@GOTNTPOFF
- ; DARWIN: f5:
+ ; DARWIN-LABEL: f5:
; DARWIN: _external_ie@TLVP
}
ret i32* @internal_ie
; Non-PIC code can use local exec, PIC code use initial exec as specified.
- ; X64: f6:
+ ; X64-LABEL: f6:
; X64: internal_ie@TPOFF
- ; X32: f6:
+ ; X32-LABEL: f6:
; X32: internal_ie@NTPOFF
- ; X64_PIC: f6:
+ ; X64_PIC-LABEL: f6:
; X64_PIC: internal_ie@GOTTPOFF
- ; X32_PIC: f6:
+ ; X32_PIC-LABEL: f6:
; X32_PIC: internal_ie@GOTNTPOFF
- ; DARWIN: f6:
+ ; DARWIN-LABEL: f6:
; DARWIN: _internal_ie@TLVP
}
ret i32* @external_le
; Non-PIC and PIC code will use local exec as specified.
- ; X64: f7:
+ ; X64-LABEL: f7:
; X64: external_le@TPOFF
- ; X32: f7:
+ ; X32-LABEL: f7:
; X32: external_le@NTPOFF
- ; X64_PIC: f7:
+ ; X64_PIC-LABEL: f7:
; X64_PIC: external_le@TPOFF
- ; X32_PIC: f7:
+ ; X32_PIC-LABEL: f7:
; X32_PIC: external_le@NTPOFF
- ; DARWIN: f7:
+ ; DARWIN-LABEL: f7:
; DARWIN: _external_le@TLVP
}
ret i32* @internal_le
; Non-PIC and PIC code will use local exec as specified.
- ; X64: f8:
+ ; X64-LABEL: f8:
; X64: internal_le@TPOFF
- ; X32: f8:
+ ; X32-LABEL: f8:
; X32: internal_le@NTPOFF
- ; X64_PIC: f8:
+ ; X64_PIC-LABEL: f8:
; X64_PIC: internal_le@TPOFF
- ; X32_PIC: f8:
+ ; X32_PIC-LABEL: f8:
; X32_PIC: internal_le@NTPOFF
- ; DARWIN: f8:
+ ; DARWIN-LABEL: f8:
; DARWIN: _internal_le@TLVP
}
ret i32 %tmp1
}
-; X32: f1:
+; X32-LABEL: f1:
; X32: leal i@TLSGD(,%ebx), %eax
; X32: calll ___tls_get_addr@PLT
-; X64: f1:
+; X64-LABEL: f1:
; X64: leaq i@TLSGD(%rip), %rdi
; X64: callq __tls_get_addr@PLT
ret i32* @i
}
-; X32: f2:
+; X32-LABEL: f2:
; X32: leal i@TLSGD(,%ebx), %eax
; X32: calll ___tls_get_addr@PLT
-; X64: f2:
+; X64-LABEL: f2:
; X64: leaq i@TLSGD(%rip), %rdi
; X64: callq __tls_get_addr@PLT
ret i32 %tmp1
}
-; X32: f3:
+; X32-LABEL: f3:
; X32: leal i@TLSGD(,%ebx), %eax
; X32: calll ___tls_get_addr@PLT
-; X64: f3:
+; X64-LABEL: f3:
; X64: leaq i@TLSGD(%rip), %rdi
; X64: callq __tls_get_addr@PLT
ret i32* @i
}
-; X32: f4:
+; X32-LABEL: f4:
; X32: leal i@TLSGD(,%ebx), %eax
; X32: calll ___tls_get_addr@PLT
-; X64: f4:
+; X64-LABEL: f4:
; X64: leaq i@TLSGD(%rip), %rdi
; X64: callq __tls_get_addr@PLT
ret i32 %add
}
-; X32: f5:
+; X32-LABEL: f5:
; X32: leal {{[jk]}}@TLSLDM(%ebx)
; X32: calll ___tls_get_addr@PLT
; X32: movl {{[jk]}}@DTPOFF(%e
; X32: addl {{[jk]}}@DTPOFF(%e
-; X64: f5:
+; X64-LABEL: f5:
; X64: leaq {{[jk]}}@TLSLD(%rip), %rdi
; X64: callq __tls_get_addr@PLT
; X64: movl {{[jk]}}@DTPOFF(%r
@i2 = external thread_local global i32
define i32 @f1() {
-; X32: f1:
+; X32-LABEL: f1:
; X32: movl %gs:i@NTPOFF, %eax
; X32-NEXT: ret
-; X64: f1:
+; X64-LABEL: f1:
; X64: movl %fs:i@TPOFF, %eax
; X64-NEXT: ret
}
define i32* @f2() {
-; X32: f2:
+; X32-LABEL: f2:
; X32: movl %gs:0, %eax
; X32-NEXT: leal i@NTPOFF(%eax), %eax
; X32-NEXT: ret
-; X64: f2:
+; X64-LABEL: f2:
; X64: movq %fs:0, %rax
; X64-NEXT: leaq i@TPOFF(%rax), %rax
; X64-NEXT: ret
}
define i32 @f3() {
-; X32: f3:
+; X32-LABEL: f3:
; X32: calll .L{{[0-9]+}}$pb
; X32-NEXT: .L{{[0-9]+}}$pb:
; X32-NEXT: popl %eax
; X32-NEXT: movl i2@GOTNTPOFF(%eax), %eax
; X32-NEXT: movl %gs:(%eax), %eax
; X32-NEXT: ret
-; X64: f3:
+; X64-LABEL: f3:
; X64: movq i2@GOTTPOFF(%rip), %rax
; X64-NEXT: movl %fs:(%rax), %eax
; X64-NEXT: ret
}
define i32* @f4() {
-; X32: f4:
+; X32-LABEL: f4:
; X32: calll .L{{[0-9]+}}$pb
; X32-NEXT: .L{{[0-9]+}}$pb:
; X32-NEXT: popl %ecx
; X32-NEXT: movl %gs:0, %eax
; X32-NEXT: addl i2@GOTNTPOFF(%ecx), %eax
; X32-NEXT: ret
-; X64: f4:
+; X64-LABEL: f4:
; X64: movq %fs:0, %rax
; X64-NEXT: addq i2@GOTTPOFF(%rip), %rax
; X64-NEXT: ret
@b1 = thread_local global i8 0
define i32 @f1() {
-; X32_LINUX: f1:
+; X32_LINUX-LABEL: f1:
; X32_LINUX: movl %gs:i1@NTPOFF, %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f1:
+; X64_LINUX-LABEL: f1:
; X64_LINUX: movl %fs:i1@TPOFF, %eax
; X64_LINUX-NEXT: ret
-; X32_WIN: f1:
+; X32_WIN-LABEL: f1:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: movl _i1@SECREL32(%eax), %eax
; X32_WIN-NEXT: ret
-; X64_WIN: f1:
+; X64_WIN-LABEL: f1:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i32* @f2() {
-; X32_LINUX: f2:
+; X32_LINUX-LABEL: f2:
; X32_LINUX: movl %gs:0, %eax
; X32_LINUX-NEXT: leal i1@NTPOFF(%eax), %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f2:
+; X64_LINUX-LABEL: f2:
; X64_LINUX: movq %fs:0, %rax
; X64_LINUX-NEXT: leaq i1@TPOFF(%rax), %rax
; X64_LINUX-NEXT: ret
-; X32_WIN: f2:
+; X32_WIN-LABEL: f2:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: leal _i1@SECREL32(%eax), %eax
; X32_WIN-NEXT: ret
-; X64_WIN: f2:
+; X64_WIN-LABEL: f2:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i32 @f3() nounwind {
-; X32_LINUX: f3:
+; X32_LINUX-LABEL: f3:
; X32_LINUX: movl i2@INDNTPOFF, %eax
; X32_LINUX-NEXT: movl %gs:(%eax), %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f3:
+; X64_LINUX-LABEL: f3:
; X64_LINUX: movq i2@GOTTPOFF(%rip), %rax
; X64_LINUX-NEXT: movl %fs:(%rax), %eax
; X64_LINUX-NEXT: ret
-; X32_WIN: f3:
+; X32_WIN-LABEL: f3:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: movl _i2@SECREL32(%eax), %eax
; X32_WIN-NEXT: ret
-; X64_WIN: f3:
+; X64_WIN-LABEL: f3:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i32* @f4() {
-; X32_LINUX: f4:
+; X32_LINUX-LABEL: f4:
; X32_LINUX: movl %gs:0, %eax
; X32_LINUX-NEXT: addl i2@INDNTPOFF, %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f4:
+; X64_LINUX-LABEL: f4:
; X64_LINUX: movq %fs:0, %rax
; X64_LINUX-NEXT: addq i2@GOTTPOFF(%rip), %rax
; X64_LINUX-NEXT: ret
-; X32_WIN: f4:
+; X32_WIN-LABEL: f4:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: leal _i2@SECREL32(%eax), %eax
; X32_WIN-NEXT: ret
-; X64_WIN: f4:
+; X64_WIN-LABEL: f4:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i32 @f5() nounwind {
-; X32_LINUX: f5:
+; X32_LINUX-LABEL: f5:
; X32_LINUX: movl %gs:i3@NTPOFF, %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f5:
+; X64_LINUX-LABEL: f5:
; X64_LINUX: movl %fs:i3@TPOFF, %eax
; X64_LINUX-NEXT: ret
-; X32_WIN: f5:
+; X32_WIN-LABEL: f5:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: movl _i3@SECREL32(%eax), %eax
; X32_WIN-NEXT: ret
-; X64_WIN: f5:
+; X64_WIN-LABEL: f5:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i32* @f6() {
-; X32_LINUX: f6:
+; X32_LINUX-LABEL: f6:
; X32_LINUX: movl %gs:0, %eax
; X32_LINUX-NEXT: leal i3@NTPOFF(%eax), %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f6:
+; X64_LINUX-LABEL: f6:
; X64_LINUX: movq %fs:0, %rax
; X64_LINUX-NEXT: leaq i3@TPOFF(%rax), %rax
; X64_LINUX-NEXT: ret
-; X32_WIN: f6:
+; X32_WIN-LABEL: f6:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: leal _i3@SECREL32(%eax), %eax
; X32_WIN-NEXT: ret
-; X64_WIN: f6:
+; X64_WIN-LABEL: f6:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i32 @f7() {
-; X32_LINUX: f7:
+; X32_LINUX-LABEL: f7:
; X32_LINUX: movl %gs:i4@NTPOFF, %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f7:
+; X64_LINUX-LABEL: f7:
; X64_LINUX: movl %fs:i4@TPOFF, %eax
; X64_LINUX-NEXT: ret
}
define i32* @f8() {
-; X32_LINUX: f8:
+; X32_LINUX-LABEL: f8:
; X32_LINUX: movl %gs:0, %eax
; X32_LINUX-NEXT: leal i4@NTPOFF(%eax), %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f8:
+; X64_LINUX-LABEL: f8:
; X64_LINUX: movq %fs:0, %rax
; X64_LINUX-NEXT: leaq i4@TPOFF(%rax), %rax
; X64_LINUX-NEXT: ret
}
define i32 @f9() {
-; X32_LINUX: f9:
+; X32_LINUX-LABEL: f9:
; X32_LINUX: movl %gs:i5@NTPOFF, %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f9:
+; X64_LINUX-LABEL: f9:
; X64_LINUX: movl %fs:i5@TPOFF, %eax
; X64_LINUX-NEXT: ret
}
define i32* @f10() {
-; X32_LINUX: f10:
+; X32_LINUX-LABEL: f10:
; X32_LINUX: movl %gs:0, %eax
; X32_LINUX-NEXT: leal i5@NTPOFF(%eax), %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f10:
+; X64_LINUX-LABEL: f10:
; X64_LINUX: movq %fs:0, %rax
; X64_LINUX-NEXT: leaq i5@TPOFF(%rax), %rax
; X64_LINUX-NEXT: ret
}
define i16 @f11() {
-; X32_LINUX: f11:
+; X32_LINUX-LABEL: f11:
; X32_LINUX: movzwl %gs:s1@NTPOFF, %eax
; Why is this kill line here, but no where else?
; X32_LINUX-NEXT: # kill
; X32_LINUX-NEXT: ret
-; X64_LINUX: f11:
+; X64_LINUX-LABEL: f11:
; X64_LINUX: movzwl %fs:s1@TPOFF, %eax
; X64_LINUX-NEXT: # kill
; X64_LINUX-NEXT: ret
-; X32_WIN: f11:
+; X32_WIN-LABEL: f11:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: movzwl _s1@SECREL32(%eax), %eax
; X32_WIN-NEXT: # kill
; X32_WIN-NEXT: ret
-; X64_WIN: f11:
+; X64_WIN-LABEL: f11:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i32 @f12() {
-; X32_LINUX: f12:
+; X32_LINUX-LABEL: f12:
; X32_LINUX: movswl %gs:s1@NTPOFF, %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f12:
+; X64_LINUX-LABEL: f12:
; X64_LINUX: movswl %fs:s1@TPOFF, %eax
; X64_LINUX-NEXT: ret
-; X32_WIN: f12:
+; X32_WIN-LABEL: f12:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: movswl _s1@SECREL32(%eax), %eax
; X32_WIN-NEXT: ret
-; X64_WIN: f12:
+; X64_WIN-LABEL: f12:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i8 @f13() {
-; X32_LINUX: f13:
+; X32_LINUX-LABEL: f13:
; X32_LINUX: movb %gs:b1@NTPOFF, %al
; X32_LINUX-NEXT: ret
-; X64_LINUX: f13:
+; X64_LINUX-LABEL: f13:
; X64_LINUX: movb %fs:b1@TPOFF, %al
; X64_LINUX-NEXT: ret
-; X32_WIN: f13:
+; X32_WIN-LABEL: f13:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: movb _b1@SECREL32(%eax), %al
; X32_WIN-NEXT: ret
-; X64_WIN: f13:
+; X64_WIN-LABEL: f13:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
}
define i32 @f14() {
-; X32_LINUX: f14:
+; X32_LINUX-LABEL: f14:
; X32_LINUX: movsbl %gs:b1@NTPOFF, %eax
; X32_LINUX-NEXT: ret
-; X64_LINUX: f14:
+; X64_LINUX-LABEL: f14:
; X64_LINUX: movsbl %fs:b1@TPOFF, %eax
; X64_LINUX-NEXT: ret
-; X32_WIN: f14:
+; X32_WIN-LABEL: f14:
; X32_WIN: movl __tls_index, %eax
; X32_WIN-NEXT: movl %fs:__tls_array, %ecx
; X32_WIN-NEXT: movl (%ecx,%eax,4), %eax
; X32_WIN-NEXT: movsbl _b1@SECREL32(%eax), %eax
; X32_WIN-NEXT: ret
-; X64_WIN: f14:
+; X64_WIN-LABEL: f14:
; X64_WIN: movl _tls_index(%rip), %eax
; X64_WIN-NEXT: movq %gs:88, %rcx
; X64_WIN-NEXT: movq (%rcx,%rax,8), %rax
@c = external thread_local global %struct.A, align 4
define void @main() nounwind ssp {
-; CHECK: main:
+; CHECK-LABEL: main:
entry:
call void @llvm.memset.p0i8.i64(i8* getelementptr inbounds (%struct.A* @c, i32 0, i32 0, i32 0), i8 0, i64 60, i32 1, i1 false)
unreachable
%obil = extractvalue {i32, i1} %res, 1
ret i1 %obil
-; CHECK: a:
+; CHECK-LABEL: a:
; CHECK: mull
; CHECK: seto %al
; CHECK: movzbl %al, %eax
ret void
}
-; X8664: calls_unwind_init:
+; X8664-LABEL: calls_unwind_init:
; X8664: pushq %rbp
; X8664: pushq %r15
; X8664: pushq %r14
; X8664: popq %r14
; X8664: popq %r15
-; X8632: calls_unwind_init:
+; X8632-LABEL: calls_unwind_init:
; X8632: pushl %ebp
; X8632: pushl %ebx
; X8632: pushl %edi
define <4 x i32> @signd(<4 x i32> %a, <4 x i32> %b) nounwind {
entry:
-; CHECK: signd:
+; CHECK-LABEL: signd:
; CHECK: psignd
; CHECK-NOT: sub
; CHECK: ret
define <4 x i32> @blendvb(<4 x i32> %b, <4 x i32> %a, <4 x i32> %c) nounwind {
entry:
-; CHECK: blendvb:
+; CHECK-LABEL: blendvb:
; CHECK: pblendvb
; CHECK: ret
%b.lobit = ashr <4 x i32> %b, <i32 31, i32 31, i32 31, i32 31>
; RUN: llc < %s -march=x86-64 -mattr=+sse2,-sse41 | FileCheck --check-prefix=X64 %s
define <4 x float> @t1(float %s, <4 x float> %tmp) nounwind {
-; X32: t1:
+; X32-LABEL: t1:
; X32: shufps $36
; X32: ret
}
define <4 x i32> @t2(i32 %s, <4 x i32> %tmp) nounwind {
-; X32: t2:
+; X32-LABEL: t2:
; X32: shufps $36
; X32: ret
}
define <2 x double> @t3(double %s, <2 x double> %tmp) nounwind {
-; X32: t3:
+; X32-LABEL: t3:
; X32: movhpd
; X32: ret
-; X64: t3:
+; X64-LABEL: t3:
; X64: unpcklpd
; X64: ret
}
define <8 x i16> @t4(i16 %s, <8 x i16> %tmp) nounwind {
-; X32: t4:
+; X32-LABEL: t4:
; X32: pinsrw
; X32: ret
store x86_mmx %tmp23, x86_mmx* %P
ret void
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK-NOT: %mm
; CHECK: shll $12
; CHECK-NOT: %mm
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 4, i32 4, i32 4, i32 0 >
ret <4 x float> %tmp2
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: pslldq $12
}
%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> zeroinitializer, <4 x i32> < i32 2, i32 3, i32 4, i32 4 >
ret <4 x float> %tmp2
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: psrldq $8
}
%tmp2 = shufflevector <4 x float> zeroinitializer, <4 x float> %tmp1, <4 x i32> < i32 7, i32 0, i32 0, i32 0 >
ret <4 x float> %tmp2
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: psrldq $12
}
%s = shufflevector <16 x i8> %x, <16 x i8> zeroinitializer, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 17>
ret <16 x i8> %s
-; CHECK: t5:
+; CHECK-LABEL: t5:
; CHECK: psrldq $1
}
%s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <16 x i8> %s
-; CHECK: t6:
+; CHECK-LABEL: t6:
; CHECK: palignr $1
}
%s = shufflevector <16 x i8> %x, <16 x i8> undef, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 1, i32 2>
ret <16 x i8> %s
-; CHECK: t7:
+; CHECK-LABEL: t7:
; CHECK: pslldq $13
}
%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp, <4 x i32> < i32 4, i32 1, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
ret <4 x i32> %tmp6
-; X86-32: t1:
+; X86-32-LABEL: t1:
; X86-32: movd 4(%esp), %xmm0
-; X86-64: t1:
+; X86-64-LABEL: t1:
; X86-64: movd %e{{..}}, %xmm0
}
%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %tmp, <2 x i32> < i32 2, i32 1 > ; <<4 x i32>> [#uses=1]
ret <2 x i64> %tmp6
-; X86-32: t2:
+; X86-32-LABEL: t2:
; X86-32: movq 4(%esp), %xmm0
-; X86-64: t2:
+; X86-64-LABEL: t2:
; X86-64: movd %r{{..}}, %xmm0
}
%tmp8 = bitcast <4 x i32> %tmp7 to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp8
-; X86-32: t3:
+; X86-32-LABEL: t3:
; X86-32: movl 4(%esp)
; X86-32: movq
-; X86-64: t3:
+; X86-64-LABEL: t3:
; X86-64: movq ({{.*}}), %xmm0
}
%tmp7 = bitcast <4 x i32> %tmp6 to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp7
-; X86-32: t4:
+; X86-32-LABEL: t4:
; X86-32: movq %xmm0, %xmm0
-; X86-64: t4:
+; X86-64-LABEL: t4:
; X86-64: movq {{.*}}, %xmm0
}
%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> < i32 2, i32 1 > ; <<4 x i32>> [#uses=1]
ret <2 x i64> %tmp6
-; X86-32: t5:
+; X86-32-LABEL: t5:
; X86-32: movq %xmm0, %xmm0
-; X86-64: t5:
+; X86-64-LABEL: t5:
; X86-64: movq {{.*}}, %xmm0
}
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse,-sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse
; RUN: llc < %s -march=x86 -mcpu=penryn -mattr=+sse2 -mtriple=i386-apple-darwin | FileCheck %s -check-prefix=sse2
-; sse: t1:
-; sse2: t1:
+; sse-LABEL: t1:
+; sse2-LABEL: t1:
define <4 x float> @t1(<4 x float> %a, <4 x float> %b) nounwind {
; sse: shufps
; sse2: pshufd
ret <4 x float> %tmp1
}
-; sse: t2:
-; sse2: t2:
+; sse-LABEL: t2:
+; sse2-LABEL: t2:
define <4 x float> @t2(<4 x float> %A, <4 x float> %B) nounwind {
; sse: shufps
; sse2: pshufd
ret <4 x float> %tmp
}
-; sse: t3:
-; sse2: t3:
+; sse-LABEL: t3:
+; sse2-LABEL: t3:
define <4 x float> @t3(<4 x float> %A, <4 x float> %B) nounwind {
; sse: shufps
; sse2: pshufd
ret <4 x float> %tmp
}
-; sse: t4:
-; sse2: t4:
+; sse-LABEL: t4:
+; sse2-LABEL: t4:
define <4 x float> @t4(<4 x float> %A, <4 x float> %B) nounwind {
; sse: shufps
define <4 x float> @t1(<4 x float> %a, <1 x i64>* nocapture %p) nounwind {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: movlps (%rdi), %xmm0
; CHECK: ret
%p.val = load <1 x i64>* %p, align 1
define <4 x float> @t1a(<4 x float> %a, <1 x i64>* nocapture %p) nounwind {
entry:
-; CHECK: t1a:
+; CHECK-LABEL: t1a:
; CHECK: movlps (%rdi), %xmm0
; CHECK: ret
%0 = bitcast <1 x i64>* %p to double*
define void @t2(<1 x i64>* nocapture %p, <4 x float> %a) nounwind {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: movlps %xmm0, (%rdi)
; CHECK: ret
%cast.i = bitcast <4 x float> %a to <2 x i64>
define void @t2a(<1 x i64>* nocapture %p, <4 x float> %a) nounwind {
entry:
-; CHECK: t2a:
+; CHECK-LABEL: t2a:
; CHECK: movlps %xmm0, (%rdi)
; CHECK: ret
%0 = bitcast <1 x i64>* %p to double*
; rdar://10436044
define <2 x double> @t3() nounwind readonly {
bb:
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: punpcklqdq %xmm1, %xmm0
; CHECK: movq (%rax), %xmm1
; CHECK: movsd %xmm1, %xmm0
; rdar://10450317
define <2 x i64> @t4() nounwind readonly {
bb:
-; CHECK: t4:
+; CHECK-LABEL: t4:
; CHECK: punpcklqdq %xmm0, %xmm1
; CHECK: movq (%rax), %xmm0
; CHECK: movsd %xmm1, %xmm0
%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i16> %tmp6
-; CHECK: shuf_8i16_0:
+; CHECK-LABEL: shuf_8i16_0:
; CHECK: pshuflw $0
}
%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i16> %tmp6
-; CHECK: shuf_8i16_1:
+; CHECK-LABEL: shuf_8i16_1:
; CHECK: pshuflw $5
}
%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 undef, i32 undef>
ret <8 x i16> %tmp6
-; CHECK: shuf_8i16_2:
+; CHECK-LABEL: shuf_8i16_2:
; CHECK: punpcklwd
; CHECK-NEXT: pshufd $-86
}
%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 3, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i16> %tmp6
-; CHECK: shuf_8i16_3:
+; CHECK-LABEL: shuf_8i16_3:
; CHECK: pshuflw $15
}
%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef>
ret <8 x i16> %tmp6
-; CHECK: shuf_8i16_4:
+; CHECK-LABEL: shuf_8i16_4:
; CHECK: movhlps
}
%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i16> %tmp6
-; CHECK: shuf_8i16_5:
+; CHECK-LABEL: shuf_8i16_5:
; CHECK: punpckhwd
; CHECK-NEXT: pshufd $85
}
%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 6, i32 6, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i16> %tmp6
-; CHECK: shuf_8i16_6:
+; CHECK-LABEL: shuf_8i16_6:
; CHECK: punpckhwd
; CHECK-NEXT: pshufd $-86
}
%tmp6 = shufflevector <8 x i16> %T0, <8 x i16> %T1, <8 x i32> <i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
ret <8 x i16> %tmp6
-; CHECK: shuf_8i16_7:
+; CHECK-LABEL: shuf_8i16_7:
; CHECK: punpckhwd
; CHECK-NEXT: pshufd $-1
}
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 0, i32 undef, i32 undef, i32 0, i32 undef, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_8:
+; CHECK-LABEL: shuf_16i8_8:
; CHECK: punpcklbw
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: pshufd $0
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_9:
+; CHECK-LABEL: shuf_16i8_9:
; CHECK: punpcklbw
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: pshufd $85
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 2, i32 undef, i32 undef, i32 2, i32 undef, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_10:
+; CHECK-LABEL: shuf_16i8_10:
; CHECK: punpcklbw
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: pshufd $-86
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 3, i32 undef, i32 undef, i32 3, i32 undef, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_11:
+; CHECK-LABEL: shuf_16i8_11:
; CHECK: punpcklbw
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: pshufd $-1
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 4, i32 undef, i32 undef, i32 undef, i32 4, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_12:
+; CHECK-LABEL: shuf_16i8_12:
; CHECK: pshufd $5
}
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 5, i32 undef, i32 undef, i32 5, i32 undef, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_13:
+; CHECK-LABEL: shuf_16i8_13:
; CHECK: punpcklbw
; CHECK-NEXT: punpckhbw
; CHECK-NEXT: pshufd $85
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 6, i32 undef, i32 undef, i32 6, i32 undef, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_14:
+; CHECK-LABEL: shuf_16i8_14:
; CHECK: punpcklbw
; CHECK-NEXT: punpckhbw
; CHECK-NEXT: pshufd $-86
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 7, i32 undef, i32 undef, i32 7, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef >
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_15:
+; CHECK-LABEL: shuf_16i8_15:
; CHECK: punpcklbw
; CHECK-NEXT: punpckhbw
; CHECK-NEXT: pshufd $-1
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 8, i32 undef, i32 undef, i32 8, i32 undef, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8, i32 8>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_16:
+; CHECK-LABEL: shuf_16i8_16:
; CHECK: punpckhbw
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: pshufd $0
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 9, i32 undef, i32 undef, i32 9, i32 undef, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9, i32 9>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_17:
+; CHECK-LABEL: shuf_16i8_17:
; CHECK: punpckhbw
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: pshufd $85
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 10, i32 undef, i32 undef, i32 10, i32 undef, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10, i32 10>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_18:
+; CHECK-LABEL: shuf_16i8_18:
; CHECK: punpckhbw
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: pshufd $-86
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 11, i32 undef, i32 undef, i32 11, i32 undef, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11, i32 11>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_19:
+; CHECK-LABEL: shuf_16i8_19:
; CHECK: punpckhbw
; CHECK-NEXT: punpcklbw
; CHECK-NEXT: pshufd $-1
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 12, i32 undef, i32 undef, i32 12, i32 undef, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12, i32 12>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_20:
+; CHECK-LABEL: shuf_16i8_20:
; CHECK: punpckhbw
; CHECK-NEXT: punpckhbw
; CHECK-NEXT: pshufd $0
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 13, i32 undef, i32 undef, i32 13, i32 undef, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13, i32 13>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_21:
+; CHECK-LABEL: shuf_16i8_21:
; CHECK: punpckhbw
; CHECK-NEXT: punpckhbw
; CHECK-NEXT: pshufd $85
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 14, i32 undef, i32 undef, i32 14, i32 undef, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14, i32 14>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_22:
+; CHECK-LABEL: shuf_16i8_22:
; CHECK: punpckhbw
; CHECK-NEXT: punpckhbw
; CHECK-NEXT: pshufd $-86
%tmp6 = shufflevector <16 x i8> %T0, <16 x i8> %T1, <16 x i32> <i32 15, i32 undef, i32 undef, i32 15, i32 undef, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15, i32 15>
ret <16 x i8> %tmp6
-; CHECK: shuf_16i8_23:
+; CHECK-LABEL: shuf_16i8_23:
; CHECK: punpckhbw
; CHECK-NEXT: punpckhbw
; CHECK-NEXT: pshufd $-1
; RUN: llc < %s -march=x86 -mcpu=corei7-avx | FileCheck %s
; RUN: opt -instsimplify -disable-output < %s
-;CHECK: AGEP0:
+;CHECK-LABEL: AGEP0:
define <4 x i32*> @AGEP0(i32* %ptr) nounwind {
entry:
%vecinit.i = insertelement <4 x i32*> undef, i32* %ptr, i32 0
;CHECK: ret
}
-;CHECK: AGEP1:
+;CHECK-LABEL: AGEP1:
define i32 @AGEP1(<4 x i32*> %param) nounwind {
entry:
;CHECK: padd
;CHECK: ret
}
-;CHECK: AGEP2:
+;CHECK-LABEL: AGEP2:
define i32 @AGEP2(<4 x i32*> %param, <4 x i32> %off) nounwind {
entry:
;CHECK: pslld $2
;CHECK: ret
}
-;CHECK: AGEP3:
+;CHECK-LABEL: AGEP3:
define <4 x i32*> @AGEP3(<4 x i32*> %param, <4 x i32> %off) nounwind {
entry:
;CHECK: pslld $2
;CHECK: ret
}
-;CHECK: AGEP4:
+;CHECK-LABEL: AGEP4:
define <4 x i16*> @AGEP4(<4 x i16*> %param, <4 x i32> %off) nounwind {
entry:
; Multiply offset by two (add it to itself).
;CHECK: ret
}
-;CHECK: AGEP5:
+;CHECK-LABEL: AGEP5:
define <4 x i8*> @AGEP5(<4 x i8*> %param, <4 x i8> %off) nounwind {
entry:
;CHECK: paddd
; The size of each element is 1 byte. No need to multiply by element size.
-;CHECK: AGEP6:
+;CHECK-LABEL: AGEP6:
define <4 x i8*> @AGEP6(<4 x i8*> %param, <4 x i32> %off) nounwind {
entry:
;CHECK-NOT: pslld
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
; CHECK: psllq
%shl = shl <2 x i64> %val, < i64 32, i64 32 >
store <2 x i64> %shl, <2 x i64>* %dst
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
; CHECK: movd
; CHECK: psllq
%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
; CHECK: pslld
%shl = shl <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
store <4 x i32> %shl, <4 x i32>* %dst
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
; CHECK: movd
; CHECK: pslld
%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
; CHECK: psllw
%shl = shl <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
store <8 x i16> %shl, <8 x i16>* %dst
; Make sure the shift amount is properly zero extended.
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
; CHECK: movzwl
; CHECK: movd
; CHECK-NEXT: psllw
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
; CHECK: psrlq
%lshr = lshr <2 x i64> %val, < i64 32, i64 32 >
store <2 x i64> %lshr, <2 x i64>* %dst
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, i64 %amt) nounwind {
entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
; CHECK: movd
; CHECK: psrlq
%0 = insertelement <2 x i64> undef, i64 %amt, i32 0
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
; CHECK: psrld
%lshr = lshr <4 x i32> %val, < i32 17, i32 17, i32 17, i32 17 >
store <4 x i32> %lshr, <4 x i32>* %dst
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
; CHECK: movd
; CHECK: psrld
%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
; CHECK: psrlw
%lshr = lshr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
store <8 x i16> %lshr, <8 x i16>* %dst
; properly zero extend the shift amount
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
; CHECK: movzwl
; CHECK: movd
; CHECK: psrlw
; shift1a can't use a packed shift
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst) nounwind {
entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
; CHECK: sarl
%ashr = ashr <2 x i64> %val, < i64 32, i64 32 >
store <2 x i64> %ashr, <2 x i64>* %dst
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst) nounwind {
entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
; CHECK: psrad $5
%ashr = ashr <4 x i32> %val, < i32 5, i32 5, i32 5, i32 5 >
store <4 x i32> %ashr, <4 x i32>* %dst
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
; CHECK: movd
; CHECK: psrad
%0 = insertelement <4 x i32> undef, i32 %amt, i32 0
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst) nounwind {
entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
; CHECK: psraw $5
%ashr = ashr <8 x i16> %val, < i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5 >
store <8 x i16> %ashr, <8 x i16>* %dst
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
; CHECK: movzwl
; CHECK: movd
; CHECK: psraw
define void @shift1a(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
entry:
-; CHECK: shift1a:
+; CHECK-LABEL: shift1a:
; CHECK: psllq
%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 0>
%shl = shl <2 x i64> %val, %shamt
; shift1b can't use a packed shift
define void @shift1b(<2 x i64> %val, <2 x i64>* %dst, <2 x i64> %sh) nounwind {
entry:
-; CHECK: shift1b:
+; CHECK-LABEL: shift1b:
; CHECK: shll
%shamt = shufflevector <2 x i64> %sh, <2 x i64> undef, <2 x i32> <i32 0, i32 1>
%shl = shl <2 x i64> %val, %shamt
define void @shift2a(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
entry:
-; CHECK: shift2a:
+; CHECK-LABEL: shift2a:
; CHECK: pslld
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt
define void @shift2b(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
entry:
-; CHECK: shift2b:
+; CHECK-LABEL: shift2b:
; CHECK: pslld
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 undef, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt
define void @shift2c(<4 x i32> %val, <4 x i32>* %dst, <2 x i32> %amt) nounwind {
entry:
-; CHECK: shift2c:
+; CHECK-LABEL: shift2c:
; CHECK: pslld
%shamt = shufflevector <2 x i32> %amt, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
%shl = shl <4 x i32> %val, %shamt
define void @shift3a(<8 x i16> %val, <8 x i16>* %dst, <8 x i16> %amt) nounwind {
entry:
-; CHECK: shift3a:
+; CHECK-LABEL: shift3a:
; CHECK: movzwl
; CHECK: psllw
%shamt = shufflevector <8 x i16> %amt, <8 x i16> undef, <8 x i32> <i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6, i32 6>
define void @shift3b(<8 x i16> %val, <8 x i16>* %dst, i16 %amt) nounwind {
entry:
-; CHECK: shift3b:
+; CHECK-LABEL: shift3b:
; CHECK: movzwl
; CHECK: psllw
%0 = insertelement <8 x i16> undef, i16 %amt, i32 0
define void @shift5a(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
entry:
-; CHECK: shift5a:
+; CHECK-LABEL: shift5a:
; CHECK: movd
; CHECK: pslld
%amt = load i32* %pamt
define void @shift5b(<4 x i32> %val, <4 x i32>* %dst, i32* %pamt) nounwind {
entry:
-; CHECK: shift5b:
+; CHECK-LABEL: shift5b:
; CHECK: movd
; CHECK: psrad
%amt = load i32* %pamt
define void @shift5c(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
-; CHECK: shift5c:
+; CHECK-LABEL: shift5c:
; CHECK: movd
; CHECK: pslld
%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
define void @shift5d(<4 x i32> %val, <4 x i32>* %dst, i32 %amt) nounwind {
entry:
-; CHECK: shift5d:
+; CHECK-LABEL: shift5d:
; CHECK: movd
; CHECK: psrad
%tmp0 = insertelement <4 x i32> undef, i32 %amt, i32 0
define void @convert(<2 x double>* %dst.addr, <3 x double> %src) {
entry:
-; CHECK: convert:
+; CHECK-LABEL: convert:
; CHECK: unpcklpd {{%xmm[0-7]}}, {{%xmm[0-7]}}
; CHECK-NEXT: movapd
%val = shufflevector <3 x double> %src, <3 x double> undef, <2 x i32> < i32 0, i32 1>
ret void
}
-; CHECK: add31i8:
+; CHECK-LABEL: add31i8:
%i8vec31 = type <31 x i8>
define void @add31i8(%i8vec31* nocapture sret %ret, %i8vec31* %ap, %i8vec31* %bp) nounwind {
; CHECK: movdqa
; widening shuffle v3float and then a add
define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
entry:
-; CHECK: shuf:
+; CHECK-LABEL: shuf:
; CHECK: extractps
; CHECK: extractps
%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
; widening shuffle v3float with a different mask and then a add
define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
entry:
-; CHECK: shuf2:
+; CHECK-LABEL: shuf2:
; CHECK: extractps
; CHECK: extractps
%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
; opA with opB, the DAG will produce new operations with opA.
define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
entry:
-; CHECK: shuf3:
+; CHECK-LABEL: shuf3:
; CHECK: shufps
%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
-; CHECK: shuf4:
+; CHECK-LABEL: shuf4:
; CHECK-NOT: punpckldq
%vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
ret <8 x i8> %vshuf
; PR11389: another CONCAT_VECTORS case
define void @shuf5(<8 x i8>* %p) nounwind {
-; CHECK: shuf5:
+; CHECK-LABEL: shuf5:
%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
store <8 x i8> %v, <8 x i8>* %p, align 8
ret void
declare void @llvm.va_start(i8*) nounwind
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: pushq
; CHECK: leaq 56(%rsp),
define i8* @f5(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, ...) nounwind {
ret i8* %ap1
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: pushq
; CHECK: leaq 48(%rsp),
define i8* @f4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind {
ret i8* %ap1
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: pushq
; CHECK: leaq 40(%rsp),
define i8* @f3(i64 %a0, i64 %a1, i64 %a2, ...) nounwind {
}
; This copy can't be coalesced away because it needs the implicit zero-extend.
-; CHECK: bbb:
+; CHECK-LABEL: bbb:
; CHECK: movl %edi, %edi
define void @bbb(i64 %x) nounwind {
; This should use a 32-bit and with implicit zero-extension, not a 64-bit and
; with a separate mov to materialize the mask.
; rdar://7527390
-; CHECK: ccc:
+; CHECK-LABEL: ccc:
; CHECK: andl $-1048593, %edi
declare void @foo(i64 %x) nounwind
}
; This requires a mov and a 64-bit and.
-; CHECK: ddd:
+; CHECK-LABEL: ddd:
; CHECK: movabsq $4294967296, %r
; CHECK: andq %rax, %rdi
%struct.foo = type { [4 x i64] }
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: movq %rdi, %rax
; For the x32 ABI, pointers are 32-bit so 32-bit instructions will be used
-; X32ABI: bar:
+; X32ABI-LABEL: bar:
; X32ABI: movl %edi, %eax
define void @bar(%struct.foo* noalias sret %agg.result, %struct.foo* %d) nounwind {
ret void
}
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: movq %rdi, %rax
; For the x32 ABI, pointers are 32-bit so 32-bit instructions will be used
-; X32ABI: foo:
+; X32ABI-LABEL: foo:
; X32ABI: movl %edi, %eax
define void @foo({ i64 }* noalias nocapture sret %agg.result) nounwind {
define <16 x i8> @shl9(<16 x i8> %A) nounwind {
%B = shl <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %B
-; CHECK: shl9:
+; CHECK-LABEL: shl9:
; CHECK: psllw $3
; CHECK: pand
; CHECK: ret
define <16 x i8> @shr9(<16 x i8> %A) nounwind {
%B = lshr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %B
-; CHECK: shr9:
+; CHECK-LABEL: shr9:
; CHECK: psrlw $3
; CHECK: pand
; CHECK: ret
define <16 x i8> @sra_v16i8_7(<16 x i8> %A) nounwind {
%B = ashr <16 x i8> %A, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
ret <16 x i8> %B
-; CHECK: sra_v16i8_7:
+; CHECK-LABEL: sra_v16i8_7:
; CHECK: pxor
; CHECK: pcmpgtb
; CHECK: ret
define <16 x i8> @sra_v16i8(<16 x i8> %A) nounwind {
%B = ashr <16 x i8> %A, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
ret <16 x i8> %B
-; CHECK: sra_v16i8:
+; CHECK-LABEL: sra_v16i8:
; CHECK: psrlw $3
; CHECK: pand
; CHECK: pxor
@.str = private unnamed_addr constant [10 x i8] c"%llx, %d\0A\00", align 1
define i32 @t1() nounwind {
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: movl $0, 12(%esp)
; CHECK: movl $0, 8(%esp)
; CHECK: movl $72, 4(%esp)
}
define i32 @t2() nounwind {
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: movl $0, 12(%esp)
; CHECK: movl $0, 8(%esp)
; CHECK: movl $0, 4(%esp)
}
define i32 @t3() nounwind {
-; CHECK: t3:
+; CHECK-LABEL: t3:
; CHECK: movl $1, 12(%esp)
; CHECK: movl $-1, 8(%esp)
; CHECK: movl $-9, 4(%esp)
define i32 @t(i32 %a, i32 %b) nounwind ssp {
entry:
-; X32: t:
+; X32-LABEL: t:
; X32: xorb
; X32-NOT: andb
; X32-NOT: shrb
; X32: testb $64
; X32: je
-; X64: t:
+; X64-LABEL: t:
; X64-NOT: setne
; X64: xorl
; X64: testb $64
declare i32 @bar(...)
define i32 @t2(i32 %x, i32 %y) nounwind ssp {
-; X32: t2:
+; X32-LABEL: t2:
; X32: cmpl
; X32: sete
; X32: cmpl
; X32-NOT: xor
; X32: je
-; X64: t2:
+; X64-LABEL: t2:
; X64: testl
; X64: sete
; X64: testl
call void @bar(double 0.0)
ret double 0.0
-;CHECK-32: foo:
+;CHECK-32-LABEL: foo:
;CHECK-32: call
;CHECK-32: fldz
;CHECK-32: ret
-;CHECK-64: foo:
+;CHECK-64-LABEL: foo:
;CHECK-64: xorps
;CHECK-64: call
;CHECK-64: xorps
call void @barf(float 0.0)
ret float 0.0
-;CHECK-32: foof:
+;CHECK-32-LABEL: foof:
;CHECK-32: call
;CHECK-32: fldz
;CHECK-32: ret
-;CHECK-64: foof:
+;CHECK-64-LABEL: foof:
;CHECK-64: xorps
;CHECK-64: call
;CHECK-64: xorps
; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
define void @t() nounwind ssp {
-; CHECK: t:
+; CHECK-LABEL: t:
entry:
br i1 undef, label %return, label %if.end.i
define i32 @t1(i8 zeroext %x) nounwind readnone ssp {
entry:
-; CHECK: t1:
+; CHECK-LABEL: t1:
; CHECK: shll
; CHECK-NOT: movzwl
; CHECK: ret
define i32 @t2(i8 zeroext %x) nounwind readnone ssp {
entry:
-; CHECK: t2:
+; CHECK-LABEL: t2:
; CHECK: shrl
; CHECK-NOT: movzwl
; CHECK: ret
; rdar://7570931
define i64 @foo(i64 %a, i64 %b) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
; CHECK: leal
; CHECK-NOT: movl
; CHECK: ret
call void @llvm.stackrestore(i8* %0)
ret void
}
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: ldaw [[REGISTER:r[0-9]+]], {{r[0-9]+}}[-r1]
; CHECK: set sp, [[REGISTER]]
; CHECK: extsp 1
; RUN: llc < %s -march=xcore | FileCheck %s
define void @_Z1fz(...) {
entry:
-; CHECK: _Z1fz:
+; CHECK-LABEL: _Z1fz:
; CHECK: extsp 3
; CHECK: stw r[[REG:[0-3]{1,1}]]
; CHECK: , sp{{\[}}[[REG]]{{\]}}
%3 = add i64 %2, %a
ret i64 %3
}
-; CHECK: maccu:
+; CHECK-LABEL: maccu:
; CHECK: maccu r1, r0, r3, r2
; CHECK-NEXT: retsp 0
%3 = add i64 %2, %a
ret i64 %3
}
-; CHECK: maccs:
+; CHECK-LABEL: maccs:
; CHECK: maccs r1, r0, r3, r2
; CHECK-NEXT: retsp 0
%6 = add i64 %5, %3
ret i64 %6
}
-; CHECK: lmul:
+; CHECK-LABEL: lmul:
; CHECK: lmul r1, r0, r1, r0, r2, r3
; CHECK-NEXT: retsp 0
@b = alias i32* @b_val
@c = alias i32* @c_val
-; CHECK: a_addr:
+; CHECK-LABEL: a_addr:
; CHECK: ldap r11, a
; CHECK: retsp
define void ()* @a_addr() nounwind {
ret void ()* @a
}
-; CHECK: b_addr:
+; CHECK-LABEL: b_addr:
; CHECK: ldaw r11, cp[b]
; CHECK: retsp
define i32 *@b_addr() nounwind {
ret i32* @b
}
-; CHECK: c_addr:
+; CHECK-LABEL: c_addr:
; CHECK: ldaw r0, dp[c]
; CHECK: retsp
define i32 *@c_addr() nounwind {
%1 = ashr i32 %a, %b
ret i32 %1
}
-; CHECK: ashr:
+; CHECK-LABEL: ashr:
; CHECK-NEXT: ashr r0, r0, r1
define i32 @ashri1(i32 %a) {
%1 = ashr i32 %a, 24
ret i32 %1
}
-; CHECK: ashri1:
+; CHECK-LABEL: ashri1:
; CHECK-NEXT: ashr r0, r0, 24
define i32 @ashri2(i32 %a) {
%1 = ashr i32 %a, 31
ret i32 %1
}
-; CHECK: ashri2:
+; CHECK-LABEL: ashri2:
; CHECK-NEXT: ashr r0, r0, 32
define i32 @f1(i32 %a) {
not_less:
ret i32 17
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK-NEXT: ashr r0, r0, 32
; CHECK-NEXT: bt r0
not_greater:
ret i32 17
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK-NEXT: ashr r0, r0, 32
; CHECK-NEXT: bt r0
%2 = select i1 %1, i32 10, i32 17
ret i32 %2
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK-NEXT: ashr r0, r0, 32
; CHECK-NEXT: bt r0
; CHECK-NEXT: ldc r0, 17
%2 = select i1 %1, i32 10, i32 17
ret i32 %2
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK-NEXT: ashr r0, r0, 32
; CHECK-NEXT: bt r0
; CHECK-NEXT: ldc r0, 10
%2 = zext i1 %1 to i32
ret i32 %2
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK-NEXT: ashr r0, r0, 32
; CHECK-NEXT: eq r0, r0, 0
%3 = insertvalue %0 %2, i32 24601, 3
ret %0 %3
}
-; CHECK: ReturnBigStruct:
+; CHECK-LABEL: ReturnBigStruct:
; CHECK: ldc r0, 12
; CHECK: ldc r1, 24
; CHECK: ldc r2, 48
%4 = insertvalue %1 %3, i32 4321, 4
ret %1 %4
}
-; CHECK: ReturnBigStruct2:
+; CHECK-LABEL: ReturnBigStruct2:
; CHECK: ldc r1, 4321
; CHECK: stw r1, r0[4]
; CHECK: ldc r1, 24601
; CHECK: .section .cp.rodata.cst4,"aMc",@progbits,4
; CHECK: .LCPI0_0:
; CHECK: .long 12345678
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: ldw r0, cp[.LCPI0_0]
define i32 @f() {
entry:
define i32 @g() {
entry:
-; CHECK: g:
+; CHECK-LABEL: g:
; CHECK: mkmsk r0, 1
; CHECK: retsp 0
ret i32 1;
declare void @llvm.xcore.clre()
define i32 @f(i8 addrspace(1)* %r) nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
entry:
; CHECK: clre
call void @llvm.xcore.clre()
}
define i32 @g(i8 addrspace(1)* %r) nounwind {
-; CHECK: g:
+; CHECK-LABEL: g:
entry:
; CHECK: clre
call void @llvm.xcore.clre()
declare double @llvm.sqrt.f64(double)
define double @cos(double %F) {
-; CHECK: cos:
+; CHECK-LABEL: cos:
; CHECK: bl cos
%result = call double @llvm.cos.f64(double %F)
ret double %result
declare float @llvm.cos.f32(float)
-; CHECK: cosf:
+; CHECK-LABEL: cosf:
; CHECK: bl cosf
define float @cosf(float %F) {
%result = call float @llvm.cos.f32(float %F)
}
define double @exp(double %F) {
-; CHECK: exp:
+; CHECK-LABEL: exp:
; CHECK: bl exp
%result = call double @llvm.exp.f64(double %F)
ret double %result
declare float @llvm.exp.f32(float)
define float @expf(float %F) {
-; CHECK: expf:
+; CHECK-LABEL: expf:
; CHECK: bl expf
%result = call float @llvm.exp.f32(float %F)
ret float %result
}
define double @exp2(double %F) {
-; CHECK: exp2:
+; CHECK-LABEL: exp2:
; CHECK: bl exp2
%result = call double @llvm.exp2.f64(double %F)
ret double %result
declare float @llvm.exp2.f32(float)
define float @exp2f(float %F) {
-; CHECK: exp2f:
+; CHECK-LABEL: exp2f:
; CHECK: bl exp2f
%result = call float @llvm.exp2.f32(float %F)
ret float %result
}
define double @log(double %F) {
-; CHECK: log:
+; CHECK-LABEL: log:
; CHECK: bl log
%result = call double @llvm.log.f64(double %F)
ret double %result
declare float @llvm.log.f32(float)
define float @logf(float %F) {
-; CHECK: logf:
+; CHECK-LABEL: logf:
; CHECK: bl logf
%result = call float @llvm.log.f32(float %F)
ret float %result
}
define double @log10(double %F) {
-; CHECK: log10:
+; CHECK-LABEL: log10:
; CHECK: bl log10
%result = call double @llvm.log10.f64(double %F)
ret double %result
declare float @llvm.log10.f32(float)
define float @log10f(float %F) {
-; CHECK: log10f:
+; CHECK-LABEL: log10f:
; CHECK: bl log10f
%result = call float @llvm.log10.f32(float %F)
ret float %result
}
define double @log2(double %F) {
-; CHECK: log2:
+; CHECK-LABEL: log2:
; CHECK: bl log2
%result = call double @llvm.log2.f64(double %F)
ret double %result
declare float @llvm.log2.f32(float)
define float @log2f(float %F) {
-; CHECK: log2f:
+; CHECK-LABEL: log2f:
; CHECK: bl log2f
%result = call float @llvm.log2.f32(float %F)
ret float %result
}
define double @pow(double %F, double %power) {
-; CHECK: pow:
+; CHECK-LABEL: pow:
; CHECK: bl pow
%result = call double @llvm.pow.f64(double %F, double %power)
ret double %result
declare float @llvm.pow.f32(float, float)
define float @powf(float %F, float %power) {
-; CHECK: powf:
+; CHECK-LABEL: powf:
; CHECK: bl powf
%result = call float @llvm.pow.f32(float %F, float %power)
ret float %result
}
define double @powi(double %F, i32 %power) {
-; CHECK: powi:
+; CHECK-LABEL: powi:
; CHECK: bl __powidf2
%result = call double @llvm.powi.f64(double %F, i32 %power)
ret double %result
declare float @llvm.powi.f32(float, i32)
define float @powif(float %F, i32 %power) {
-; CHECK: powif:
+; CHECK-LABEL: powif:
; CHECK: bl __powisf2
%result = call float @llvm.powi.f32(float %F, i32 %power)
ret float %result
}
define double @sin(double %F) {
-; CHECK: sin:
+; CHECK-LABEL: sin:
; CHECK: bl sin
%result = call double @llvm.sin.f64(double %F)
ret double %result
declare float @llvm.sin.f32(float)
define float @sinf(float %F) {
-; CHECK: sinf:
+; CHECK-LABEL: sinf:
; CHECK: bl sinf
%result = call float @llvm.sin.f32(float %F)
ret float %result
}
define double @sqrt(double %F) {
-; CHECK: sqrt:
+; CHECK-LABEL: sqrt:
; CHECK: bl sqrt
%result = call double @llvm.sqrt.f64(double %F)
ret double %result
declare float @llvm.sqrt.f32(float)
define float @sqrtf(float %F) {
-; CHECK: sqrtf:
+; CHECK-LABEL: sqrtf:
; CHECK: bl sqrtf
%result = call float @llvm.sqrt.f32(float %F)
ret float %result
define i32 *@addr_G1() {
entry:
-; CHECK: addr_G1:
+; CHECK-LABEL: addr_G1:
; CHECK: ldaw r0, dp[G1]
ret i32* @G1
}
define i32 *@addr_G2() {
entry:
-; CHECK: addr_G2:
+; CHECK-LABEL: addr_G2:
; CHECK: ldaw r0, dp[G2]
ret i32* @G2
}
define i32 *@addr_G3() {
entry:
-; CHECK: addr_G3:
+; CHECK-LABEL: addr_G3:
; CHECK: ldaw r11, cp[G3]
; CHECK: mov r0, r11
ret i32* @G3
define i32 **@addr_G4() {
entry:
-; CHECK: addr_G4:
+; CHECK-LABEL: addr_G4:
; CHECK: ldaw r0, dp[G4]
ret i32** @G4
}
define i32 **@addr_G5() {
entry:
-; CHECK: addr_G5:
+; CHECK-LABEL: addr_G5:
; CHECK: ldaw r11, cp[G5]
; CHECK: mov r0, r11
ret i32** @G5
define i32 **@addr_G6() {
entry:
-; CHECK: addr_G6:
+; CHECK-LABEL: addr_G6:
; CHECK: ldaw r0, dp[G6]
ret i32** @G6
}
define i32 **@addr_G7() {
entry:
-; CHECK: addr_G7:
+; CHECK-LABEL: addr_G7:
; CHECK: ldaw r11, cp[G7]
; CHECK: mov r0, r11
ret i32** @G7
define i32 *@addr_G8() {
entry:
-; CHECK: addr_G8:
+; CHECK-LABEL: addr_G8:
; CHECK: ldaw r0, dp[G8]
ret i32* @G8
}
@C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
define internal i32 @foo(i32 %i) nounwind {
-; CHECK: foo:
+; CHECK-LABEL: foo:
entry:
%0 = load i8** @nextaddr, align 4 ; <i8*> [#uses=2]
%1 = icmp eq i8* %0, null ; <i1> [#uses=1]
%2 = add i64 %1, %0 ; <i64> [#uses=1]
ret i64 %2
}
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldc r2, 0
; CHECK-NEXT: ladd r1, r0, r1, r0, r2
; CHECK-NEXT: retsp 0
%2 = sub i64 %1, %0 ; <i64> [#uses=1]
ret i64 %2
}
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldc r2, 0
; CHECK-NEXT: lsub r1, r0, r1, r0, r2
; CHECK-NEXT: neg r1, r1
%1 = add i64 %x, %0 ; <i64> [#uses=1]
ret i64 %1
}
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ldc r3, 0
; CHECK-NEXT: ladd r2, r0, r0, r2, r3
; CHECK-NEXT: add r1, r1, r2
%1 = add i64 %0, %y ; <i64> [#uses=1]
ret i64 %1
}
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ldc r3, 0
; CHECK-NEXT: ladd r1, r0, r0, r1, r3
; CHECK-NEXT: add r1, r2, r1
%1 = sub i64 %x, %0 ; <i64> [#uses=1]
ret i64 %1
}
-; CHECK: f5:
+; CHECK-LABEL: f5:
; CHECK: ldc r3, 0
; CHECK-NEXT: lsub r2, r0, r0, r2, r3
; CHECK-NEXT: sub r1, r1, r2
; MachineLICM should hoist the LDWCP out of the loop.
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK-NEXT: ldw [[REG:r[0-9]+]], cp[.LCPI0_0]
; CHECK-NEXT: .LBB0_1:
; CHECK-NEXT: stw [[REG]], r0[0]
define i32 @load32(i32* %p, i32 %offset) nounwind {
entry:
-; CHECK: load32:
+; CHECK-LABEL: load32:
; CHECK: ldw r0, r0[r1]
%0 = getelementptr i32* %p, i32 %offset
%1 = load i32* %0, align 4
define i32 @load32_imm(i32* %p) nounwind {
entry:
-; CHECK: load32_imm:
+; CHECK-LABEL: load32_imm:
; CHECK: ldw r0, r0[11]
%0 = getelementptr i32* %p, i32 11
%1 = load i32* %0, align 4
define i32 @load16(i16* %p, i32 %offset) nounwind {
entry:
-; CHECK: load16:
+; CHECK-LABEL: load16:
; CHECK: ld16s r0, r0[r1]
; CHECK-NOT: sext
%0 = getelementptr i16* %p, i32 %offset
define i32 @load8(i8* %p, i32 %offset) nounwind {
entry:
-; CHECK: load8:
+; CHECK-LABEL: load8:
; CHECK: ld8u r0, r0[r1]
; CHECK-NOT: zext
%0 = getelementptr i8* %p, i32 %offset
@GConst = external constant i32
define i32 @load_cp() nounwind {
entry:
-; CHECK: load_cp:
+; CHECK-LABEL: load_cp:
; CHECK: ldw r0, cp[GConst]
%0 = load i32* @GConst
ret i32 %0
declare i32 @llvm.xcore.getet()
define i32 @bitrev(i32 %val) {
-; CHECK: bitrev:
+; CHECK-LABEL: bitrev:
; CHECK: bitrev r0, r0
%result = call i32 @llvm.xcore.bitrev(i32 %val)
ret i32 %result
}
define i32 @crc32(i32 %crc, i32 %data, i32 %poly) {
-; CHECK: crc32:
+; CHECK-LABEL: crc32:
; CHECK: crc32 r0, r1, r2
%result = call i32 @llvm.xcore.crc32(i32 %crc, i32 %data, i32 %poly)
ret i32 %result
}
define %0 @crc8(i32 %crc, i32 %data, i32 %poly) {
-; CHECK: crc8:
+; CHECK-LABEL: crc8:
; CHECK: crc8 r0, r1, r1, r2
%result = call %0 @llvm.xcore.crc8(i32 %crc, i32 %data, i32 %poly)
ret %0 %result
}
define i32 @zext(i32 %a, i32 %b) {
-; CHECK: zext:
+; CHECK-LABEL: zext:
; CHECK: zext r0, r1
%result = call i32 @llvm.xcore.zext(i32 %a, i32 %b)
ret i32 %result
}
define i32 @zexti(i32 %a) {
-; CHECK: zexti:
+; CHECK-LABEL: zexti:
; CHECK: zext r0, 4
%result = call i32 @llvm.xcore.zext(i32 %a, i32 4)
ret i32 %result
}
define i32 @sext(i32 %a, i32 %b) {
-; CHECK: sext:
+; CHECK-LABEL: sext:
; CHECK: sext r0, r1
%result = call i32 @llvm.xcore.sext(i32 %a, i32 %b)
ret i32 %result
}
define i32 @sexti(i32 %a) {
-; CHECK: sexti:
+; CHECK-LABEL: sexti:
; CHECK: sext r0, 4
%result = call i32 @llvm.xcore.sext(i32 %a, i32 4)
ret i32 %result
}
define i32 @geted() {
-; CHECK: geted:
+; CHECK-LABEL: geted:
; CHECK: get r11, ed
; CHECK-NEXT: mov r0, r11
%result = call i32 @llvm.xcore.geted()
}
define i32 @getet() {
-; CHECK: getet:
+; CHECK-LABEL: getet:
; CHECK: get r11, et
; CHECK-NEXT: mov r0, r11
%result = call i32 @llvm.xcore.getet()
; RUN: llc < %s -march=xcore | FileCheck %s
define i32 @f(i32) nounwind {
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: mkmsk r0, r0
; CHECK-NEXT: retsp 0
entry:
%2 = mul i64 %1, %0
ret i64 %2
}
-; CHECK: umul_lohi:
+; CHECK-LABEL: umul_lohi:
; CHECK: ldc [[REG:r[0-9]+]], 0
; CHECK-NEXT: lmul {{.*}}, [[REG]], [[REG]]
; CHECK-NEXT: retsp 0
%2 = mul i64 %1, %0
ret i64 %2
}
-; CHECK: smul_lohi:
+; CHECK-LABEL: smul_lohi:
; CHECK: ldc
; CHECK-NEXT: mov
; CHECK-NEXT: maccs
%0 = mul i64 %a, %b
ret i64 %0
}
-; CHECK: mul64:
+; CHECK-LABEL: mul64:
; CHECK: ldc
; CHECK-NEXT: lmul
; CHECK-NEXT: mul
%1 = mul i64 %a, %0
ret i64 %1
}
-; CHECK: mul64_2:
+; CHECK-LABEL: mul64_2:
; CHECK: ldc
; CHECK-NEXT: lmul
; CHECK-NEXT: mul
define i32 *@f1() nounwind {
entry:
-; CHECK: f1:
+; CHECK-LABEL: f1:
; CHECK: ldaw r11, cp[a+4]
; CHECK: mov r0, r11
%0 = getelementptr [0 x i32]* @a, i32 0, i32 1
define i32 *@f2() nounwind {
entry:
-; CHECK: f2:
+; CHECK-LABEL: f2:
; CHECK: ldaw r0, dp[b+4]
%0 = getelementptr [0 x i32]* @b, i32 0, i32 1
ret i32* %0
define i32 *@f3() nounwind {
entry:
-; CHECK: f3:
+; CHECK-LABEL: f3:
; CHECK: ldaw r11, cp[a]
; CHECK: sub r0, r11, 4
%0 = getelementptr [0 x i32]* @a, i32 0, i32 -1
define i32 *@f4() nounwind {
entry:
-; CHECK: f4:
+; CHECK-LABEL: f4:
; CHECK: ldaw [[REG:r[0-9]+]], dp[b]
; CHECK: sub r0, [[REG]], 4
%0 = getelementptr [0 x i32]* @b, i32 0, i32 -1
@baz = private global i32 4
define i32 @bar() {
-; CHECK: bar:
+; CHECK-LABEL: bar:
; CHECK: bl .Lfoo
; CHECK: ldw r0, dp[.Lbaz]
call void @foo()
declare void @llvm.xcore.setps(i32, i32)
define i32 @getps(i32 %reg) nounwind {
-; CHECK: getps:
+; CHECK-LABEL: getps:
; CHECK: get r0, ps[r0]
%result = call i32 @llvm.xcore.getps(i32 %reg)
ret i32 %result
define void @setps(i32 %reg, i32 %value) nounwind {
-; CHECK: setps:
+; CHECK-LABEL: setps:
; CHECK: set ps[r0], r1
call void @llvm.xcore.setps(i32 %reg, i32 %value)
ret void
declare i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
define i8 addrspace(1)* @getr() {
-; CHECK: getr:
+; CHECK-LABEL: getr:
; CHECK: getr r0, 5
%result = call i8 addrspace(1)* @llvm.xcore.getr.p1i8(i32 5)
ret i8 addrspace(1)* %result
}
define void @freer(i8 addrspace(1)* %r) {
-; CHECK: freer:
+; CHECK-LABEL: freer:
; CHECK: freer res[r0]
call void @llvm.xcore.freer.p1i8(i8 addrspace(1)* %r)
ret void
}
define i32 @in(i8 addrspace(1)* %r) {
-; CHECK: in:
+; CHECK-LABEL: in:
; CHECK: in r0, res[r0]
%result = call i32 @llvm.xcore.in.p1i8(i8 addrspace(1)* %r)
ret i32 %result
}
define i32 @int(i8 addrspace(1)* %r) {
-; CHECK: int:
+; CHECK-LABEL: int:
; CHECK: int r0, res[r0]
%result = call i32 @llvm.xcore.int.p1i8(i8 addrspace(1)* %r)
ret i32 %result
}
define i32 @inct(i8 addrspace(1)* %r) {
-; CHECK: inct:
+; CHECK-LABEL: inct:
; CHECK: inct r0, res[r0]
%result = call i32 @llvm.xcore.inct.p1i8(i8 addrspace(1)* %r)
ret i32 %result
}
define void @out(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: out:
+; CHECK-LABEL: out:
; CHECK: out res[r0], r1
call void @llvm.xcore.out.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void
}
define void @outt(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: outt:
+; CHECK-LABEL: outt:
; CHECK: outt res[r0], r1
call void @llvm.xcore.outt.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void
}
define void @outct(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: outct:
+; CHECK-LABEL: outct:
; CHECK: outct res[r0], r1
call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void
}
define void @outcti(i8 addrspace(1)* %r) {
-; CHECK: outcti:
+; CHECK-LABEL: outcti:
; CHECK: outct res[r0], 11
call void @llvm.xcore.outct.p1i8(i8 addrspace(1)* %r, i32 11)
ret void
}
define void @chkct(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: chkct:
+; CHECK-LABEL: chkct:
; CHECK: chkct res[r0], r1
call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void
}
define void @chkcti(i8 addrspace(1)* %r) {
-; CHECK: chkcti:
+; CHECK-LABEL: chkcti:
; CHECK: chkct res[r0], 11
call void @llvm.xcore.chkct.p1i8(i8 addrspace(1)* %r, i32 11)
ret void
}
define void @setd(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setd:
+; CHECK-LABEL: setd:
; CHECK: setd res[r0], r1
call void @llvm.xcore.setd.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void
}
define void @setc(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setc:
+; CHECK-LABEL: setc:
; CHECK: setc res[r0], r1
call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void
}
define void @setci(i8 addrspace(1)* %r) {
-; CHECK: setci:
+; CHECK-LABEL: setci:
; CHECK: setc res[r0], 2
call void @llvm.xcore.setc.p1i8(i8 addrspace(1)* %r, i32 2)
ret void
}
define i32 @inshr(i32 %value, i8 addrspace(1)* %r) {
-; CHECK: inshr:
+; CHECK-LABEL: inshr:
; CHECK: inshr r0, res[r1]
%result = call i32 @llvm.xcore.inshr.p1i8(i8 addrspace(1)* %r, i32 %value)
ret i32 %result
}
define i32 @outshr(i32 %value, i8 addrspace(1)* %r) {
-; CHECK: outshr:
+; CHECK-LABEL: outshr:
; CHECK: outshr res[r1], r0
%result = call i32 @llvm.xcore.outshr.p1i8(i8 addrspace(1)* %r, i32 %value)
ret i32 %result
}
define void @setpt(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: setpt:
+; CHECK-LABEL: setpt:
; CHECK: setpt res[r0], r1
call void @llvm.xcore.setpt.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void
}
define i32 @getts(i8 addrspace(1)* %r) {
-; CHECK: getts:
+; CHECK-LABEL: getts:
; CHECK: getts r0, res[r0]
%result = call i32 @llvm.xcore.getts.p1i8(i8 addrspace(1)* %r)
ret i32 %result
}
define void @syncr(i8 addrspace(1)* %r) {
-; CHECK: syncr:
+; CHECK-LABEL: syncr:
; CHECK: syncr res[r0]
call void @llvm.xcore.syncr.p1i8(i8 addrspace(1)* %r)
ret void
}
define void @settw(i8 addrspace(1)* %r, i32 %value) {
-; CHECK: settw:
+; CHECK-LABEL: settw:
; CHECK: settw res[r0], r1
call void @llvm.xcore.settw.p1i8(i8 addrspace(1)* %r, i32 %value)
ret void
}
define void @setv(i8 addrspace(1)* %r, i8* %p) {
-; CHECK: setv:
+; CHECK-LABEL: setv:
; CHECK: mov r11, r1
; CHECK-NEXT: setv res[r0], r11
call void @llvm.xcore.setv.p1i8(i8 addrspace(1)* %r, i8* %p)
}
define void @setev(i8 addrspace(1)* %r, i8* %p) {
-; CHECK: setev:
+; CHECK-LABEL: setev:
; CHECK: mov r11, r1
; CHECK-NEXT: setev res[r0], r11
call void @llvm.xcore.setev.p1i8(i8 addrspace(1)* %r, i8* %p)
}
define void @eeu(i8 addrspace(1)* %r) {
-; CHECK: eeu:
+; CHECK-LABEL: eeu:
; CHECK: eeu res[r0]
call void @llvm.xcore.eeu.p1i8(i8 addrspace(1)* %r)
ret void
}
define i32 @peek(i8 addrspace(1)* %r) {
-; CHECK: peek:
+; CHECK-LABEL: peek:
; CHECK: peek r0, res[r0]
%result = call i32 @llvm.xcore.peek.p1i8(i8 addrspace(1)* %r)
ret i32 %result
}
define i32 @endin(i8 addrspace(1)* %r) {
-; CHECK: endin:
+; CHECK-LABEL: endin:
; CHECK: endin r0, res[r0]
%result = call i32 @llvm.xcore.endin.p1i8(i8 addrspace(1)* %r)
ret i32 %result
%2 = sext i1 %1 to i32
ret i32 %2
}
-; CHECK: sext1:
+; CHECK-LABEL: sext1:
; CHECK: sext r0, 1
define i32 @sext2(i32 %a) {
%2 = sext i2 %1 to i32
ret i32 %2
}
-; CHECK: sext2:
+; CHECK-LABEL: sext2:
; CHECK: sext r0, 2
define i32 @sext8(i32 %a) {
%2 = sext i8 %1 to i32
ret i32 %2
}
-; CHECK: sext8:
+; CHECK-LABEL: sext8:
; CHECK: sext r0, 8
define i32 @sext16(i32 %a) {
%2 = sext i16 %1 to i32
ret i32 %2
}
-; CHECK: sext16:
+; CHECK-LABEL: sext16:
; CHECK: sext r0, 16
declare void @llvm.xcore.clrsr(i32)
define void @setsr() nounwind {
-; CHECK: setsr:
+; CHECK-LABEL: setsr:
; CHECK: setsr 128
call void @llvm.xcore.setsr(i32 128)
ret void
define void @clrsr() nounwind {
-; CHECK: clrsr:
+; CHECK-LABEL: clrsr:
; CHECK: clrsr 128
call void @llvm.xcore.clrsr(i32 128)
ret void
define void @store32(i32* %p, i32 %offset, i32 %val) nounwind {
entry:
-; CHECK: store32:
+; CHECK-LABEL: store32:
; CHECK: stw r2, r0[r1]
%0 = getelementptr i32* %p, i32 %offset
store i32 %val, i32* %0, align 4
define void @store32_imm(i32* %p, i32 %val) nounwind {
entry:
-; CHECK: store32_imm:
+; CHECK-LABEL: store32_imm:
; CHECK: stw r1, r0[11]
%0 = getelementptr i32* %p, i32 11
store i32 %val, i32* %0, align 4
define void @store16(i16* %p, i32 %offset, i16 %val) nounwind {
entry:
-; CHECK: store16:
+; CHECK-LABEL: store16:
; CHECK: st16 r2, r0[r1]
%0 = getelementptr i16* %p, i32 %offset
store i16 %val, i16* %0, align 2
define void @store8(i8* %p, i32 %offset, i8 %val) nounwind {
entry:
-; CHECK: store8:
+; CHECK-LABEL: store8:
; CHECK: st8 r2, r0[r1]
%0 = getelementptr i8* %p, i32 %offset
store i8 %val, i8* %0, align 1
declare void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %r, i8* %value)
define i8 addrspace(1)* @getst(i8 addrspace(1)* %r) {
-; CHECK: getst:
+; CHECK-LABEL: getst:
; CHECK: getst r0, res[r0]
%result = call i8 addrspace(1)* @llvm.xcore.getst.p1i8.p1i8(i8 addrspace(1)* %r)
ret i8 addrspace(1)* %result
}
define void @ssync() {
-; CHECK: ssync:
+; CHECK-LABEL: ssync:
; CHECK: ssync
call void @llvm.xcore.ssync()
ret void
}
define void @mjoin(i8 addrspace(1)* %r) {
-; CHECK: mjoin:
+; CHECK-LABEL: mjoin:
; CHECK: mjoin res[r0]
call void @llvm.xcore.mjoin.p1i8(i8 addrspace(1)* %r)
ret void
}
define void @initsp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initsp:
+; CHECK-LABEL: initsp:
; CHECK: init t[r0]:sp, r1
call void @llvm.xcore.initsp.p1i8(i8 addrspace(1)* %t, i8* %src)
ret void
}
define void @initpc(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initpc:
+; CHECK-LABEL: initpc:
; CHECK: init t[r0]:pc, r1
call void @llvm.xcore.initpc.p1i8(i8 addrspace(1)* %t, i8* %src)
ret void
}
define void @initlr(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initlr:
+; CHECK-LABEL: initlr:
; CHECK: init t[r0]:lr, r1
call void @llvm.xcore.initlr.p1i8(i8 addrspace(1)* %t, i8* %src)
ret void
}
define void @initcp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initcp:
+; CHECK-LABEL: initcp:
; CHECK: init t[r0]:cp, r1
call void @llvm.xcore.initcp.p1i8(i8 addrspace(1)* %t, i8* %src)
ret void
}
define void @initdp(i8 addrspace(1)* %t, i8* %src) {
-; CHECK: initdp:
+; CHECK-LABEL: initdp:
; CHECK: init t[r0]:dp, r1
call void @llvm.xcore.initdp.p1i8(i8 addrspace(1)* %t, i8* %src)
ret void
define i32 *@addr_G() {
entry:
-; CHECK: addr_G:
+; CHECK-LABEL: addr_G:
; CHECK: get r11, id
ret i32* @G
}
define void @f() nounwind {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: ldap r11, g.1101
; CHECK: stw r11, sp[7]
%TRAMP.23 = alloca [20 x i8], align 2
}
; Half word aligned load.
-; CHECK: align2:
+; CHECK-LABEL: align2:
; CHECK: ld16s
; CHECK: ld16s
; CHECK: or
@a = global [5 x i8] zeroinitializer, align 4
; Constant offset from word aligned base.
-; CHECK: align3:
+; CHECK-LABEL: align3:
; CHECK: ldw {{r[0-9]+}}, dp
; CHECK: ldw {{r[0-9]+}}, dp
; CHECK: or
; RUN: llc < %s -march=xcore | FileCheck %s
; Byte aligned store.
-; CHECK: align1:
+; CHECK-LABEL: align1:
; CHECK: bl __misaligned_store
define void @align1(i32* %p, i32 %val) nounwind {
entry:
; of size 8
define void @f(i64* %dst, i64* %src) nounwind {
entry:
-; CHECK: f:
+; CHECK-LABEL: f:
; CHECK: ldc r2, 8
; CHECK: bl memmove
%0 = load i64* %src, align 1
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