Update testcase to be more careful about checking register
values. While regexes are general goodness for these sorts of
testcases, in this example, the registers are constrained by
the calling convention, so we can and should check their
explicit values.
rdar://
14779513
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188819
91177308-0d34-0410-b5e6-
96231b3b80d8
}
unsigned ResultReg = createResultReg(RC);
if (!UseImm) {
- Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 1);
+ Op2Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op2Reg, 1);
Op1Reg = constrainOperandRegClass(TII.get(MovCCOpc), Op1Reg, 2);
BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg)
.addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR);
entry:
; ARM: t3
; ARM: cmp r0, #0
-; ARM: movne r{{[1-9]}}, r{{[1-9]}}
-; ARM: mov r0, r{{[1-9]}}
+; ARM: movne r2, r1
+; ARM: add r0, r2, r1
; THUMB: t3
; THUMB: cmp r0, #0
; THUMB: it ne
-; THUMB: movne r{{[1-9]}}, r{{[1-9]}}
-; THUMB: mov r0, r{{[1-9]}}
+; THUMB: movne r2, r1
+; THUMB: add.w r0, r2, r1
%0 = select i1 %c, i32 %a, i32 %b
- ret i32 %0
+ %1 = add i32 %0, %a
+ ret i32 %1
}
define i32 @t4(i1 %c) nounwind readnone {