Add support for the 'x' constraint.

Part of rdar://9307836 and rdar://9119939

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134215 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index 7828447875cdc8d2e21ab8fba4629c37ffd18be2..22cd78f80bbf92b63c946a2f03ba9ff0642a10ad 100644 (file)
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -7483,6 +7483,7 @@ ARMTargetLowering::getConstraintType(const std::string &Constraint) const {
     case 'l': return C_RegisterClass;
     case 'w': return C_RegisterClass;
     case 'h': return C_RegisterClass;
+    case 'x': return C_RegisterClass;
     }
   } else if (Constraint.size() == 2) {
     switch (Constraint[0]) {
@@ -7555,6 +7556,14 @@ ARMTargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
       if (VT.getSizeInBits() == 128)
         return RCPair(0U, ARM::QPRRegisterClass);
       break;
+    case 'x':
+      if (VT == MVT::f32)
+       return RCPair(0U, ARM::SPR_8RegisterClass);
+      if (VT.getSizeInBits() == 64)
+       return RCPair(0U, ARM::DPR_8RegisterClass);
+      if (VT.getSizeInBits() == 128)
+       return RCPair(0U, ARM::QPR_8RegisterClass);
+      break;
     }
   }
   if (StringRef("{cc}").equals_lower(Constraint))

diff --git a/test/CodeGen/ARM/inlineasm3.ll b/test/CodeGen/ARM/inlineasm3.ll
index 58687b9692463ef28379c2c564c0b9468240c890..f09deb39f8c8a2d0bae9bd5f790d37461151e904 100644 (file)
--- a/test/CodeGen/ARM/inlineasm3.ll
+++ b/test/CodeGen/ARM/inlineasm3.ll
@@ -58,3 +58,13 @@ entry:
 call void asm sideeffect "flds s15, $0 \0A", "*^Uvm,~{s15}"(float* @k.2126) nounwind
 ret i32 0
 }
+
+; Radar 9307836 & 9119939
+
+define float @t6(float %y) nounwind {
+entry:
+; CHECK: t6
+; CHECK: flds s15, s0
+  %0 = tail call float asm "flds s15, $0", "=x"() nounwind
+  ret float %0
+}