}
else //single lvds channel
{
+ val = 0;
val &= ~(LVDS_CH0TTL_EN | LVDS_CH1TTL_EN | LVDS_CH1_PWR_EN | LVDS_PLL_PWR_DN | LVDS_CH_SEL); //use channel 0
val |= (LVDS_CH0_PWR_EN) |(LVDS_CBG_PWR_EN) | (LVDS_OUT_FORMAT(screen->hw_format)) |
- (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH0_PWR_EN << 16) |
- (LVDS_CBG_PWR_EN << 16)|(LVDS_CH_SEL << 16) | (LVDS_PLL_PWR_DN << 16)|
- (LVDS_OUT_FORMAT_MASK);
+ (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH0_PWR_EN << 16) |
+ (LVDS_DCLK_INV ) | (LVDS_CH0TTL_EN << 16) | (LVDS_CH1TTL_EN << 16) |(LVDS_CH0_PWR_EN << 16) |
+ (LVDS_CBG_PWR_EN << 16)|(LVDS_CH_SEL << 16) | (LVDS_PLL_PWR_DN << 16)|
+ (LVDS_OUT_FORMAT_MASK) | (LVDS_DCLK_INV << 16);
ret = rk616->write_dev(rk616,CRU_LVDS_CON0,&val);
-
+
dev_info(rk616->dev,"rk616 use single lvds channel.......\n");
+
}
}
#define VIF1_CLK_DIV_MASK (7<<25)
#define VIF0_CLK_DIV_MASK (7<<19)
#define SCLIN_CLK_SEL (1<<15)
+#define SCL_SEL_VIF0 0
+#define SCL_SEL_VIF1 1
#define DITHER_CLK_SEL (1<<14)
+#define DITHER_SEL_VIF0 0
+#define DITHER_SEL_SCL 1
+
#define HDMI_CLK_SEL(x) (((x)&3)<<12)
#define VIF1_CLK_DIV(x) (((x)&7)<<9)
#define VIF1_CLK_GATE (1<<8)
#define PLL1_FOUTVCO_PWR_DN (1<<26)
#define PLL1_POSTDIV_PWR_DN (1<<25)
#define PLL1_DAC_PWR_DN (1<<24)
-#define PLL1_FRAC(x) (((x)&0xffffff)<0)
+#define PLL1_FRAC(x) (((x)&0xffffff)<<0)
#define CRU_I2C_CON0 0x0080