rk3188: fix uart0 init 49.5MHz error, set uart0 = 48MHz

diff --git a/arch/arm/mach-rk3188/clock_data.c b/arch/arm/mach-rk3188/clock_data.c
index c04177a7b4b90d197334de898684d7b4179ffaa5..757098415340d409d50db079a6c75d1e13143d34 100755 (executable)
--- a/arch/arm/mach-rk3188/clock_data.c
+++ b/arch/arm/mach-rk3188/clock_data.c
@@ -3553,7 +3553,7 @@ static void __init rk30_clock_common_init(unsigned long gpll_rate, unsigned long
        clk_set_parent_nolock(&aclk_gpu, &general_pll_clk);
        clk_set_rate_nolock(&aclk_gpu, 200 * MHZ);
        
-       clk_set_rate_nolock(&clk_uart0, 49500000);
+       clk_set_rate_nolock(&clk_uart0, 48000000);
        clk_set_rate_nolock(&clk_sdmmc, 24750000);
        clk_set_rate_nolock(&clk_sdio, 24750000);
 }