powerpc/eeh: EEH backend for P7IOC
authorGavin Shan <shangw@linux.vnet.ibm.com>
Thu, 20 Jun 2013 05:21:06 +0000 (13:21 +0800)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Thu, 20 Jun 2013 07:06:20 +0000 (17:06 +1000)
For EEH on PowerNV platform, the overall architecture is different
from that on pSeries platform. In order to support multiple I/O chips
in future, we split EEH to 3 layers for PowerNV platform: EEH core,
platform layer, I/O layer. It would give EEH implementation on PowerNV
platform much more flexibility in future.

The patch adds the EEH backend for P7IOC.

Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/platforms/powernv/Makefile
arch/powerpc/platforms/powernv/eeh-ioda.c [new file with mode: 0644]
arch/powerpc/platforms/powernv/pci.h

index bcc3cb48a44ee341dc7fb871387ff3cf391fe90a..09bd0cbb7c4fc122f82928ca34723508153701aa 100644 (file)
@@ -3,3 +3,4 @@ obj-y                   += opal-rtc.o opal-nvram.o
 
 obj-$(CONFIG_SMP)      += smp.o
 obj-$(CONFIG_PCI)      += pci.o pci-p5ioc2.o pci-ioda.o
+obj-$(CONFIG_EEH)      += eeh-ioda.o
diff --git a/arch/powerpc/platforms/powernv/eeh-ioda.c b/arch/powerpc/platforms/powernv/eeh-ioda.c
new file mode 100644 (file)
index 0000000..f12e888
--- /dev/null
@@ -0,0 +1,45 @@
+/*
+ * The file intends to implement the functions needed by EEH, which is
+ * built on IODA compliant chip. Actually, lots of functions related
+ * to EEH would be built based on the OPAL APIs.
+ *
+ * Copyright Benjamin Herrenschmidt & Gavin Shan, IBM Corporation 2013.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/bootmem.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/msi.h>
+#include <linux/pci.h>
+#include <linux/string.h>
+
+#include <asm/eeh.h>
+#include <asm/eeh_event.h>
+#include <asm/io.h>
+#include <asm/iommu.h>
+#include <asm/msi_bitmap.h>
+#include <asm/opal.h>
+#include <asm/pci-bridge.h>
+#include <asm/ppc-pci.h>
+#include <asm/tce.h>
+
+#include "powernv.h"
+#include "pci.h"
+
+struct pnv_eeh_ops ioda_eeh_ops = {
+       .post_init              = NULL,
+       .set_option             = NULL,
+       .get_state              = NULL,
+       .reset                  = NULL,
+       .get_log                = NULL,
+       .configure_bridge       = NULL,
+       .next_error             = NULL
+};
index 25d76c4df50b27711c6bd1bb40481216a7009eb6..336c9dc1b314f424591d762c92ab013b46a9162a 100644 (file)
@@ -66,15 +66,35 @@ struct pnv_ioda_pe {
        struct list_head        list;
 };
 
+/* IOC dependent EEH operations */
+#ifdef CONFIG_EEH
+struct pnv_eeh_ops {
+       int (*post_init)(struct pci_controller *hose);
+       int (*set_option)(struct eeh_pe *pe, int option);
+       int (*get_state)(struct eeh_pe *pe);
+       int (*reset)(struct eeh_pe *pe, int option);
+       int (*get_log)(struct eeh_pe *pe, int severity,
+                      char *drv_log, unsigned long len);
+       int (*configure_bridge)(struct eeh_pe *pe);
+       int (*next_error)(struct eeh_pe **pe);
+};
+#endif /* CONFIG_EEH */
+
 struct pnv_phb {
        struct pci_controller   *hose;
        enum pnv_phb_type       type;
        enum pnv_phb_model      model;
+       u64                     hub_id;
        u64                     opal_id;
        void __iomem            *regs;
        int                     initialized;
        spinlock_t              lock;
 
+#ifdef CONFIG_EEH
+       struct pnv_eeh_ops      *eeh_ops;
+       int                     eeh_enabled;
+#endif
+
 #ifdef CONFIG_PCI_MSI
        unsigned int            msi_base;
        unsigned int            msi32_support;
@@ -150,6 +170,9 @@ struct pnv_phb {
 };
 
 extern struct pci_ops pnv_pci_ops;
+#ifdef CONFIG_EEH
+extern struct pnv_eeh_ops ioda_eeh_ops;
+#endif
 
 extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
                                      void *tce_mem, u64 tce_size,