[ARM64] Tighten up the special casing in emitting arithmetic extends. UXTW should...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@205886 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
index d17182da7619f8bba0e1672ef7b5ce0d55d6ac14..7d1dd50b720bb5bd5597cd8996a99b57a1c3ce4b 100644 (file)
--- a/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
+++ b/lib/Target/ARM64/InstPrinter/ARM64InstPrinter.cpp
@@ -1097,8 +1097,10 @@ void ARM64InstPrinter::printExtend(const MCInst *MI, unsigned OpNum,
   if (ExtType == ARM64_AM::UXTW || ExtType == ARM64_AM::UXTX) {
     unsigned Dest = MI->getOperand(0).getReg();
     unsigned Src1 = MI->getOperand(1).getReg();
-    if (Dest == ARM64::SP || Dest == ARM64::WSP || Src1 == ARM64::SP ||
-        Src1 == ARM64::WSP) {
+    if ( ((Dest == ARM64::SP || Src1 == ARM64::SP) &&
+          ExtType == ARM64_AM::UXTX) ||
+         ((Dest == ARM64::WSP || Src1 == ARM64::WSP) &&
+          ExtType == ARM64_AM::UXTW) ) {
       if (ShiftVal != 0)
         O << ", lsl #" << ShiftVal;
       return;

diff --git a/test/MC/ARM64/arithmetic-encoding.s b/test/MC/ARM64/arithmetic-encoding.s
index 3177ca49ee0fefbac8a04e07db0e921058d76456..6d28bce5a830687a50ded9ccf5bd1e5506b3276a 100644 (file)
--- a/test/MC/ARM64/arithmetic-encoding.s
+++ b/test/MC/ARM64/arithmetic-encoding.s
@@ -368,8 +368,8 @@ foo:
 ; CHECK: subs x3, sp, x9, lsl #2     ; encoding: [0xe3,0x6b,0x29,0xeb]
 ; CHECK: cmp wsp, w8                 ; encoding: [0xff,0x43,0x28,0x6b]
 ; CHECK: cmp wsp, w8                 ; encoding: [0xff,0x43,0x28,0x6b]
-; CHECK: cmp sp, w8                  ; encoding: [0xff,0x43,0x28,0xeb]
-; CHECK: cmp sp, w8                  ; encoding: [0xff,0x43,0x28,0xeb]
+; CHECK: cmp sp, w8, uxtw            ; encoding: [0xff,0x43,0x28,0xeb]
+; CHECK: cmp sp, w8, uxtw            ; encoding: [0xff,0x43,0x28,0xeb]
 
   sub wsp, w9, w8, uxtw
   sub w1, wsp, w8, uxtw
@@ -383,11 +383,11 @@ foo:
 ; CHECK: sub wsp, w9, w8             ; encoding: [0x3f,0x41,0x28,0x4b]
 ; CHECK: sub w1, wsp, w8             ; encoding: [0xe1,0x43,0x28,0x4b]
 ; CHECK: sub wsp, wsp, w8            ; encoding: [0xff,0x43,0x28,0x4b]
-; CHECK: sub sp, x9, w8              ; encoding: [0x3f,0x41,0x28,0xcb]
-; CHECK: sub x1, sp, w8              ; encoding: [0xe1,0x43,0x28,0xcb]
-; CHECK: sub sp, sp, w8              ; encoding: [0xff,0x43,0x28,0xcb]
+; CHECK: sub sp, x9, w8, uxtw        ; encoding: [0x3f,0x41,0x28,0xcb]
+; CHECK: sub x1, sp, w8, uxtw        ; encoding: [0xe1,0x43,0x28,0xcb]
+; CHECK: sub sp, sp, w8, uxtw        ; encoding: [0xff,0x43,0x28,0xcb]
 ; CHECK: subs w1, wsp, w8            ; encoding: [0xe1,0x43,0x28,0x6b]
-; CHECK: subs x1, sp, w8             ; encoding: [0xe1,0x43,0x28,0xeb]
+; CHECK: subs x1, sp, w8, uxtw       ; encoding: [0xe1,0x43,0x28,0xeb]
 
 ;==---------------------------------------------------------------------------==
 ; Signed/Unsigned divide