ARM: EXYNOS: apply S5P_CENTRAL_SEQ_OPTION fix only when necessary
authorBartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Sat, 24 Jan 2015 05:05:50 +0000 (14:05 +0900)
committerKukjin Kim <kgene@kernel.org>
Thu, 29 Jan 2015 23:38:52 +0000 (08:38 +0900)
Commit c2dd114d2486 ("ARM: EXYNOS: fix register setup for AFTR mode
code") added S5P_CENTRAL_SEQ_OPTION register setup fix for all
Exynos SoCs to AFTR mode code-path.  It turned out that for coupled
cpuidle AFTR mode on Exynos4210 (added by the next patch) applying
this fix causes lockup so enable it in the AFTR mode code-path only
on SoCs that require it (in the suspend code-path it can be always
applied like it was before commit c2dd114d2486 ("ARM: EXYNOS: fix
register setup for AFTR mode code")

Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Colin Cross <ccross@google.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
arch/arm/mach-exynos/pm.c
arch/arm/mach-exynos/suspend.c

index 86f3ecd88f78f92c492e23b2043902b290f2dc2c..159eb4c9779e06db65341dea2b05b0a3e64dede2 100644 (file)
@@ -97,10 +97,6 @@ void exynos_pm_central_suspend(void)
        tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
        tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
        pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
-
-       /* Setting SEQ_OPTION register */
-       pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
-                      S5P_CENTRAL_SEQ_OPTION);
 }
 
 int exynos_pm_central_resume(void)
@@ -164,6 +160,13 @@ void exynos_enter_aftr(void)
 
        exynos_pm_central_suspend();
 
+       if (of_machine_is_compatible("samsung,exynos4212") ||
+           of_machine_is_compatible("samsung,exynos4412")) {
+               /* Setting SEQ_OPTION register */
+               pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
+                              S5P_CENTRAL_SEQ_OPTION);
+       }
+
        cpu_suspend(0, exynos_aftr_finisher);
 
        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
index f8e7dcd1705529d52cd3c4c4c3b9cf609ae92e34..9c67a15f4a0fb72e15b062dc4b8af4b60094fa07 100644 (file)
@@ -282,6 +282,10 @@ static int exynos_pm_suspend(void)
 {
        exynos_pm_central_suspend();
 
+       /* Setting SEQ_OPTION register */
+       pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
+                      S5P_CENTRAL_SEQ_OPTION);
+
        if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
                exynos_cpu_save_register();