Wrap long lines.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15915 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/Target/PowerPC/PPC64RegisterInfo.cpp b/lib/Target/PowerPC/PPC64RegisterInfo.cpp
index e30613041d65d87f05173de8a11cef60997f926d..b394568acd9f90115e54dd7ae06f5d86799ce14c 100644 (file)
--- a/lib/Target/PowerPC/PPC64RegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPC64RegisterInfo.cpp
@@ -72,11 +72,10 @@ void
 PPC64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                        MachineBasicBlock::iterator MI,
                                        unsigned SrcReg, int FrameIdx) const {
-  const TargetRegisterClass *RC = getRegClass(SrcReg);
   static const unsigned Opcode[] = { 
     PPC::STB, PPC::STH, PPC::STW, PPC::STD, PPC::STFS, PPC::STFD 
   };
-
+  const TargetRegisterClass *RC = getRegClass(SrcReg);
   unsigned OC = Opcode[getIdx(RC)];
   if (SrcReg == PPC::LR) {
     BuildMI(MBB, MI, PPC::MFLR, 0, PPC::R11);
@@ -204,13 +203,15 @@ PPC64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
     // convert into indexed form of the instruction
     // sth 0:rA, 1:imm 2:(rB) ==> sthx 0:rA, 2:rB, 1:r0
     // addi 0:rA 1:rB, 2, imm ==> add 0:rA, 1:rB, 2:r0
-    unsigned NewOpcode = const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
+    unsigned NewOpcode = 
+      const_cast<std::map<unsigned, unsigned>& >(ImmToIdxMap)[MI.getOpcode()];
     assert(NewOpcode && "No indexed form of load or store available!");
     MI.setOpcode(NewOpcode);
     MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
     MI.SetMachineOperandReg(2, PPC::R0);
   } else {
-    MI.SetMachineOperandConst(OffIdx,MachineOperand::MO_SignExtendedImmed,Offset);
+    MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_SignExtendedImmed,
+                              Offset);
   }
 }