rockchip:mali400:enable mali400 irq and resource address in rk3036.dtsi
authorxxm <xxm@rock-chips.com>
Fri, 4 Jul 2014 02:57:56 +0000 (10:57 +0800)
committerxxm <xxm@rock-chips.com>
Fri, 4 Jul 2014 02:57:56 +0000 (10:57 +0800)
arch/arm/boot/dts/rk3036.dtsi

index 04023ec9a76b550dd0fcaf5845152ef6827234cb..a971bb204e664727fadb5404e757563a2ffc7383 100644 (file)
                bus-width = <4>;
        };
        gpu {
-                     compatible = "arm,mali400";
-                     reg = <0x10090000 0x10000>;
-                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
-                           <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
-                                                  <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
-                         interrupt-names = "GP", "MMU", "PP";
+               compatible = "arm,mali400";
+               reg = <0x10091000 0x200>,
+                         <0x10090000 0x100>,
+                         <0x10093000 0x100>,
+                         <0x10098000 0x1100>,
+                         <0x10094000 0x100>;
+               reg-names = "Mali_L2",
+                                       "Mali_GP",
+                                       "Mali_GP_MMU",
+                                       "Mali_PP0",
+                                       "Mali_PP0_MMU";
+
+           interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+           interrupt-names = "Mali_GP_IRQ", 
+                                                 "Mali_GP_MMU_IRQ", 
+                                                 "Mali_PP0_IRQ",
+                                                 "Mali_PP0_MMU_IRQ";
          };
 
 };