Fix expansion of vsetcc to set the high bit for true instead of 1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61129 91177308-0d34-0410-b5e6-96231b3b80d8

diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 3a99a256cccd00b6e5cb856a2e3b439457a331fe..18ba9125d12a9116d9c0ed54d2a44bdbcbc3e0c3 100644 (file)
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -3144,10 +3144,12 @@ SDValue SelectionDAGLegalize::LegalizeOp(SDValue Op) {
         SDValue In1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
                                   Tmp1, DAG.getIntPtrConstant(i));
         Ops[i] = DAG.getNode(ISD::SETCC, TLI.getSetCCResultType(In1), In1,
-                              DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
-                                          Tmp2, DAG.getIntPtrConstant(i)),
-                              CC);
-        Ops[i] = DAG.getNode(ISD::SIGN_EXTEND, EltVT, Ops[i]);
+                             DAG.getNode(ISD::EXTRACT_VECTOR_ELT, TmpEltVT,
+                                         Tmp2, DAG.getIntPtrConstant(i)),
+                             CC);
+        Ops[i] = DAG.getNode(ISD::SELECT, EltVT, Ops[i],
+                             DAG.getConstant(EltVT.getIntegerVTBitMask(),EltVT),
+                             DAG.getConstant(0, EltVT));
       }
       Result = DAG.getNode(ISD::BUILD_VECTOR, VT, &Ops[0], NumElems);
       break;